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"Steven K. Knapp" wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F00FDD2.C74022BD@yahoo.com... > > "Nicholas C. Weaver" wrote: > > That is a good point about the tools. I forget that the XC3S is only > > supported in webpack in the XC3S50 now and I think only up to the > > XC3S400 in the next release. I honestly don't get the idea of selling > > very low cost chips and not adding them to the free tools. > > Personally, I agree with your statement and have been trying to convince the > powers that be to add additional Spartan-3 devices to WebPack. The folks > responsible for WebPack are concerned about the total download size. The > larger devices have multi-MB support files. If the size of the download is the issue, there are very simple ways to address that. One is to split the download into two parts, one for the current configuration and one for the added support for the larger devices. The other is just to ship the CD as you already do. I don't think adding all the chips will blow away a CD will it? As it is, I don't think it is very practical to ask a user to download a 150 MB file. At least it is not practical for me to download it. > > But good luck getting a price on the XC3S1000 at this point. The > > XC3S1000 parts have been pushed back due to design problems and will not > > be out until Q1 or perhaps later. The XC3S400 and one of the larger > > parts will be out in 4Q03 according to their schedule. > > Hmm. Engineering samples of the XC3S1000 and XC3S50 are available today. > The engineering samples have the part number XC3S1000J and XC3S50J to > distinguish them from the production devices. This may be the reason you > were quoted longer delivery. The non-'J' devices are due out in 4Q2003. > The non-'J' version of the XC3S50 also includes block RAM, embedded > multipliers, and 2 Digital Clock Managers (DCMs), which the XC3S50J does > not. I have been told that the 50 and 1000 have a design problem with 3 volt tolerance and have been pushed back from late Q3 or early Q4 to 1Q04. The other two or three chips due out in Q4 (including the XC3S400) are now the first chips to be available in full production. I am having a lot of trouble getting straight information and this is what I currently have in print! If this is not correct, I really need to know now! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57526
hello, i want to capture 2 mbps serial data stream through my ethernet card. i already have a Virtex FPGA based hardware and I want to add it this data logging funtionality. I want to use FPGA to convert the received serial data into ethernet format and dump it onto the ethernet interface. Then i can use some port sniffer to capture that data. i just have the vague idea. kidly someone tell me, how much is this feasible. also, i need to know where i can find the most relevant helping material. Regards, Amir AminArticle: 57527
>or shoudl i get started with writing my own ARM compiler (but would >take ages (: ) NetBSD runs on ARM systems. It's using the gnu tool chain. from gcc -v: Using builtin specs. gcc version 2.95.3 20010315 (release) (NetBSD nb3) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 57528
Peter -- I have no problem with the fact that these are 2 seperate product lines which target 2 different needs, but when Xilinx states that "Spartan-3 is basically Virtex-II, but whith a few things missing", I think Xilinx ought to be considerate of it's customers and enumerate EXACTLY what those ".... few things missing" are. To paraphrase John Cooley (Synopsys & EDA Gadfly): Customers can accept virtually any truth about a product as long as they don't have to find out about it painfully. I'm not asking for "champagne on a beer budget". What I am saying is: I've spent a good amount of time studying champagne (Virtex-II), but I don't have a lot of time right now to study beer (Spartan-3) from scratch. Since Xilinx claims to be making beer by subtracting a few things from champagne, Xilinx can save me a LOT OF TIME by just telling me what those few subtractions are, and then I can quickly figure out if beer is what I need. My management is experiencing a little sticker shock right now at the cost of champagne, but if I get them hooked on the cost of beer, and we discover that beer can't quite satisfy our tastes 6 months from now, that will be an enormous source of grief & embarrassment that I want to avoid. Can you comment on my list? Additions? Corrections? "Peter Alfke" <peter@xilinx.com> wrote in message news:3F0200FB.FF77F1E8@xilinx.com... > Xilinx has two major product lines. Virtex is for performance and > features, Spartan is for low cost. Otherwise, the architectures are very similar. > > That gives us a chance to really optimize each line. The Spartan > developers reduce the cost, accepting that this makes their devices > non-optimal for certain applications, but there is always Virtex to > deliver higher functionality and performance (at a higher price). > The Virtex designers can optimize functionality and speed, knowing that > this might increase the cost, but there is always Spartan to satisfy > less performance-critical, but more cost-sensitive applications. > > There is no free lunch, in engineering almost everything is a trade-off. > But everybody still asks for champagne on a beer budget :-) > Peter Alfke > ======================= > Luiz Carlos wrote: > > > > > > I'm not complaining, and I know that Xilinx wil not make a special > > Spartan3 just for me. But I have the right to express what I think, > > and maybe I'm not alone. Maybe there are a lot of Luizes and Rays, > > maybe Xilinx will hear us and maybe, at these nanometer scales where > > the pads are so big, to have all the CLBs configurable as memory is > > not so significant in silicon area. > > > > Luiz Carlos Oenning Martins > > KHOMP Solutions >Article: 57529
Matt <> wrote: : Greetings, <p> I am having a strage time with some code I recently wrote to implement a UART - the code is working fine now, but a problem cropped up that is baffling me. This design is being synthesized in Xilinx ISE 5 and implemented into a Spartan-II XD2S50 device. I'm on something of a learning curve with things right now so please go easy on me! :D <p> when 10 => -- Stop Bit <BR> : BitPos := 11; -- next is holding pattern for breaks <BR> Formatting postings in ASCII and not in HTML makes them more readable and enhances the chances for answers. As does a valid reply addrss. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57530
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F027B39.A0E8DD68@yahoo.com... > "Steven K. Knapp" wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3F00FDD2.C74022BD@yahoo.com... > > > "Nicholas C. Weaver" wrote: > > > That is a good point about the tools. I forget that the XC3S is only > > > supported in webpack in the XC3S50 now and I think only up to the > > > XC3S400 in the next release. I honestly don't get the idea of selling > > > very low cost chips and not adding them to the free tools. > > > > Personally, I agree with your statement and have been trying to convince the > > powers that be to add additional Spartan-3 devices to WebPack. The folks > > responsible for WebPack are concerned about the total download size. The > > larger devices have multi-MB support files. > > If the size of the download is the issue, there are very simple ways to > address that. One is to split the download into two parts, one for the > current configuration and one for the added support for the larger > devices. The other is just to ship the CD as you already do. I don't > think adding all the chips will blow away a CD will it? As it is, I > don't think it is very practical to ask a user to download a 150 MB > file. At least it is not practical for me to download it. > There's little doubt that multiple optional download parts is the most elegant solution - along with the possiblity of getting everything on CD for those that want that. However, the current WebPack is so large that a few extra megabytes for extra part support would not make a significant difference. And anyway, are there many companies with the resources to be involved in fpga design, but without a permanent internet connection? Even if it's a bit slow, you can always leave a download running overnight.Article: 57531
William LenihanIii wrote: > I'm not asking for "champagne on a beer budget". What I am saying is: > I've spent a good amount of time studying champagne (Virtex-II), but > I don't have a lot of time right now to study beer (Spartan-3) from > scratch. As has been said before in the group, one of the best features of Xilinx datasheets was the section on 'how this part differs from the last generation.' Is that too complex for management to get it?Article: 57532
Peter Alfke wrote: > I cannot understand that at all. If the question is ventilated in > public, it should be answered in public. Unless the answer is very > embarrassing... It's like sex - can be embarrassing at first for the strongest soul, but once you get the habit... Someone at Altera should take a vow to answer _every_ question for, say, a week. We will all applaud. To paraphase Blackadder on airplanes: "I treat my Usenet questions like I treat my women. Climb aboard twice a day and fly them up to heaven."Article: 57533
> There is no free lunch, in engineering almost everything is a trade-off. > But everybody still asks for champagne on a beer budget :-) > Peter Alfke French champagne, please! :) Luiz CarlosArticle: 57534
> Alvin Andries wrote: > > > What about the minimal 24 MHz clock frequency for the DCM or does it only > > apply to the output clock frequency? "Peter Alfke" <peter@xilinx.com> wrote in message news:3EF87F9F.2967F506@xilinx.com... > Good question, and you gave the right answer yourself: > In frequency synthesis the incoming frequency is multiplied by M/D, and > only the output frequency must be >24 MHz. > Good catch... If you needed a lower frequency couldn't you always generate a power of two multiple of it, and then divide that down? -- glenArticle: 57535
> After all, > you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very > possible that the S3s will run faster even with the added delays. It doesn't look like (using the projected speeds for MicroBlaze). > I am sorry if my "nagging" is annoying. But I have watched a lot of > changes in FPGAs and have often felt they were not for the better. But > somewhere around the Virtex or VirtexII parts I started to realize that > I needed to forget about how the parts were different and focus on how > to solve my design problems using them. With that I have come to > understand that often what I saw as a limitation is more than made up > for in other areas. I am sure that Xilinx does not remove functionality > without considering the trade offs very seriously. It's ok. Maybe some day we can take a drink and talk about this. Better, let's invite Peter, he can pay that french champagne! (I like beer too) :) Luiz CarlosArticle: 57536
Hi all! I'm trying to make a hard macro of a design and I got that error: FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file start property read <0xffffcacc> Seems like the FPGA Editor tool has problems with POWER and GND connections (see former post http://groups.google.com/groups?selm=72480649.0210271033.535836f4%40posting.google.com) In my case, that gnd/pwr connections are inferred by the synthesis tool, and it's not easy to get rid of them. My question is if this problem is solved in the ISE 5.2 version? Does it worth to upgrade the tool? Other ideas of overcome this problem? Are there anyone having the same problem? Thanks, Santi ------------------------------------ Santiago Esteban Zorita Electric and Electronic Engineering dept. University of Strathclyde santi@eee.strath.ac.uk ------------------------------------Article: 57537
Hi everyone, Iam basic to the communication design, I have a query regarding NRZ interface with FPGA, Can we provide NRZ interface to FPGA, how does the voltage level will be at the interface ? Is it like 1 --> + V 0 --> -V ? Is it possible to interface it with FPGA? Thanks in Advance.Article: 57538
Hello, The synthesis tool is identifying your signal as clock and instantiating a clock buffer. This has to be loc'ed to a gclkiob. If you do not want the synthesiser to instantiate clock buffer, in the synthesis options under the 'Xilinx specific options' tab, specify zero in the 'number of clock buffer' field. This will prevent the tool to instantiate clock buffers on its own. The properties will show this if you have the 'show advanced properties' set in the preference in the edit menu. Sandeep <hamish@cloud.net.au> wrote in message news:3f015fc6$0$23112$5a62ac22@freenews.iinet.net.au... > Thomas <tom3@protectedfromreality.com> wrote: > > ERROR:MapLib:93 - Illegal LOC on symbol "pin_cpuphase2" (pad > > signal=pin_cpuphase2) or BUFGP symbol "pin_cpuphase2_bufgp" (output > > signal=pin_cpuphase2_bufgp), IPAD-IBUFG should only be LOCed to GCLKIOB > > site. > > > > so, apparently it wants that signal to be on a GCLKIOB; what would be the > > workaround to use this input as a clock without going through one of the > > gclkiob pin? > > You need to use a simple IBUF instead of an IBUFG. Your synthesis tool > is probably trying to be helpful. You may have to instantiate the IBUF. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57539
<guest> schrieb im Newsbeitrag news:ee7e625.-1@WebX.sUN8CHnE... > Hi everyone, > Iam basic to the communication design, > I have a query regarding NRZ interface with FPGA, > Can we provide NRZ interface to FPGA, > how does the voltage level will be at the interface ? > Is it like 1 --> + V > 0 --> -V ? > Is it possible to interface it with FPGA? > Thanks in Advance. This is not a question of NRZ, ist a quaestion of signaling voltage level. TTL 0-5V LVTTL 0-3.3V RS232 +/-12V etc. So the FPGA can only output/input voltage levels stated in the datasheet. -- Regards FalkArticle: 57540
Hi all, here is a quit simple, general question: Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for their FlipFlips? + This would reduce the power for the clock tree. + I could directly use the Data from an external DDR-DRAMArticle: 57541
Hi Folks I am currently experiencing problems with a PBGA PCB and was wondering if anyone encounter this before. The PCB was developed by external company and it is connected to a switch mode power supply (flyback). The power supply switches between two input voltage supply, 28V and 7.2V where the outputs are two 5V and two 3V3. When the 28V and 7.2V are switched on, the PBGA is power up but when the 28V is turned off, the PBGA writes information to a memory and power down. The 7.2V supply is used to power the memory, a 24-bit counter, an oscillator and a crystal. The problem is the output of the PBGA seem to be producing a 1HZ pulse which is expected when the 28V is on but not expected when the 28V is turned off. The 1HZ pulse has a amplitude of 2V when the 28V is off but when the 28V is on, the amplitude is 5V. I have tested the power supply stand-alone and it works perfectly. When the 28V is off, the PBGA power should be zero but in this case, the voltage is 1.4V when connected to the PCB. Could someone explain the effects that I am experiencing. Thanks PaulArticle: 57542
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:bdrmtf$101fja$1@ID-84877.news.dfncis.de... > > <Marlboro> schrieb im Newsbeitrag news:ee7e56e.2@WebX.sUN8CHnE... > Hi Petter, > The speed is very slow, data is updated every 33 ms or so but the clock is > 50 mhz, I think there would be no problem... > > In this case you should consider using a serial adder. Uses much less > ressources. Without more description it would be hard to say. If the whole design could be implemented serially it would make a lot of sense. If a parallel 48 bit output is needed, then deserializing the result will make it more complicated. It is interesting what people used to do. I remember a description of the PDP-8s, a PDP-8 implemented with a serial ALU. -- glenArticle: 57543
> I cannot understand that at all. If the question is ventilated in > public, it should be answered in public. Unless the answer is very embarrassing... Embarrassment has nothing to do with it. I personally think that this newsgroup is the wrong place to attack the competitor's products -- in general, I think both X & A are pretty well behaved, pointing out our strong points instead of directly pointing out weaknesses in our competitor's products. In a personal email, there is much more freedom to say what I feel like and to venture off into opinion from fact. Plus, if I'm not 100% sure, I can just say so and follow-up later when I find out the full answer; in the newsgroup, you can look pretty silly when you do so (speaking from experience...). Most of us who post here from Altera are in the R&D side of the company, so we're usually unaware of product positioning or the "company line" on certain issues. When in doubt, I rather just reply offline while I wait for a response from the apps folks. Regards, PaulArticle: 57544
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<omuMa.1725$zn2.469105682@twister1.starband.net>... > > The non-'J' version of the XC3S50 also includes block RAM, embedded > multipliers, and 2 Digital Clock Managers (DCMs) > While you're adding things, any chance of sneaking the real differential input terminators ( LVDS_25_DT, LDT_25_DT, etc. ) of the V2Pro into the S3 ? Brian P.S. And I'd personally love to see some TBUF's - Xilinx seems to have forgotten that not only did they provide (the illusion of) tristate buffers, but also dedicated chip-spanning routing for wide multi-source buses without tying up routing resources. Although their demise was not unexpected, given that they'd already been chopped off at the knees in V2 by providing TBUF's at a vertical pitch that didn't match the carry chain pitch. For V3(??), how about a full set of TBUFs every N columns, instead of a half set in every column?Article: 57545
dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0306271328.8bb2ef4@posting.google.com>... > hello. > > i'm just getting started to learn fpga and i'm interested in dsp > design in fpga. > what small projects do you recommend to start with? > i need to define small projects so that i have goals, rather than > studying without any target. > > thanks! Have a look at http://tutor.al-williams.com -- we have several free PLD tutorials there including info on Xilinx, Altera, Verilog, etc. Al Williams AWCArticle: 57546
Hello, I am implementating Fixed point signed multiplication. Is there a algorithm to implement it. I have done the usual method of multiplication i.e partial products ...shift and add method. But its very slow. If you know any algorithm which will faster do mention. Any reference will be great. How does the signed multipliers in xilinx that fast. what algorithm do they use. I need to first implement in on MATLAB and see the result. waiting for reply praveenArticle: 57547
I too have been contacted thru email everytime that my Altera ng questions were not replied to in the group. Altera seemed to put alot of thought into the answers. It would be nice if they replied to the group to share the knowledge, except that maybe my questions were too specific to be helpful to others. -- Pete > Steve Casselman wrote: > > > > What you should really do is count the number of times someone from Xilinx > > has answered questions on the NG and the number of times you see someone > > from Altera (or other vendors) answer any questions. I think you will see it > > is about 100 to 1. A question about Xilinx will almost always be answered > > where as a question about Altera will only be answered by some other user. > > So basically you see more Xilinx questions because users know they will get > > an answer by someone who knows what they are talking about. You can't say > > that about Altera. > > Except that I often am contacted by Altera directly rather than here in > public. I can understand why they would do that. I think you will also > find that very recently there are a lot more posts here from Altera. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57548
> The issue is not the software, it's the testing. With thousands of > device/package/speed > grade combinations, plus the platforms and OSs, plus all the EDA > interfaces we support, > there are millions of possibilities that need to be tested. Since the > Spartan software was > high quality, and we didn't want to destabalize it with enhancements > needed for newer > architectures, we decided to freeze the Spartan software. This allows > us to focus our > testing efforts where they are needed most. I am a bit surprised that with software this complex that there was no way to de-couple the various parts. I am sure Xilinx does a lot of testing on their software, but I am always amazed when I find a bug that is known about and it takes them several major releases to fix it. My favorite was VHP__0854 The expression can not be converted to type std_logic_vector. That bug was there forever and finally fixed in 4.x. We currently hold 7 Xilinx licenses that cost us about $10K a year to maintain. With Xilinx claiming to be best in class I expect more. I find it interesting when I had called the Xilinx hotline that they said there was no way to get the older software. It's not an issue for us as we maintain them. For others this may be a problem. The bigger problem is that we have some parts that we use that requires us to keep an old Window 95 PC setup just to support the old software. Plus, we don't get to leverage the newer interfaces as they are developed. Instead we are forced to remember how to use the old tools. This costs us time and money. Thanks for picking up Synplicity. We use their full tools. Fast, don't drop support, and best of all, their tools work.Article: 57549
> > As for maintaining multiple versions of the software > on the same computer, I have found that VMWARE (www.vmware.com) > is a very good solution. I basically set up a virtual computer > for each version of the software, and each is kept separate > and there are no conflicts. Costs a few GBytes of disk, which > these days is only a few $. Good advice, but it addresses they symptom, not the root problem. I don't want to have to work around what Xilinx is doing. I want them to do a better job for us.
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Compare FPGA features and resources
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