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"Josh Pfrimmer" <yeah_spam_me@thisaddress.com> writes: > Regarding LEON-2, can anybody tell me the differences between versions > 1.0.10 and 1.0.11-XST? > > Obviously the 1.0.11 version is intended for synthesis with Xilinx XST, but > what are the specific differences that that necessitates? There's this tool called "diff"...Article: 52576
dnnout@yahoo.com (J.G.) wrote: > Ok for my senior design class id like to build a digital voice/sound > recorder. [..] > I wanted to know if it would be possible to do > this project using a fpga (sorta like a dsp). It is possible and allready done. http://www.ra.informatik.uni-stuttgart.de/Leon/ shows a digital dictation machine on a Virtex XCV800 using a Leon-core. I know that there are further designs based on this, but they don't seem to be freely accessable by the web. bye ThomasArticle: 52577
Ruth, I've just discovered this and have used it. As the design block I'm doing now though is something that is just triggered and it runs for thousands of clock cycles I've resorted back to the Quartus simulator for now (which has now begun to work again - the results window was massively zoomed in and wouldn't zoom out, unless I selected the zoom command on the menu and explicitly entered a time range). I'll bear in mind the testbench angle although my limited experience of ModelSim suggests to me that it isn't the most usable tool I've ever come across. Also the loose integration of these 3rd party tools with Quartus is not ideal. I've noticed that one of the other FPGA companies (Actel maybe) mentions that they have a complete integrated system from them which does strike a cord with me I must admit. I've only ever used Altera so maybe I should be looking at other manufacturers anyway. Thanks for your comments. Rog. "Ruth" <ruthsims@hotmail.com> wrote in message news:ff5ada4a.0302120756.70df990e@posting.google.com... > I take it that you have already tried to export your vwf files as a > vht file and used the vht file as the testbench in modelsim to get you > started?Article: 52578
Hello again, I'm still messing about with the simulator side of things. I can see the point of a complex test bench approach for a traffic router say (this was an example mentioned by another person on the news group) where different packets need to be constructed and fired at the logic but for simpler stuff, I still think a timing diagram is needed. My current design is accessing an SSRAM with image data which is very fiddly and I think a timing diagram is the only way to go in this case. Rog. "Ruth" <ruthsims@hotmail.com> wrote in message news:ff5ada4a.0302120735.78817c28@posting.google.com... > > Yes, I know what you mean and although you can move the label around, the > > pin stays on the side. Annoying. > > ......and what a daft way to design it :-) > > > It's interesting that you use VHDL and graphical entry. This is the way I do > > designs as I like a graphical top level although I think it's not the done > > thing anymore (for some reason). > > I think it makes it easier to see the structure of the design even > though its more time consuming, and in any case my project manager > wouldn't be happy without a picture. > > > I'm glad your Quartus hangs up now and again as well. It's obviously not my > > fault! Maybe later versions will improve its reliability. > > > > I'm having problems with simulation. Which simulator do you use? > > Either Quartus for little bits and pieces or ModelSim for verifying > larger bits of code. > > RArticle: 52579
> I'm still messing about with the simulator side of things. I can see the > point of a complex test bench approach for a traffic router say (this was an > example mentioned by another person on the news group) Me again :-) > where different > packets need to be constructed and fired at the logic but for simpler stuff, > I still think a timing diagram is needed. My current design is accessing an > SSRAM with image data which is very fiddly and I think a timing diagram is > the only way to go in this case. Roger, You can have timing information in a testbench :-). It is even better than that because you can gave a generic input to the testbench which selects whether max/min timing values are being used for your Ram etc. You can also incporporate board delays etc. Even for the simplest designs I'd recommend a testbench and modelsim. Some editing tools (eg emacs) will generate a simple testbench round a design at the touch of a button. For those of us who don't have three joints in each finger and who use a 'normal' editor a perl script can do the same thing. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52580
Hi, I am thinking of attaching an application specific coprocessor to the OCM or PLB interface of the PowerPC CPU in a Xilinx-II Pro device. My questions are: 1. which interface is best suited for low latency communication between CPU and a CPU-external (but FPGA-internal) instruction register of a coprocessor? 2. how many cycles do I need to write or read to/from such a register? 3. which fequency can be achieved at OCM and PLB? Thanks Heiko -- --------------------------------------------------------------- Dipl. Ing. H. Kalte | HEINZ NIXDORF INSTITUTE | Office: F1.213 System and Circuit Technology | Fon: +49 (0)5251 60-6459 Fürstenallee 11 | Fax: +49 (0)5251 60-6351 33102 Paderborn, Germany | --------------------------------------------------------------- mailto:kalte@hni.uni-paderborn.de http://wwwhni.uni-paderborn.de/sct/ --------------------------------------------------------------- Home of the RAPTOR Rapid Prototyping Systems http://www.RAPTOR2000.de/ ---------------------------------------------------------------Article: 52581
Hello, I'm new to this group and Xilinx: please forgive me if this is a stupid question. I'm building a 16KByte RAM on a Spartan IIE, without CoreGen (as I'm using the WebPack ISE at the moment). I've organised this as a stack of 32 512x8 BRAMs, with 8 32-way MUXes on the data outs. I could use the address decoding to ENABLE each BRAM with a common WRITE line, or vice versa, or both. Any idea which is preferable? Many thanks MattArticle: 52582
Anyone have experience with using the Xilinx CORDIC v1.0 in atan mode? Following is the behavior I've seen when using it. There is a newer version (V1.1) which would require me to upgrade to newer (ISE 5.1) software. So far, I haven't been able to get a confirmation that the new version is fixed. Anyone know for sure?: CORDIC core version 1.0 has some unexplained behavior when used as an atan function. For the following discussion, assume 16 bit (rectangular) inputs and (phase - scaled radian) output, where each number is given first as a decimal number followed by its binary floating point representation in 1QN or 2QN format: X_IN Y_IN PHASE_OUT -4100 (-0.25) 3900 (0.238) 30785 (3.75) -4000 (-0.25) 4000 (0.244) 18432 (2.25) 11900 (0.726) 12100 (0.739) 14358 (1.75) 12000 (0.732) 12000 (0.732) 2048 (2.611) Ignoring the fact that the outputs often are greater than 1 (which can easily be fixed by discarding the whole number part), it is obvious that there are large discontinuities at certain points. I've found that the following workaround equation gives a useful output: phase_out <= raw_phase_out(15) & raw_phase_out(15) & raw_phase_out(15) & raw_phase_out(14) & raw_phase_out(11 downto 0); While sign extending over bits 14 and 13 makes sense since these two bits are the whole number part of the 2QN output format, replacing bit 12 with bit 14 makes no sense at all. Is this a known problem in the core? Will this workaround work for all inputs? Thanks, Doug MillerArticle: 52583
On Fri, 14 Feb 2003 12:38:20 +0000, Matthew Warren <warren@hep.ucl.ac.uk> wrote: >Hello, >I'm new to this group and Xilinx: please forgive me if this is a stupid >question. > >I'm building a 16KByte RAM on a Spartan IIE, without CoreGen (as I'm >using the WebPack ISE at the moment). > >I've organised this as a stack of 32 512x8 BRAMs, with 8 32-way >MUXes on the data outs. > >I could use the address decoding to ENABLE each BRAM with a common WRITE >line, or vice versa, or both. >Any idea which is preferable? How about using 32 4kx1 BRAMs, with 8 4-way MUXes on the data outs? These muxes will be smaller and faster than your 32-way ones. Regards, Allan.Article: 52584
On Thu, 13 Feb 2003 14:45:49 -0800, Austin Lesea <austin.lesea@xilinx.com> wrote: >All, > >I have it on good authority (ie the folks who know!) that early fab lots had >slower than allowed IO transistor performance. Please open the case on the >hotline for prompt resolution. > >Austin > Austin, I already have a case open and Xilinx Support has been helpful and responsive. They had not mentioned the possibility that my parts might be from one of these slow lots, but I've just asked them to let me know how to identify those lots. -Brian.Article: 52585
Matthew Fowle <thefowle@wam.umd.edu> wrote in message news:<3E49BF9D.4F4029A3@wam.umd.edu>... > Been a long time microcontroller man, but I'd really like to start > getting into fpga's. Can anyone recommend good starting places? Good > books? > > Thanks > Matt I had the same experience -- lots of micro and discrete digital, but it took me a while to make the plunge into programmable logic. You can find my experiences with Xilinx and Altera in (free) tutorial form at http://tutor.al-williams.com Regards, Al Williams AWC http://www.al-williams.comArticle: 52586
Hello, My need is fulfilled by telling Modelsim to break for a given severity level. But first, I also thought of using Mr Andraka's method. Yet there is a small problem: if the signal assignment is in a "if rising_edge(clk)" statement (e.g. in a FSM), the signal value will only be set for the next clock cycle, a little to late in some cases... Maybe using a variable instead would do it, but how do I define a global variable inVHDL that is easily usable by all VHDL modules? In a package maybe? Yours, FB "Ray Andraka" <ray@andraka.com> a écrit dans le message de news: 3E4B95E0.799629BA@andraka.com... > This comes up from time to time. As long as you don't have processes inside > your UUT that go without a clock from the outside (such as some pll models), you > can stop simulation by causing all the processes to wait indefinitely. Stop the > clocks, and you will stop all clock dependent processes. Here is how to stop > them > > > process ( > begin > if end_sim then > wait; > end if; > clk<='1'; > wait for 5 ns; > clk<='0'; > wait for 5 ns; > end ; > > Then in your stimulus process > if stop_condition > end_sim<=true; > end if;Article: 52587
I'm providing input to our marketing group for literature on our our latest PMC boards with Virtex IIs on them and want to make sure we use the right terminology for our abilities with respect to reconfiguring the FPGAs. We support reconfiguring the Virtex directly from PCI, as well as reprogramming the onboard configuration eeprom and forcing the Virtex to reconfigure from it. I'm a bit worried that the terms "dynamic reconfiguration" and "on the fly reconfiguration" may imply that we do partial reconfiguration, which we have yet to look into or play with. So, are the terms "dynamic" and "on-the-fly" OK and is "partial" the only word to be concerned about using? Finally, is doing a partial reconfig more of an issue with the actual FPGA load itself, or the load tools, or both? I.e. if we can do full reconfigs from PCI, does that imply we can do partials as well? ----- Ron Huizen BittWareArticle: 52588
I the Xilinx programming interface is available at all times you can say the board supports just about anything you want. It would be nice if you could do readback as well as configuration. All the other buzz words are really software/use issues. Steve "Ron Huizen" <rhuizen@bittware.com> wrote in message news:3E4D39FA.3A64120B@bittware.com... > I'm providing input to our marketing group for literature on our our > latest PMC boards with Virtex IIs on them and want to make sure we use > the right terminology for our abilities with respect to reconfiguring > the FPGAs. > > We support reconfiguring the Virtex directly from PCI, as well as > reprogramming the onboard configuration eeprom and forcing the Virtex to > reconfigure from it. I'm a bit worried that the terms "dynamic > reconfiguration" and "on the fly reconfiguration" may imply that we do > partial reconfiguration, which we have yet to look into or play with. > > So, are the terms "dynamic" and "on-the-fly" OK and is "partial" the > only word to be concerned about using? > > Finally, is doing a partial reconfig more of an issue with the actual > FPGA load itself, or the load tools, or both? I.e. if we can do full > reconfigs from PCI, does that imply we can do partials as well? > > > ----- > Ron Huizen > BittWareArticle: 52589
"Steve Casselman" <sc@vcc.com> writes: > > more useful were focused on > > shortening reconfiguration times. > > and processes are swapped in and out. It would be nice to have a 32 bit > configuration interface. Todays systems are 8-bit external and 32-bit > internal (or 100s of bits if you count a frame as the internal bit length). Or be able to swap frames of config bits config<->BRAMs. That is then 1000s of bits parallel. With them many BRAMs in VII that should go possible without adding more resources (just a bit of config control circuits), so long one only exchanges smallish sections. > > machines is a great application, but it seems a ways off before > > its ready for the masses of programmers writing software that manipulates > > hardware in realtime. > > No I don't believe so. Really just a case of the appropriate compiler. Anything that can be automated that way gets quickly used if it is usefull. But it first has to go through the possibilities discovery phase. Computers started around 1950. And took until 1970 to settle. Microprocessors stated then, and were stable about 1990. FPGAs OTOH have largly avoided even getting into that phase. > > I can see your vision, but with the Xilinx 6000 demise, (too early to > market?) > > as an example, potential backers of open bitstream fpga architectures > > should think long and hard. > The real problem with the 6200 was logic size and performance. Yup. Them small 3-input fixed function multiplexers requirded lots to get anywhere. And with small chips (64x64 array in 6216) one has roughly 32x32 LUTs, so about 2/3 XC2S50. Small. And with 2 rows of multiplexers per bit for an sensible data path and without carry logic, all arithmetic was very slow. Same problems killed Atmels AT6000. > There is perceived value in having your > hardware > > designs distributed in a traditional confusticated form Look into the VII DES encryption, for those that are paranoid[1]. [1] That is in its "mentally defect" meaning. Intels customers have not died from i188 and i386 machine code being public. Dito Motorolas from 680x0 and PPC being known. > Someday I > believe that we will look at hardware designs as programming Every FPGA interested person I know personally already does believe that. Of course programmers as beginner FPGA designers produce awfull messes, but so they did on their first processor program. And some will learn in time. And then someone writes a FPGA HOWTO with an "pitfalls" section, and the rest also get it. > and accept that > fact that you can disassemble a program if you really want to. And most likely will never do it, no more than it is done with most computer programs[2]. Better uses for time[3]. [2] And when, it is usually customers trying to patch an bug. [3] That is why open source designs are the way to go. Users incresingly demand this. > While I'm not > saying FPGA companies should abandon their current business models they > should think about designing a device that is supposed to be programmed and > understood by programmers. Some device that understands that it will have to > fetch pieces of hardware over and over an OS that understands that computing > is both changing hardware and changing software. A separate device just for the open crowd will not sell. Else Xilinx would have kept 6200 alive and grown it to larger sizes. > It seems like every 20 years we start to have break throughs of this kind. > In the 60's real computers were programmed by real programmers that > programmed in assembly. In the 80's power DSP programmers programmed power > applications using only assembly. And in between in the 1970s hobbyists took microprocessors that were intended for industrial control and started the PC revolution from them. Much to Intels and Motorolas surprise. > In the '00's we have creative engineers > creating magic using hardware programming tools. Yup, annother revolution just waiting to be happen. > In the end clever people > found how to capture that expertise and interpret computer languages so > average people could do what use to take the top 5% burning the candle at > both ends to accomplish. Yes. And the more of the creative people get a chance, the faster one of them is going to hit the right combination. Who of the Fortran and Algol (about VHDL and Verilog level development) toting people in the 1960s would have made or predicted C? It took an bunch of outsiders at AT&T to do it, the last ones anyone would have asked. > To really do this you need to publish the data so you can have 1000's of > people working on it instead of just the people you pay. Exactly. > company D that published all the data would win in the market place. This is > because other companies and individuals would work to provide tools and > might do things company D or C did not think of (like timing driven place > and route) and that would make a difference. And expecting then to go the "NDA -> closed source -> firm" route immediately gets rid of all individuals without interest in becoming vendors. And so a large amount of talent. > But of course I'm just one dude with a dream. One of thousands of dudes. Don't undersell yourself. Just look at the often reoccurence of this theme every few months. And that is just those that a) come her and b) complain, for triggering. > This kind of stuff will only > come around when companies C and D have customers that want this And managers who regard those customers as important. With other words: see the potential they are offering. Society noticed long ago that science brings more than dogma. Politics noticed long ago that democracy brings more than monarchy. Software is learning that open source brings more than closed source. FPGA manufacturers still seem to be in the stone age in this respect. I repeat my prediction: the first FPGA company to see the light will become the Intel of FPGAs, dominating the rest with an large distance. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 52590
Hi, I am a Grad student at the Texas A&M University Computer Engineering Group. I am doin the FPGA implementation of Kalman filter using VHDL. This filter has around 30 matrix operations like 6x6 Matrix Multiplication, matrix inverse, Determinant of a matrix etc as a part of the Kalman filtering algorithm. I have a strict constraint on the area that my module can occupy. So i have been forced to use a single double precision adder, multiplier and divider for the entire design.. for example, i am using the same adder for doing both matrix addition and also for multiply-add sequence for my matrix multiplier. As a result of this, I have a big state machine with 3000 states. I am not able to synthesize this using the xilinx ISE software. some people suggest that I break down the state machine into smaller state machines. Also it was suggested that I use "one-hot" encoding instead of binary encoding. Now, my doubt is, if I break my code such that it has some 50 state machines, each of which has some 60 small state machine inside, and use two state variables of 50 and 60 bit width and use the "onehot" encoding technique, is it possible that it will work?. please tell me your suggestions. Thanks. Anand RajaramArticle: 52591
Anand, I would suggest you either use a block RAM as a state machine (use the RAM as a lookup table - ROM - for the inputs, outputs, and next state), or use the Microblaze soft processor core (ie program the state machine as a small program for the uBlaze. The advatages of either method is that they both are synchronous, and execute in a predictable fashion (same number of clocks per state in the RAM, code with same number of instructions per state for uBlaze). Personally, I would use the uBlaze approach. For where the uBlaze is overkill (perhaps in this case) there is the even smaller PicoBlaze (or KCMP) which is even smaller. The uBlaze can be programmed in c, which might lead to making timing harder to follow, wheras the pBlaze is programmed in assembly, and you have 100% observability of the process. Austin Anand Kumar Rajaram wrote: > Hi, > I am a Grad student at the Texas A&M University Computer Engineering > Group. I am doin the FPGA implementation of Kalman filter using VHDL. > > This filter has around 30 matrix operations like 6x6 Matrix > Multiplication, matrix inverse, Determinant of a matrix etc as a part of > the Kalman filtering algorithm. > > I have a strict constraint on the area that my module can occupy. So i > have been forced to use a single double precision adder, multiplier and > divider for the entire design.. for example, i am using the same adder for > doing both matrix addition and also for multiply-add sequence for my > matrix multiplier. > > As a result of this, I have a big state machine with 3000 states. I am not > able to synthesize this using the xilinx ISE software. some people suggest > that I break down the state machine into smaller state machines. Also it > was suggested that I use "one-hot" encoding instead of binary encoding. > > Now, my doubt is, if I break my code such that it has some 50 state > machines, each of which has some 60 small state machine inside, and use > two state variables of 50 and 60 bit width and use the "onehot" encoding > technique, is it possible that it will work?. please tell me your > suggestions. > > Thanks. > Anand RajaramArticle: 52592
Sounds like a candidate for a lookup table approach, but 3000 states is extreme for any single state machine. So before you do that I'd try the suggestions that you partition it into multiple smaller state machines. With matrix operations it also seems like most of the state transitions could be encoded using one or more counters that are controlled/enabled by your master state machine. For example, when you do a 6x6 matrix multiplication you can sit in one master state while a counter counts 0-35, then jump to the next state. If you need to do N consecutive 6x6 matrix multiplications then have counter A count 0-35, then increment counter B, clear counter A, and start over. When counter A reaches 35 and counter B = N-1 the N matrix operations are complete and you can sit in one master state during the whole thing. I hope that gives you some ideas. Robert "Anand Kumar Rajaram" <anandr@ee.tamu.edu> wrote in message news:Pine.GSO.4.21.0302141630060.12903-100000@eesun1.tamu.edu... > > Hi, > I am a Grad student at the Texas A&M University Computer Engineering > Group. I am doin the FPGA implementation of Kalman filter using VHDL. > > This filter has around 30 matrix operations like 6x6 Matrix > Multiplication, matrix inverse, Determinant of a matrix etc as a part of > the Kalman filtering algorithm. > > I have a strict constraint on the area that my module can occupy. So i > have been forced to use a single double precision adder, multiplier and > divider for the entire design.. for example, i am using the same adder for > doing both matrix addition and also for multiply-add sequence for my > matrix multiplier. > > As a result of this, I have a big state machine with 3000 states. I am not > able to synthesize this using the xilinx ISE software. some people suggest > that I break down the state machine into smaller state machines. Also it > was suggested that I use "one-hot" encoding instead of binary encoding. > > Now, my doubt is, if I break my code such that it has some 50 state > machines, each of which has some 60 small state machine inside, and use > two state variables of 50 and 60 bit width and use the "onehot" encoding > technique, is it possible that it will work?. please tell me your > suggestions. > > Thanks. > Anand Rajaram > >Article: 52593
Anand Kumar Rajaram <anandr@ee.tamu.edu> wrote: > As a result of this, I have a big state machine with 3000 states. I am not > able to synthesize this using the xilinx ISE software. some people suggest > that I break down the state machine into smaller state machines. Also it > was suggested that I use "one-hot" encoding instead of binary encoding. did you implement the MUL operation using pure states instead of a counter. if yes, you can reduce the number of states by using a counter to represent sequence of states in a operatoin: use loop instead of listing all the array elements one-by-one if you have already done this, it's helpless to reduce the states unless you re-design your algorithm > Now, my doubt is, if I break my code such that it has some 50 state > machines, each of which has some 60 small state machine inside, and use > two state variables of 50 and 60 bit width and use the "onehot" encoding > technique, is it possible that it will work?. please tell me your > suggestions. no matter how many *small* FSMs you break, the results wont help: size and speed. using onehot FSM will generate a 3000 stages shift register. My suggestion is to re-design the state machine to reduce/merge states. If this is not possible, may be micro-coding can help you. > Thanks. > Anand Rajaram -- Tsoi Kuen Hung (Brittle) CSE CUHKArticle: 52594
Hi Anand,
This really does not sound like a traditional state machine
type problem. Contraindications include the very large
number of states [1], multiple complex sequences [2] that are
repeated multiple times [3], a single shared resource [4] that
is required by multiple mutually (in time) exclusive
sub-sequences.
[1] 3000 states
[2] 6x6 Matrix Multiplication
matrix inverse
Determinant of a matrix
[3] around 30 matrix operations
[4] single double precision adder
multiplier
divider
This really sounds like a problem which would best be served
by a microcoded solution, with a microcode memory that might
be 1000 locations of maybe 30 to 40 bits each. This could
support conditional branches, subroutines (mat mul, etc),
and of course looping.
For an into to microcoded architectures, look at
http://www.cs.clemson.edu/~mark/uprog.html
Mick, John. And J. Brick, "Bit-Slice Microprocessor Design,"
New York: Mcgraw-Hill, C1980 ISBN 0-07-041781-4 in 1980
White, D. E., "Bit Slice Design: Controllers And ALUs,"
New York: Garland Stpm Press, C1981.
ISBN 0-8240-7103-4
Amazingly this is also available on-line for free
http://www10.dacafe.com/book/parse_book.php?article=BITSLICE/index.html
You should also consider something like Xilinx's free Pico-Blaze
processor as the driver for this, (you could consider it a
prebuilt microcoded core)
Good luck with this project,
Philip Freidin
On Fri, 14 Feb 2003 16:36:51 -0600, Anand Kumar Rajaram <anandr@ee.tamu.edu>
wrote:
>Hi,
> I am a Grad student at the Texas A&M University Computer Engineering
>Group. I am doin the FPGA implementation of Kalman filter using VHDL.
>
>This filter has around 30 matrix operations like 6x6 Matrix
>Multiplication, matrix inverse, Determinant of a matrix etc as a part of
>the Kalman filtering algorithm.
>
>I have a strict constraint on the area that my module can occupy. So i
>have been forced to use a single double precision adder, multiplier and
>divider for the entire design.. for example, i am using the same adder for
>doing both matrix addition and also for multiply-add sequence for my
>matrix multiplier.
>
>As a result of this, I have a big state machine with 3000 states. I am not
>able to synthesize this using the xilinx ISE software. some people suggest
>that I break down the state machine into smaller state machines. Also it
>was suggested that I use "one-hot" encoding instead of binary encoding.
>
>Now, my doubt is, if I break my code such that it has some 50 state
>machines, each of which has some 60 small state machine inside, and use
>two state variables of 50 and 60 bit width and use the "onehot" encoding
>technique, is it possible that it will work?. please tell me your
>suggestions.
>
>Thanks.
>Anand Rajaram
>
Philip Freidin
Fliptronics
Article: 52595What is the purpose of Xilinx Flex License Utility? I have it with my Xilinx ISE 4.2i. What part of Xilinx ISE that needs Flex License Utility? Thanks!Article: 52596
> I'll bear in mind the testbench angle although my limited experience of > ModelSim suggests to me that it isn't the most usable tool I've ever come > across. Also the loose integration of these 3rd party tools with Quartus is > not ideal. I've noticed that one of the other FPGA companies (Actel maybe) > mentions that they have a complete integrated system from them which does > strike a cord with me I must admit. I've only ever used Altera so maybe I > should be looking at other manufacturers anyway. Roger, I suggest you download the evaluation version of the activeHDL simulator. www.aldec.com Its a rival to ModelSim (and costs a similar amount though is extremely cheap for academia) I think you will find it more Altera 'point and click' than Modelsim and my personal preference is it is generally more productive. One specific point you raise is the simulation of timing diagrams. AHDL lets you draw the waveforms using stimuli definitions that you can see (and you can draw directly in the waveform window if you want) and will then create a VHDL testbench with exactly those signal transitions at a press of a button. Its of limited use when you go to bigger projects, but for the level you describe its perfect as its an automatically generated halfway house. Within the free 10 day trial you should get the hang of things. I find that you use AHDL to do design entry and debugging/simulation and let it use its preconfigured links with Quartus synthesiser/Place and route to make use of Quartus in the background transparent. (There are a few quirks etc particularly if you use Leonardo for synthesis and Quartus just for P&R but for your simple project you probably won't encounter them.) Good luck PaulArticle: 52597
If you have the ISE and not the webpack, only modelsim needs the flex license. I don't know if webpack has a flex license. Giuseppe "Kyle Davis" <kyledavis@nowhere.com> ha scritto nel messaggio news:z2m3a.2848$A95.79@newssvr19.news.prodigy.com... > What is the purpose of Xilinx Flex License Utility? I have it with my Xilinx > ISE 4.2i. > What part of Xilinx ISE that needs Flex License Utility? > Thanks! > > >Article: 52598
Alphaboran <alphaboran@yahoo-no-spam.com> wrote: > I just received the new version of the Xilinx Foundation tool. I now use the > 4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express > 3.6.1. My target devices are Virtex-EM. > > Are there any good reasons to upgrade my system? Does the new tool offer > something really new and useful? More accurate timing data for the devices you are using? You should always use the most accurate data for your devices, which usually means using the latest tool versions. In my experience 4.1i was quite poor - 4.2i is much better and is well worth the upgrade. I have a mixed reaction to 5.1i so far. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 52599
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