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Does anyone know of a good line counter that can count VHDL lines, and ignore VHDL comments. Preferably from command line, and with multiple files. Thanks. AlbaArticle: 53401
Hi, maybe an Altera guy is reading this newsgroup as well and can give some recommendations for Altera FPGAs during power up. Best regards, Thorsten "Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag news:3E6F8C12.40766C6@xilinx.com... > Jim, > > By the way, since this discussion is about something I am familiar with, none of this > information should be applied to any other non-Xilinx FPGA product. > > See below, > > Austin >Article: 53402
Thanks Kevin reply, please correct me if I am wrong this time :
1) The parity generator doesn't take PAR ( itself ) as an input
2) If the number of '1's on AD[31:0] and C/BE[3:0] is even then PAR = 0, else PAR =1
By the way I am trying to implement a "master only", so during address
phase I have to generate PAR. It's 64 bit, 66 MHZ { as fast as I can : )
Article: 53403> I bought while ago two FPGA from Altera, they are called APEX and > ACEX, their distributor sent me both FPGA, but... they came without > memory, i have talked to them and they said they could sell me memory, > and it is almost as expensive as FPGA. They gave me this prices: > > EPC1PC8 or EPC2LC20 for EP1K50,(ACEX) > EPC2LC20 for EP1K100.(APEX) > > EPC2LC20.Altera > -price 21,59 eu. > - This one is JTAG programable. > > EPC1PC8.Altera. > -price 7,12 eu. > > Are this good prices ? Add sending and taxes...its in euro, almost > like dollar. > > Anyways, it's the first time i buy this things, i don't know if they > are being nice or being too smart...what do you think ? > > Could I use another memory for my FPGA ? What tipe would you recommend > me ? You could use a normal Flash (like 512Kx8 for about EUR 3) and a small PLD (adds some more EUR) and configure the FPGA from that. There are some application notes for this. The simplest design (mine :-) uses ACEX in parallel mode and fits in an EPM7032 (all 32 macrocells used). But the only problem is that you have to download some design into your FPGA to program the flash. I'm using a soft core processor (my JOP Java Processor) for that task. Or you have to struggle with JTAG... You can find the schematics for this with ACEX under: http://www.jopdesign.com/board.html and the VHD files for the PLD under: http://www.jopdesign.com/download.html Hope this helps, MartinArticle: 53404
I will make the answer as simple as your question: Synchronous. "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message news:<b4mu54$20hp84$2@ID-159866.news.dfncis.de>... > hi, > which reset is better synchronous or asynchronous > > thanks > lijoArticle: 53405
You can call a mechanical drawing at XILINX. Into Protel is very simple to drawing the footprint using the component PCB wizard. Powermos -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Mike Hubert" <mph@xiphos.ca> ha scritto nel messaggio news:Xns933C7B4221699mphxiphosca@142.77.1.194... > John Larkin <John.Larkin> wrote in > news:4rnu6v0dj3kjlpmegovi7fb2o88g3roeop@4ax.com: > > > > > What do you mean by 'footprint source'? If you want the CAD layout, > > what file format? > > > > John > > > > > > By source I mean someone who can kindly pass it along to me, or a company > from which I can purchase it. > > I use Orcad Layout, so if you're offering me a footprint, you could send me > a library file, that'd be awesome. I could potentially also deal with > Protel format... > > mph@xiphos.ca > > THANKS!!! > > Mike. > >Article: 53406
Hi Pepito,
I have a similar problem with Xilinx proms. My solution is to use a
EEPROM from atmel to program during development and to use a
one-time-programmable EPROM part for production. The EEPROM saves a lot
of hassle in development but the cost is about $20 US. The OTP part is
only about $3. This is for a Spartan2E 50K gate part. Yours will be
different but the price difference should be similar. The flash part from
Xilinx is even higher. The Atmel EEprom and the xilinx OTP part are
pin-for-pin compatible.
Theron Hicks
Pepito Perez wrote:
> Hello,
>
> I bought while ago two FPGA from Altera, they are called APEX and
> ACEX, their distributor sent me both FPGA, but... they came without
> memory, i have talked to them and they said they could sell me memory,
> and it is almost as expensive as FPGA. They gave me this prices:
>
> EPC1PC8 or EPC2LC20 for EP1K50,(ACEX)
> EPC2LC20 for EP1K100.(APEX)
>
> EPC2LC20.Altera
> -price 21,59 eu.
> - This one is JTAG programable.
>
> EPC1PC8.Altera.
> -price 7,12 eu.
>
> Are this good prices ? Add sending and taxes...its in euro, almost
> like dollar.
>
> Anyways, it's the first time i buy this things, i don't know if they
> are being nice or being too smart...what do you think ?
>
> Could I use another memory for my FPGA ? What tipe would you recommend
> me ?
>
> Thank you !
Article: 53407alba nohi wrote: > Does anyone know of a good line counter that can count VHDL lines, and > ignore VHDL comments. Preferably from command line, and with multiple > files. the unix command grep -v "^[:space:]*--" filename.vhd | wc -l will give you a count of non-comment lines for a specific vhdl file. Operating over multiple files is left as an exercise for the reader. Rgds, JohnArticle: 53408
CC Nguyen wrote:
>
> Thanks Kevin reply, please correct me if I am wrong this time :
>
> 1) The parity generator doesn't take PAR ( itself ) as an input
>
It depends up on the meaning of a parity generator is (Sounds
familiar???).
If I assume that a parity generator is some logic that generates the
parity of AD[31:0] and C/BE#[3:0], and then outputs the result as PAR,
then yes, the parity generator doesn't take PAR as an input.
The time PAR becomes an input is when you are comparing the parity of
AD[31:0] and C/BE#[3:0] to PAR during a target write cycle (address
phase and data phase), the address phase of a target read cycle, or the
data phase of an initiator read cycle (After the target claim the
transaction.).
> 2) If the number of '1's on AD[31:0] and C/BE[3:0] is even then PAR
> 0, else PAR =1
>
That's correct, since a parity generator is constructed out of
XOR gates.
> By the way I am trying to implement a "master only", so during address
> phase I have to generate PAR. It's 64 bit, 66 MHZ { as fast as I can :
> )
Unless you are designing a host bridge, I don't believe it is
possible to have an initiator (master) only PCI device.
I don't know what your target technology is, but 66MHz PCI is very very
hard to do because you only got 3ns for the setup time.
If you are targeting an SRAM FPGA, considering using Virtex-II or
Virtex-II Pro.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Article: 53409John Williams wrote: > alba nohi wrote: > >> Does anyone know of a good line counter that can count VHDL lines, and >> ignore VHDL comments. Preferably from command line, and with multiple >> files. > > > the unix command > > grep -v "^[:space:]*--" filename.vhd | wc -l > > will give you a count of non-comment lines for a specific vhdl file. oops, that will also count blank lines, which you probably wouldn't want. try something like grep -v "^[:space:]*$" filename | grep -v "^[:space:]*--" | wc -l a true unix hacker could probably fold those two reg exps into one, but it will work nonetheless. Counting the number of semicolons in a VHDL file would also give you a rough complexity metric. Going further, a google search on "vhdl complexity metric" also turns up some interesting links. Followups set to comp.lang.vhdl JohnArticle: 53410
Cool, I've got it... About the "master only", yes, we are building a "host bridge" for video recording/playback system, actually there're only 2 devices on the PCI bus, one is the FPGA (the master) and the other will be the storage device (a SCSI hard drive with PCI - SCSI "bridge"). I've just started it for a week, get simple things first like the arbiter, parity generator : ) will dig deep into the configuration and the initiator machine later, thanksArticle: 53411
"john jakson" <johnjakson@yahoo.com> wrote in message news:adb3971c.0303111811.5737b3ac@posting.google.com... (snip question about TTL and ESD protection) > > In fact TTL was so tough as old boots, there are Fairchild stories > that Chinese fabs used to make ripoff TTL in fabs where the air > conditioning was an open window. > > By the way this is the wrong NG, and the wrong century. Which newsgroup do you suggest, comp.arch.ttl? -- glenArticle: 53412
Martin Schoeberl wrote:
<snip>
> You can also 'make' a 1+fractional diode out of a transistor and two
> > resistors,
> > as a Vbe multiplier, (and get some Ron slope control from the Hfe )
> > so that should you find 2.3 Diode drops is ideal, it can be be simply
> > arranged.
>
> Can you explain this a little bit for me?
>
> Martin
In this Vbe multiplier circuit :
3.3V -+-- R1 -----+-----R2-----+----- Rg---- GND
| | |
+---------C B E ---------+----> Out
npn Trx
R2 will turn on TRX when Vbe is across it.
If R1=R2, you have two diode drops C-E,
if R1 = 1.5 x R2 you have 2.5 diode drops etc.
Rg stops R1,R2 pulling Out too high, at no loads.
For the TRX a SOT23 will do, choose one with good gain
at > 1A.
Or, this lazy regulator :
3.3V -+-- R1 -----+-----R2--------- GND
| |
+---------C B E -------------> Out
npn Trx
R2/R1+R2 sets Vb, R1=R2 gives 1.65V Vb, and appx
1V on the Emitter load.
Vb can go close to 2V, on a 1.5V FPGA Vcc
Also talked about was LM317
+---> Out
+-----R1-----+----- R2---- GND
| |
3.3V -----------I O R ---------+
LM317 {FAN1084) etc
These have a min load of some mA, which may be a issue, but
have a (much) lower output impedance than the TRX above.
R2 can probably be 0 ohms, for assist applications, which
will have nom 1.2V on load.
A suitable drive device > 1A, will be in a large package.
-jg
Article: 53413I have a project which need sto interface to a system with fairly rigid timing specs. As a result I need to delay my signals coming that way a certain number of nS whiich is not a multiple of any clock I have in the chip. Is there any way I can add some propagation delay/gate delay and not have it optimized out by the XST tools. Or alternatively, is there a way to specify not only the max delay between signals, but also the min one? Thanks for any suggestionsArticle: 53414
Is this kind of what you have in mind? I have been doing synchronous
resets for a while, but based on your post, I bullet proofed it a
little...
Here is a component that takes an asynchronous reset and asserts it
asynchronously, but deasserts it synchronously.
library ieee;
use ieee.std_logic_1164.all;
entity rst is
port (reset_in : std_logic; -- asynchronous reset input
reset_out : std_logic; -- synchronous reset output
clock : in std_logic -- system clock
);
end rst;
architecture behavior of rst is
signal r1 : std_logic;
begin
process(reset_in, clock)
begin
if reset_in = '0' then
r1 <= '0'; -- clear asynchronously
reset_out <= '0';
elsif rising_edge (clock) then
r1 <= reset_in; -- dual rank synchronnise
deassertion of reset
reset_out <= r1;
end if;
end process;
end behavior;
Clyde
Mike Treseler wrote:
> LIJO wrote:
>
> > which reset is better synchronous or asynchronous
>
> Asynch reset/preset is directly supported in FPGAs
> and has the advantage of sure recovery
> of critical outputs from a panic state.
>
> An synchronous deactivation of the reset pulse
> is cleanest.
>
> Consider handling "illegal" register values
> gracefully in your logic rather the depending on reset values.
>
> -- Mike Treseler
Article: 53415Hello Abdul, You should have the documentation as well. There is a descriptive examples and step by step instruction for that examples in FPGAdv. Read through and do it (do the examples in FPGAdv), you should gain a lot of info. rgds, Basuki Keren -----Original Message----- From: AbdulMoeed [mailto:abdul@students.iiit.net] Posted At: Monday, March 10, 2003 5:21 AM Posted To: fpga Conversation: VHDL & FPGA Design tools Subject: Re: VHDL & FPGA Design tools Hi, I am using HDL Design Browser that comes with FPGA Advantage(Mentor Graphics). In that I think we need to, for a new project, create a new library called work or temp and add all the vhdl source files to it. Also we need to add our own personal library to the above library as a child. Also we need to add the stardard libraries like mgc_portable to our project library as a child. So can anyone tell me how do I do that because when I try to add mgc_portable it gets opened as an independent library and not as a child of library work/temp. When I try to compile my project(design) with mgc_portable not as a child of work using ModelSim it gives error saying that the library mgc_portable not found. So someone please really help me. I am using FPGA Advantage for the first time and am stuck at this point since 4 days. Thank You, AbdulmoeedArticle: 53416
The fact remains that a scanning matrix may determine efficiency in the process in the presense of coefficients solved in terms of freedom. The only issue with respect to such notions is that a consulting engineer gets paid half the rate in the same time as a managerial consultant and therefore exist in relation at the same rate as such knowledge that's preserved by an organization. Patrick Meuser ----------------- 'Every good idea has a past implementation' "J. Michael Milner" <jmmilner@wideopenwest.com> wrote in message news:3E66BD67.5B82AAC9@wideopenwest.com... > I agree with all you've said but the sad fact is that you are, by your own > words, "a consulting engineer" and American firms have long ago been sold on > the notion that "a managerial consultant" is the expert on the subject under > discussion. They'll suggest you pay someone outside who has special knowledge > but can't see how paying somebody inside to gain, apply, and retain the same > special knowledge works. I assume this must mean that the only thing that can be > assigned a dollar value is the result of applying special knowledge, not the > cost of gaining or the value of retaining the same. > > Mike Milner > MIT BSEE, UofI PhD CS > 25 years at Bell Labs > downsourced 2001 > > Roger Lascelles wrote: > > > > As a consulting engineer I see a lot of money wasted on buying in outside > > expertise - some of that money paid to me ! > > > > I can't count how many times I get asked to start a job then half way > > through the customer dumps the job. The customer gets zero return on the > > money spent and no-one inside the company benefits from the knowledge > > gained. > > > > My theory is that you should "own" your workers : they work in your time on > > your equipment under your roof. Look after your workers so they stay and > > build up a bank of knowledge - especially in your company's core area. > > > > Outsourcing is best when specialist expertise is needed. > > > > I have seen companies which are short of cash scrape together enough money > > to pay some outsider for a specific job - and get very little in return. > > Much better to search for a very productive, adaptable, enthusiastic, bright > > person who will enrich the company in the long term. Put a lot of effort > > into recruiting. > > > > Roger > > > > "TI" <anglomont@yahoo.com> wrote in message > > news:18a34598.0303041845.33b150a0@posting.google.com... > > > Hello > > > we are an ASIC/FPGA company currently understaffed but with a very > > > limited budget; so I wonder under what circumstances and what type of > > > projects(non crucial?) we could consider outsourcing to some(which?) > > > developing country team? > > > Thanks > > > MAArticle: 53417
Hello, I am just wondering if it is possible to write a single byte in memory, then write another single byte right next to it. Normally I would pre-append two bytes into a word of 32 bit wide, then do a single write to the memory. But is it possible to write it byte by byte, instead all at once. Assuming 32 bit memory bus width. Thanks, JimmyArticle: 53418
Hi all, where can I get or buy the 'good old' simple JTAG Download Cable type "Parallel Cable III"? Xilinx does support it but does not sell it anymore ... markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 53419
From my meagre knowledge of FPGA designs, adding delays to any signals is bad, bad, bad (a case could probably be argued for use in asynchronous systems, but I'm not the one to argue it)... what you need is more handshaking between the two systems. What about doubling your clock speed, or double edge triggering? adrian Igor Orlovich <igoro@hotmail.com> wrote in message news:sJRba.8853$Gk2.5234@twister.nyroc.rr.com... > I have a project which need sto interface to a system with fairly rigid > timing specs. As a result I need to delay my signals coming that way a > certain number of nS whiich is not a multiple of any clock I have in the > chip. Is there any way I can add some propagation delay/gate delay and not > have it optimized out by the XST tools. Or alternatively, is there a way to > specify not only the max delay between signals, but also the min one? > Thanks for any suggestions >Article: 53420
Why don't you build one yourself? It will, for a start, be between 50 and 100 times cheaper, and should only take you about half an hour or so to put together (just need a couple HC125 tristate buffers)... the schematic is floating around somewhere... adrian Markus Meng <meng.engineering@bluewin.ch> wrote in message news:3e7035f9_4@corp.newsgroups.com... > Hi all, > > where can I get or buy the 'good old' simple JTAG Download Cable > type "Parallel Cable III"? > > Xilinx does support it but does not sell it anymore ... > > markus > > -- > Mit freundlichen Grüssen > Markus Meng > > P.S. Achtung wir haben eine neue FAX-Nummer > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ** Web www.meng-engineering.ch ** > ******************************************************************** > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 53421
If you are looking for a longer answer ;-) read this: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets_rev1_1.pdf Regards Jens alba nohi wrote: > I will make the answer as simple as your question: Synchronous.Article: 53422
Hello
I'm working on a research project that use Xilinx Virtex FPGA,
I use the Coregen tool to generate multiplier, it works very well.
But I wonder where can I find the details about the structure
of the multiplier.
Thanks for any advance.
Article: 53423
hi Martin
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote
> I don't expect such a transient in normal operation of the FPGA. Should I?
I guess not, because it's unusual to power-down big chunks of an
FPGA. On the other hand, big CPUs exhibit spectacular supply
current transients in normal operation. Linear Technology's
excellent newsletter has often had articles on how to cope with
that sort of problem, as they have lots of parts targeted at the
CPU power regulator market. I think they keep it archived on
their website.
> > I wonder if your 2-diode-and-resistor arrangement could be
> > replaced with some crude but fast linear regulator
[...]
> Good idea. Do you mean something like LM317 (or one of its successor like
> xx1117)?
Not really. Those devices have big and comparatively slow regulation
feedback loops. I was thinking of something much cruder and less
accurate, maybe based on a couple of bipolar transistors.
> I don't know if these linear regulators have problems with the
> reverse voltage.
Needs to be considered, but probably not a problem with the low
voltages in question.
>And it's a little bit more space and price (but not so much).
Really not much at all, I think. But of course, any extra
component is bad news these days :-)
I'll fool around with PSPICE over the weekend ("analog" is a
dirty word in my day job!) and perhaps post something next week.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 53424Peter Alfke <peter@xilinx.com> wrote: > > which reset is better synchronous or asynchronous > > Synchronous is better if: could you be so kind and explain why you (and others in thios thread) think that synchronous reset ist better? Reset is IMO a feature to ensure, your cirquit starts in a deterministic behavior and when ever necessary can be put back in this state by an external controller. Especially during power up, you have no garantie of a determinsitic clock so you lack a deterministic synchronous reset, while an asynchronous reset during powerup is very easy. No I like to know, what drawbacks exist, that I don't have in mind. bye Thomas
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z