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Greg Steinke wrote: > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<TP5aa.79536$AV5.998926@news.chello.at>... > > I've built a board with the Cyclone from Altera. First board was ok, but on > > some of the following there was a problem with startup of the Cyclon. > > > > For the core voltage (1.5V) I use a drop-down regulator from Linear > > Technology (LTC3405) as described in the app. note (AN257). But the core > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I > > examined the problem by building an extern regulator. > > > > Starting the regulator without load and than attaching the VCCINT pins from > > the FPGA leads to a successfull start. The output capacitor (4u7) supplies > > enough initial current. > > > > Measuring the current during startup yields to following results: > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and > > staying there for about 15 us (I think for internal startup). After that it > > dropps to a few mA. > > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. It > > can not deliver this peak current during it's own start. > > > > Just wanted to tell this story (of hidden problems of a new family) for > > others who want to work with this new (still exciting) FPGAs to not run into > > the same troubles. > > > > Martin Schoeberl > > Martin, > The highest power-up current requirement that we have characterized > for the Cyclone family is 420 mA. This is more than the LTC3405 can > supply, and we are modifying AN257 accordingly. Also, we will document > the requirement for power-up current in the Cyclone datasheet. Can you also include an appx model of the effect, and some scope plots of both Icc and Vcc, for various dV/dT's ? - that would help designers avoid this on the first pass. Austin Lesa also suggested the lowest temp is not always the highest Icc point ( currently their data sheets suggest -40..-0'C is the worst corner) - can you add notes on temp corners for Altera devices. > I'm not sure why you are seeing more current than we saw - in some cases the > decoupling caps can also take some transient current as they charge > up, but I would not think that this would be 300 mA. Cap transients can be > 300mA, but they have a different curve shape. eg Switching 5uF into 1uF of distributed decoupling should give an 'instant' step to 5/6th of 5uF voltage, and then a recovery from there. -jgArticle: 53451
On Wed, 12 Mar 2003 17:08:00 GMT, Mike Hubert <mph@xiphos.ca> wrote: >John Larkin <John.Larkin> wrote in >news:4rnu6v0dj3kjlpmegovi7fb2o88g3roeop@4ax.com: > >> >> What do you mean by 'footprint source'? If you want the CAD layout, >> what file format? >> >> John >> >> > >By source I mean someone who can kindly pass it along to me, or a company >from which I can purchase it. > >I use Orcad Layout, so if you're offering me a footprint, you could send me >a library file, that'd be awesome. I could potentially also deal with >Protel format... > Doesn't Orcad Layout have a pad array generator? In my DOS PCB386 it takes few minutes to bang out a large array footprint. -- Regards, Boris Mohar Viatrack Printed Circuit Designs Aurora, OntarioArticle: 53452
No its not the diligent board, it is my own board design, but i have 6 header pins on it (very close to the device) for the JTAG.(is this what you mean by parallel cable header?) These connect using wires to my cable schematic which is connected to a serial (ie not ribbon) cable to my parallel port. pat "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1047562681.664309@skink.ru.ac.za>... > Yes... you might start by using a parallel cable...or are you just talking > in generic terms? (I presume you are still plugging into parallel port on > CPU!). Does your board have the parallel cable header on it? If you are > going to make the header, probably a good idea to put it as close to the > chip as possible. The length of the cable shouldn't make much of a > difference, as long as you don't set the JTAG clock too quickly (and cause > packet collisions...). What board are you using? Is this by any chance the > digilent board? (plugging a "serial" cable into the board sounds very > familiar) > > adrian >Article: 53453
Jim Granville wrote: > > > Cap transients can be > 300mA, but they have a different curve shape. > eg Switching 5uF into 1uF of distributed decoupling should give an > 'instant' step to 5/6th of 5uF voltage, and then a recovery from there. > Also: i/C = dV/dt which means 0.3A/3uF = 0.1V/us That means, it takes <10 microseconds to charge the capacitor to a meaningful voltage. Peter AlfkeArticle: 53454
I have used this pay for service before and it was a great time saver. They handle three CAD packages, Allegro, Orcad and Protel 99 916 Design http://www.916design.com/ sbpcd@cox.net 1-805-560-9021Article: 53455
Peter Alfke <peter@xilinx.com> wrote in message news:<3E6F61A8.3FD1010D@xilinx.com>... > LIJO wrote: > , > > which reset is better synchronous or asynchronous > > Synchronous is better if: > the chip offers this feature and you can afford the potential loss of > other input variables, > and > you can afford to wait for the reset action to be delayed until after > the next clock edge. > > These conditions are often not met. That's why there are so many > asynchronous resets. > > Peter Alfke, Xilinx Applications Peter, Does Xilinx provide a way to check timing when coming out of an async reset to any affected destination components (often D inputs on FF's, or inputs on BRAMs)? If not, what does Xilinx recommend for insuring that you successfully come out of async reset every time? Overconstrain the net delay of the async reset net? Thank you, MarcArticle: 53456
Maybe try Chameleon POD. Our Chameleon POD is about $150.-, but with the same hardware you can use our following free configuration: ParallelCableIII - all xilinx ByteBlaster - all Altera and more Wiggler - processor like ARM PPC XSCALE TRISCEND STRONGARM BDM ONce Raven - our new config, yes, completly Raven McGraigor compatible ISP - for all AVR and other ups I2C_passive - for all I2C based EEPROM and other I2C device I2C_active - ... All these config are coming for free. Your will config the Chameleon POD with our Chameleon-Colors freeware. (). More, buying Chameleon, you will receive all documentation to use the Chameleon as a CPLD CoolRunner demo kit. Very usefull. (coming with SPP EPP and a part of ECP core) On the last revision, we had a true 1284 transceiver on it :-) ! As you are coming from Switzerland, I can send you one for test. Regards, Laurent Gauch www.amontec.com Your FPGA Design Partner Markus Meng wrote: > Hi all, > > where can I get or buy the 'good old' simple JTAG Download Cable > type "Parallel Cable III"? > > Xilinx does support it but does not sell it anymore ... > > markus > > -- > Mit freundlichen Grüssen > Markus Meng > > P.S. Achtung wir haben eine neue FAX-Nummer > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ** Web www.meng-engineering.ch ** > ******************************************************************** > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 53457
Falk Brunner wrote: > "Giuseppeł" schrieb im Newsbeitrag > news:b4q49b$227b6i$1@ID-61213.news.dfncis.de... > > >I fix a similar problem with IJC-2 JTAG cable in the follow mode: > > > >In my board I've put a capacitor of 100pF nearest the TDO pin. > >Then I've open the JTAG interface and remove the capacitor labeled C1. > > > >In my opinion the R9-C1 filter is too big. > > > IMHO the schematics of the parallel-III cable is a little bit senseless. I > added two Schmitt triggers (74HC14) BEFORE the TCK line. The input to the > first schmitt-trigger is filterd by a RC filter consisting of 330 Ohms > and 1 > nF. This works well on a 3m long cable. Since there are 4 more buffers > free > inside the chip, I buffer TDI and TMS the same way. But TCK (which becomes > CCLK in serial slave mode) is by far the most critical signal. So keep the > connetion from the 74HC125 (tristate driver) to the TCK pin on the board > short, lets say < 10cm (4 inch for the non-SI guys ;-) > > -- > MfG > Falk > > > > Maybe try Chameleon POD. Our Chameleon POD is about $150.-, but with the same hardware you can use our following free configuration: ParallelCableIII - all xilinx ByteBlaster - all Altera and more Wiggler - processor like ARM PPC XSCALE TRISCEND STRONGARM BDM ONce Raven - our new config, yes, completly Raven McGraigor compatible ISP - for all AVR and other ups I2C_passive - for all I2C based EEPROM and other I2C device I2C_active - ... All these config are coming for free. Your will config the Chameleon POD with our Chameleon-Colors freeware. (). More, buying Chameleon, you will receive all documentation to use the Chameleon as a CPLD CoolRunner demo kit. Very usefull. (coming with SPP EPP and a part of ECP core) On the last revision, we had a true 1284 transceiver on it :-) ! As you are coming from Switzerland, I can send you one for test. Regards, Laurent Gauch www.amontec.com Your FPGA Design PartnerArticle: 53458
Hi Greg, just a question. I cannot find AppNote 257 on the Altera Website. Thorsten "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag news:5c1de958.0303130813.2724eca7@posting.google.com... > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<TP5aa.79536$AV5.998926@news.chello.at>... > > I've built a board with the Cyclone from Altera. First board was ok, but on > > some of the following there was a problem with startup of the Cyclon. > > > > For the core voltage (1.5V) I use a drop-down regulator from Linear > > Technology (LTC3405) as described in the app. note (AN257). But the core > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I > > examined the problem by building an extern regulator. > > > > Starting the regulator without load and than attaching the VCCINT pins from > > the FPGA leads to a successfull start. The output capacitor (4u7) supplies > > enough initial current. > > > > Measuring the current during startup yields to following results: > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and > > staying there for about 15 us (I think for internal startup). After that it > > dropps to a few mA. > > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. It > > can not deliver this peak current during it's own start. > > > > Just wanted to tell this story (of hidden problems of a new family) for > > others who want to work with this new (still exciting) FPGAs to not run into > > the same troubles. > > > > Martin Schoeberl > > Martin, > The highest power-up current requirement that we have characterized > for the Cyclone family is 420 mA. This is more than the LTC3405 can > supply, and we are modifying AN257 accordingly. Also, we will document > the requirement for power-up current in the Cyclone datasheet. I'm not > sure why you are seeing more current than we saw - in some cases the > decoupling caps can also take some transient current as they charge > up, but I would not think that this would be 300 mA. > Later posts indicate that you have solved this problem. If you have > any other questions about this feel free to contact me. > Sincerely, > Greg Steinke > Altera Corporation > gregs@altera.comArticle: 53459
IIRC, the old timing analyzer(I think back to Xact6), it did not analyze the reset path
through a flip-flop's async reset pin to its output and then to the next flip-flop's D
input. It has been quite a while since I had to use async resets in that manner, not sure
if the current tools trace that path or not.
Marc Randolph wrote:
> Peter Alfke <peter@xilinx.com> wrote in message news:<3E6F61A8.3FD1010D@xilinx.com>...
> > LIJO wrote:
> > ,
> > > which reset is better synchronous or asynchronous
> >
> > Synchronous is better if:
> > the chip offers this feature and you can afford the potential loss of
> > other input variables,
> > and
> > you can afford to wait for the reset action to be delayed until after
> > the next clock edge.
> >
> > These conditions are often not met. That's why there are so many
> > asynchronous resets.
> >
> > Peter Alfke, Xilinx Applications
>
> Peter,
>
> Does Xilinx provide a way to check timing when coming out of an
> async reset to any affected destination components (often D inputs on
> FF's, or inputs on BRAMs)?
>
> If not, what does Xilinx recommend for insuring that you successfully
> come out of async reset every time? Overconstrain the net delay of
> the async reset net?
>
> Thank you,
>
> Marc
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53460For the special case of going active after the end of configuration, there is an option to synchronize this not to CCLK, but rather to the user clock. If that clock is slow enough, all asynchronous reset operations will be terminated before the next clock edge. For the more general case, and when several asynchronous clocks are being used, we leave the resynchronizing job to the user. There are just too many clever ways to do this, and so many trade-offs. Peter Alfke Marc Randolph wrote: > > Pe> Peter, > > Does Xilinx provide a way to check timing when coming out of an > async reset to any affected destination components (often D inputs on > FF's, or inputs on BRAMs)? > > If not, what does Xilinx recommend for insuring that you successfully > come out of async reset every time? Overconstrain the net delay of > the async reset net? > > Thank you, > > MarcArticle: 53462
Thank you all !! I have understand that I could use some variety of circuits with parts that I already have at home, and the project is not to be a commercial project, so I have no worries about dealing with the cheapest memory. I'll try to use a microcontroller instead of buying that *overpriced* memory. Thank you all very much and for the links too !! If I have some trouble I'll report it. -- *FPGA Project* Free Altera Demo Board kolja@bnl.gov (Kolja Sulimma) wrote in message news:<25c81abf.0303130903.747a2523@posting.google.com>... > For 15? you get a Fujitsu micrcontroller with 256KByte Flash. > For 30? you get a 64MHz, 32-Bit Processor with 768kB Flash. > Price for a single piece, no lead time. > > You can write your own software to make it JTAG-programmable, or you > implement PPP and upload your bitstreams via FTP ;-) > > Does anybody besides me think that the FPGA configuration flash-ROMs > are overpriced? > > Kolja Sulimma > > zumbita00@yahoo.es (Pepito Perez) wrote in message news:<441d2f16.0303121138.568f4a23@posting.google.com>... > > Hello, > > > > I bought while ago two FPGA from Altera, they are called APEX and > > ACEX, their distributor sent me both FPGA, but... they came without > > memory, i have talked to them and they said they could sell me memory, > > and it is almost as expensive as FPGA. They gave me this prices: > > > > EPC1PC8 or EPC2LC20 for EP1K50,(ACEX) > > EPC2LC20 for EP1K100.(APEX) > > > > EPC2LC20.Altera > > -price 21,59 eu. > > - This one is JTAG programable. > > > > EPC1PC8.Altera. > > -price 7,12 eu. > > > > Are this good prices ? Add sending and taxes...its in euro, almost > > like dollar. > > > > Anyways, it's the first time i buy this things, i don't know if they > > are being nice or being too smart...what do you think ? > > > > Could I use another memory for my FPGA ? What tipe would you recommend > > me ? > > > > Thank you !Article: 53463
I was going to mention that one of the important reasons to avoid async reset is that the tools generally don't provide the level of support that is needed to do it right. >For the more general case, and when several asynchronous clocks are >being used, we leave the resynchronizing job to the user. There are just >too many clever ways to do this, and so many trade-offs. Do the tools provide any help for this tangle? It seems as though there should be a few generally good ways to come out of reset and life would be a lot nicer if the tools knew enough to check. I'd be happy to add tags/markers/whatever if the tools needed some assistance. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 53464
Hi everybody, I may have two (2) dummy questions, but I'd like to see how far are my thoughts on that. 1. How do I can measure the performance of DSP block if its processing time varies depending of the data itselft? By instantiation of a known time response circuit in parallel, i.e., a counter with a strobe signal and stop signal coming from the DSP block after it finishes the crunching. Can it be used? 2. Another case: Having two (2) input path to a main logic block; one of them is having a secundary combinational logic; and the secundary path (or input) does not have any logic at all. How do I synchronize the inputs of the main block? Without clock-gating, maybe with many pipeline registers on the empty path. Then, how do I determine the right number of registers and their clock frecuency. What is the right approach? Again, many thanks friends, and Ray thanks to take from your valuable time to allure our lay questions. JDSArticle: 53465
Peter Alfke wrote: > The classical well-behaved method is to use only one (global) clock, and > use a derived clock enable signal to make sure that the other part only > operates on every fourth clock cycle. > The price is slightly higher clock power consumption (provided you could > lay out the circuit such that you don't run the fast clock all over the place). > > If you use a derived clock, then you end up with two slightly staggered > time domains, which can bite you whenever there is data exchange between > the two domains. ( The obvious loss of performance due to a late-clokced > register driving data into an early-clocked one. The more devious case > is the early-clocked register driving data into the late-clocked > register, violating hold time requirements, and creating a > race-condition mess.) > > Single clock synchronous is best in 99% of the cases... > I have a similar case: a bring into a Virtex2 a 40 MHz clock and I multiply it by 2 (80MHz) with a DLL. For system reasons, I prefere to have 2 domains clocked by DLL outpus CLK0 and CLK2X. There is a unique module where data flow from the 80 MHz to the 40 MHz domain. Now, the documentation says that the outputs of the DLL are well aligned with the input (provided CLKFB is used). No matter how good the DLL is, there is a small mis-alignement between CLK0 and CLK2X. On top of that the separate distribution networks of the 2 clock increase the mis-alignement (skew). The question is if the skew is smaller then the clock-to-Q time of the flip-flops. I couldn't find it on the data sheet. The system seems to run fine in actual hardware, but I haven't done reliability studies. Thanks for commenting, -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 53466
> > Can anyone tell me some spechs for AMD processors in terms of heat > > ranges. I plan on building a system with a 2200 or 2400 CPU and a > > GeForce4200 video card. At this point I am trying to find a case. I > > like the Antec Sonata, but am a little concerned about heat dissapation > > with only one (though large) fan. > > > > I'm looking for ambient system temps, and specific processor temps or > > any other info I can find. Someone using this case (I know it's very > > new) would be great. > > > > Thanks in advance > > > > Art AMD rates the CPU temp at max 85C (90C on hte older Athlons). I bought an Antec 1040II (has two 80mm casefans at the rear), and a Athlon 2000+, with a Falconrock II CPU cooler. _NOT_ using the two casefans made the CPU temp increase (according to the BIOS) by 4C or so. -- Bas Ruiter e-Mail: lordsnow@home.nl www: http://members.home.nl/lordsnowArticle: 53467
Most likely it works as is. If you want to sleep better, you should either • make sure that the 40 MHz clock transition is earlier than the 80 MHz transition, • or artificially delay the data coming out of the 80 MHz domain, • or clock the data out on the falling edge of the 80 MHz clock. Either of these methods avoids any potential hold-time problems, and makes you less reliant on the tight clock-delay matching. Maybe this is "belts and suspenders", but logic is so cheap, and circuits are so fast these days that we can afford this for our peace of mind. Peter Alfke ================ Tullio Grassi wrote: > > I have a similar case: a bring into a Virtex2 a 40 MHz clock > and I multiply it by 2 (80MHz) with a DLL. > For system reasons, I prefere to have 2 domains > clocked by DLL outpus CLK0 and CLK2X. > There is a unique module where data flow from the 80 MHz > to the 40 MHz domain. > Now, the documentation says that the outputs of the DLL > are well aligned with the input (provided CLKFB is used). > No matter how good the DLL is, there is a small mis-alignement > between CLK0 and CLK2X. On top of that the separate distribution > networks of the 2 clock increase the mis-alignement (skew). > > The question is if the skew > is smaller then the clock-to-Q time of the flip-flops. > I couldn't find it on the data sheet. > The system seems to run fine in actual hardware, > but I haven't done reliability studies. > > Thanks for commenting, > -- > > Tullio Grassi > > ====================================== > Univ. of Maryland - Dept. of Physics > College Park, MD 20742 - US > Tel +1 301 405 5970 > Fax +1 301 699 9195 > ======================================Article: 53468
"Greg Steinke" <gregs@altera.com> wrote news:5c1de958.0303130813.2724eca7@posting.google.com... > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<TP5aa.79536$AV5.998926@news.chello.at>... > > I've built a board with the Cyclone from Altera. First board was ok, but on > > some of the following there was a problem with startup of the Cyclon. > > > > For the core voltage (1.5V) I use a drop-down regulator from Linear > > Technology (LTC3405) as described in the app. note (AN257). But the core > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I > > examined the problem by building an extern regulator. > > > > Starting the regulator without load and than attaching the VCCINT pins from > > the FPGA leads to a successfull start. The output capacitor (4u7) supplies > > enough initial current. > > > > Measuring the current during startup yields to following results: > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and > > staying there for about 15 us (I think for internal startup). After that it > > dropps to a few mA. > > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. It > > can not deliver this peak current during it's own start. > > > > Just wanted to tell this story (of hidden problems of a new family) for > > others who want to work with this new (still exciting) FPGAs to not run into > > the same troubles. > > > > Martin Schoeberl > > Martin, > The highest power-up current requirement that we have characterized > for the Cyclone family is 420 mA. This is more than the LTC3405 can > supply, and we are modifying AN257 accordingly. Also, we will document > the requirement for power-up current in the Cyclone datasheet. I'm not > sure why you are seeing more current than we saw - in some cases the > decoupling caps can also take some transient current as they charge > up, but I would not think that this would be 300 mA. Greg, thanks for the information. Can you tell us how long these 420 mA are needed. Or in other words how much 'charge' I have to supply for startup. The decoupling caps are not the problem. As you can see in the schematic of the board there are only 8x 10nF on VCCINT. I will examine the startup current in more detail (with a lower shunt) and show the plots on the web site. > Later posts indicate that you have solved this problem. If you have > any other questions about this feel free to contact me. I will write a little summary of the ideas in this thread and show the graphs. Martin SchoeberlArticle: 53469
"Thorsten Bunte" <t.bunte@beckhoff.de> schrieb im Newsbeitrag news:b4qnmr$22vid7$1@ID-22362.news.dfncis.de... > Hi Greg, > > just a question. I cannot find AppNote 257 on the Altera Website. > > Thorsten > Shall I mail you a copy :-) MartinArticle: 53470
"Thorsten Bunte" <t.bunte@beckhoff.de> wrote in message news:<b4qnmr$22vid7$1@ID-22362.news.dfncis.de>... > Hi Greg, > > just a question. I cannot find AppNote 257 on the Altera Website. > > Thorsten > > "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag > news:5c1de958.0303130813.2724eca7@posting.google.com... > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:<TP5aa.79536$AV5.998926@news.chello.at>... > > > I've built a board with the Cyclone from Altera. First board was ok, but > on > > > some of the following there was a problem with startup of the Cyclon. > > > > > > For the core voltage (1.5V) I use a drop-down regulator from Linear > > > Technology (LTC3405) as described in the app. note (AN257). But the core > > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I > > > examined the problem by building an extern regulator. > > > > > > Starting the regulator without load and than attaching the VCCINT pins > from > > > the FPGA leads to a successfull start. The output capacitor (4u7) > supplies > > > enough initial current. > > > > > > Measuring the current during startup yields to following results: > > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and > > > staying there for about 15 us (I think for internal startup). After that > it > > > dropps to a few mA. > > > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. > It > > > can not deliver this peak current during it's own start. > > > > > > Just wanted to tell this story (of hidden problems of a new family) for > > > others who want to work with this new (still exciting) FPGAs to not run > into > > > the same troubles. > > > > > > Martin Schoeberl > > > > Martin, > > The highest power-up current requirement that we have characterized > > for the Cyclone family is 420 mA. This is more than the LTC3405 can > > supply, and we are modifying AN257 accordingly. Also, we will document > > the requirement for power-up current in the Cyclone datasheet. I'm not > > sure why you are seeing more current than we saw - in some cases the > > decoupling caps can also take some transient current as they charge > > up, but I would not think that this would be 300 mA. > > Later posts indicate that you have solved this problem. If you have > > any other questions about this feel free to contact me. > > Sincerely, > > Greg Steinke > > Altera Corporation > > gregs@altera.com Thorsten, We have removed AN257 from the web site while we make the updates. We do not want any other customers to experience a similar problem. Sincerely, Greg Steinke Altera Corporation gregs@altera.comArticle: 53471
Hi Andre' I could not find the simulation options page to set No Glitch - could you please give me a pointer. Thanks a bunch. Andre Powell wrote: > HI Lijo, > If you are simulating with Modelsim you can turn off the glitch detection > using -noglitch as one of the simualation options. > > Best Regards > > Andre' > "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message > news:b4hhdm$1u7l6h$2@ID-159866.news.dfncis.de... > >>Hi all, >> I am trying to implement a logic into FPGA. I have functionally verified >>the logic and have synthesised the logic and verfied the post synthesis >>simulation output. >>After Implementation I have done the Timing Simulation with SDF files and >>have found a lot of invalid transitions between transition from one valid >>state to another valid state. I have no idea why this happens.. Is there > > any > >>problem if I download the code to the FPGA . Will it work properly. >> >>Please see the attached file. >> >>thanks >>Lijo >> >> >> > > >Article: 53472
thank you john., I am amatuer in this area. i appreciate your time for guiding me. keep me posted if you find anyone interested for PhD students for digital testing, computer architecture or Computer newtorks. By the way what is NG ? - Niranjandas M johnjakson@yahoo.com (john jakson) wrote in message > Simple bipolar devices like glue logic would'nt need much protection > from ESD, its intrinsic to the device, no thin oxides to protect > right?. Later on VLSI bipolar did start to get the same type of hard > ESD protection as CMOS was getting when the features got to small to > wing it. > > In fact TTL was so tough as old boots, there are Fairchild stories > that Chinese fabs used to make ripoff TTL in fabs where the air > conditioning was an open window. > > By the way this is the wrong NG, and the wrong century.Article: 53473
Is there any one out there who can help me with the VLCT 's ITP
(interactive tester pascal )program:
1) do we need to define VCC and GND pins. if yes, how to do that.
if no, how to test ICC tests
2) can i get a small program covering basic test for a small chip and
has explanation why they wrote the program the way it is written.
3)if i have a file in MS word how to transfer that to a solaris OS to
run ITP program.
cna u debug this program which is done for DM7408 fr leakage tests,
Voh,Vol,Vih,Vil tests and ICC tests
thank you
Niranjandas
_____________________________
Program QuadAnd;
Type
PinList=(A1,B1,Y1,A2,B2,Y2,A3,B3,Y3,A4,B4,Y4,ODD,EVEN, INPINS,
OUTPINS , ALLPINS, GND, Vcc );
PinCardList=( pins32to64, pins65to96, pins97to128, pins161to192 ,
pins193to224, pins225to256, ALLCARDS);
DCSetup = (OPENSDC, PowerdownDC, VOHTest,
VOLTest,InputLeakageOne,InputLeakageTwo,OutputLeakageOne,OutputLeakageTwo,ICCHTest,
ICCLTest );
TestNames = ( openstest,VOTest, InputLeakageTest,OutputLeakageTest,
ICCTest);
Var
result:Boolean;
index, pl_len: integer;
pl_arr : PinListArrayType;
Iih_meas : Treal;
DutToChan
1:233; {A1}
2:232; {B1}
3:101; {Y1}
4:213; {A2}
5:85; {B2}
6: ; {Y2}
7:gnd; {gnd}
8:51; {Y3}
9:173; {A3}
10:169; {B3}
11:165; {Y4}
12:45; {A4}
13:37; {B4}
14:dps; {vcc-1BX}
Begin
PinTableOpen;
PinSet (A1,1);
PinSet (B1,2);
PinSet (Y1,3);
PinSet (A2,4);
PinSet (B2,5);
PinSet (Y2,6);
PinSet ( GND,11111);
PinSet (B3,10);
PinSet (A3,9);
PinSet (Y3,8);
PinSet (B4,13);
PinSet (A4,12);
PinSet (Y4,11);
PinSet (Vcc,1111);
PinListSet ( INPINS, A1,B1,A2,B2,A3,B3,A4,B4);
PinListSet ( OUTPINS, Y1, Y2, Y3, Y4);
PinListSet ( ODD, A1, A2 , A3 , A4,);
PinListSet ( EVEN, B1, B2, B3, B4);
PinListSet ( ALLPINS, INPINS, OUTPINS);
PinCardSet ( pins32to64, S_PINCARD2);
PinCardSet ( pins65to96, S_PINCARD3);
PinCardSet ( pins97to128, S_PINCARD4);
PinCardSet ( pins161to192, S_PINCARD6);
PinCardSet ( pins193to224, S_PINCARD7);
PinCardSet ( pins225to256, S_PINCARD8);
PinCardSet ( ALLCARDS, pins32to64, pins65to96,pins97to128,
pins161to192,
pins193to224, pins225to256);
PinTableClose ;
Procedure DCDatasheet:Export;
Begin
V[VccMin]:=4.75v;
V[VccNom]:=5.00v;
V[VccMax]:=5.25v;
V[Vih]:=2.00v; { Min }
V[Vil]:=0.80v; {Max}
I[Ioh]:=-0.80mA; {Max}
I[Iol]:=16.00mA; {Max}
V[VohMin]:=2.40v; { At VccMin=4.75v, IohMax= -0.8mA,VilMax=0.8v }
V[VohTyp]:=3.40v; { At VccMin=4.75v, IohMax= -0.8mA,VilMax=0.8v }
V[VolTyp]:=0.20v; { At VccMin=4.75v, IolMax=16mA,VilMax=0.8v }
V[VolMax]:=0.40v; { At VccMin=4.75v, IolMax=16mA,VilMax=0.8v }
I[Iin_Vil]:=1mA; { VccMax=5.25v,Vi=5.5v };
I[Iih]:=40uA; { VccMax = 5.25v,Vi=2.4v };
I[Iil]:=-1.6mA; { VccMax = 5.25, Vi = 0.40v};
End;
DCSetupOpen(PowerdownDC);
DCSet(0v,0v,0v,0v,0mA,0mA,ALLCARDS);
DCConnect(ALLPINS,S_low,S_open);
DCSetupClose;
/* DCSetupOpen(ContyTest);
DCSet(0v,0v,0v,-1.0v,100uA,-100uA,ALLCARDS);
DCConnect(ALLPINS,S_low,S_pin);
DCSetupClose; */
DCSetupOpen(VOHTest);
DCSet(5.25v,0.8v,2.4v,2.0v,0A,0A,INPINS);
DCConnect(INPINS,S_LOW,S_LDOFF);
DCConnect(OUTPINS,S_LOW,S_FUNC);
DCSetupClose;
DCSetupOpen(VOLTest);
DCSet(0.8v,0v,0v,0v,0A,0A,INPINS);
DCConnect(INPINS,S_LOW,S_LDOFF);
DCConnect(OUTPINS,S_LOW,S_FUNC);
DCSetupClose;
DCSetupOpen(InputLeakageOne);
DCSet(0v,0v,0v,0v,-1.5mA,-1.7mA,ODD);
DCSet(0v,0v,0v,2.4v,30uA,50uA,EVEN);
DCConnect(INPINS,S_LOW,S_LEAK);
DCConnect(OUTPINS,S_LOW,S_OPEN);
DCSetupClose;
DCSetupOpen(InputLeakageTwo);
DCSet(0v,0v,0v,0v,-1.5mA,-1.7mA, EVEN);
DCSet(0v,0v,0v,2.4v,30uA,50uA, ODD);
DCConnect(INPINS,S_LOW,S_LEAK);
DCConnect(OUTPINS,S_LOW,S_OPEN);
DCSetupClose;
DCSetupOpen(OupputLeakageOne);
DCSet(0v,0v,0v,0.8v,0A,0A,INPINS);
DCSet(0v,0v,0v,3.4v,-0.6mA,-1.0mA,OUTPINS);
DCConnect(ALLPINS,S_LOW,S_LDOFF);
DCSetupClose;
DCSetupOpen(OupputLeakageTwo);
DCSet(0v,0v,0v,2v,0A,0A,INPINS);
DCSet(0v,0v,0v,0.2v,18mA,14mA,OUTPINS);
DCConnect(ALLPINS,S_LOW,S_LDOFF);
DCSetupClose;
DCSetupOpen(ICCHTest);
DCSet(0v,2v,0v,0v,0A,0A,INPINS);
DCConnect(INPINS,S_LOW,S_LDOFF);
DCConnect(OUTPINS,S_LOW,S_OPEN);
DCSetupClose;
DCSetupOpen(ICCLTest);
DCSet(0.8v,0v,0v,0v,0A,0A,INPINS);
DCConnect(INPINS,S_LOW,S_LDOFF);
DCConnect(OUTPINS,S_LOW,S_OPEN);
DCSetupClose;
(*##########################################*)
(*Other Setups*)
(*##########################################*)
/* TestOpen(openstest);
SetupSelect(ContyTest);
SupplySet(S_DPS1A,0v,50mA,S_Igain_1X,S_low_curr_mode);
Wait(5msec);
discard(CurrentCompare);
PinListGet(ALLPINS,pl_len,pl_arr);
for index:=1 to pl_len do
if CompareGet(pl_arr[index])
then writeln(‘pin:',pl_arr[index],'failed')
else writeln(‘pin:',pl_arr[index],'passed');
writeln;writeln;writeln(‘continuity test finished');writeln;
pause;
SetupSelect(PowerdownDC);
TestClose; */
TestOpen(VOTest);
SetupSelect(VOHTest);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(VoltageCompare);
PinListGet(OUTPINS,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( CompareGet(pl_arr[index]) >2.4v) THEN
writeln(‘OUTPIN',index,pl_arr[index],'passed')
else
writeln(‘OUTPIN',index,pl_arr[index],'failed');
pause;
TestOpen(VOTest);
SetupSelect(VOHTest);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(VoltageCompare);
PinListGet(OUTPINS,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( CompareGet(pl_arr[index]) < 0.4v) THEN
writeln(‘OUTPIN',index,pl_arr[index],'passed')
else
writeln(‘OUTPIN',index,pl_arr[index],'failed');
pause;
writeln(‘O/P Voltage Test is finished');
pause;
SetupSelect(PowerdownDC);
TestClose;
TestOpen(InputLeakageTest);
SetupSelect(InputLeakageOne);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(ODD,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( (CompareGet(pl_arr[index]) > -1.8mA ) AND
(CompareGet(pl_arr[index]) < -1.3mA ) )
then
writeln(‘ODD',pl_arr[index],'passed')
else
writeln(‘ODD',pl_arr[index],'failed');
PinListGet(EVEN,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( (CompareGet(pl_arr[index]) > 35uA ) AND
(CompareGet(pl_arr[index]) < 45uA) )
then
writeln(‘EVEN',pl_arr[index],'passed')
else
writeln(‘EVEN',pl_arr[index],'failed');
pause;
SetupSelect(InputLeakageTwo);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(EVEN,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( (CompareGet(pl_arr[index]) > -1.8mA ) AND
(CompareGet(pl_arr[index]) < -1.3mA ) )
then
writeln(‘EVEN',pl_arr[index],'passed')
else
writeln(‘EVEN',pl_arr[index],'failed');
PinListGet(ODD,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF ( (CompareGet(pl_arr[index]) > 35uA ) AND
(CompareGet(pl_arr[index]) < 45uA ) )
then
writeln(‘ODD',pl_arr[index],'passed')
else
writeln(‘ODD',pl_arr[index],'failed');
pause;
SetupSelect(PowerdownDC);
TestClose;
TestOpen(OutputLeakageTest);
SetupSelect(OupputLeakageOne);
SupplySet(S_DPS1A,4.75v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(OUTPINS,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF (CompareGet(pl_arr[index])) then
writeln(‘OUTPIN',index,'passed')
else
writeln(‘OUTPIN',index,'failed');
writeln(‘O/P high Voltage Test is finished');
pause;
SetupSelect(OupputLeakageTwo);
SupplySet(S_DPS1A,4.75v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(OUTPINS,pl_len,pl_arr);
FOR index := 1 to pl_len do
IF (CompareGet(pl_arr[index])) then
writeln(‘OUTPIN',index,'passed')
else
writeln(‘OUTPIN',index,'failed');
writeln(‘O/P low Voltage Test is finished');
pause;
writeln(‘O/P Voltage Test is finished');
pause;
SetupSelect(PowerdownDC);
TestClose;
TestOpen(ICCTest);
SetupSelect(ICCHTest);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(Vcc,index);
IF ( (CompareGet(index) > 10mA ) AND (CompareGet(index) <
22mA) )
then writeln(‘Vcc passed')
else writeln(‘Vcc failed');
writeln(‘ ICCH finished');
pause;
SetupSelect(ICCLTest);
SupplySet(S_DPS1A,5.25v,50mA,S_IGAIN_1X,S_LOW_CURR_MODE);
Wait(5msec);
DISCARD(CurrentCompare);
PinListGet(Vcc,index);
IF ( (CompareGet(index) > 19mA ) AND (CompareGet(index) <
34mA) )
then writeln(‘Vcc passed')
else writeln(‘Vcc failed');
writeln(‘ ICCL finished');
pause;
writeln(‘ICC test finished');
TestClose;
End;
Article: 53474Is there anything similar in Spartan IIE? This is again that same much discussed in this ng problem of another system requiring the data to show up so many nanoseconds after the clock edge. I did try creating a delay block by sticking a bunch of inverters with keep attributes set, but I can't seem to get the same delay among different instances. I presume creating a netslist macro is a solution, but am not sure how that is done. Peter Alfke wrote: > In Virtex-II you can specify a clock delay of n/256 of the clock period > ( limited to a granularity of ~50 picoseconds ). That solves your problem. > For most other delays the ratio between max and min is >2, which makes > any compensation attempts pretty useless. > > Peter Alfke, Xilinx Applications > ===================== > Igor Orlovich wrote: >> >> I have a project which need sto interface to a system with fairly rigid >> timing specs. As a result I need to delay my signals coming that way a >> certain number of nS whiich is not a multiple of any clock I have in the >> chip. Is there any way I can add some propagation delay/gate delay and >> not have it optimized out by the XST tools. Or alternatively, is there a >> way to specify not only the max delay between signals, but also the min >> one? Thanks for any suggestions
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