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"Jeniffer" <J_Jeniffer@excite.com> wrote in message news:ded21c45.0303180211.2d7aef7a@posting.google.com... > Given a bit file and the architecture for which the bit file is compiled, > is there a way, I can covert it back into an ncd file so that I can view > it in an FPGA editor? The NCD file seems to be used both before and after place and route. It is theoretically possible to convert bits back to an NCD file describing the CLB's and routing resources. The fact is, though, that no program exists to do that. This is reasonably equivalent to disassembly done to computer object code. It is pretty much impossible to convert the bits back to the input to place and route. Either a schematic, logic, or HDL level description. Much information is lost in the conversion that cannot be restored. This is similar to the reverse compilation that is often desired of compiled high-level languages, but usually can't be done. You should make plenty of back-up copies of your design files! -- glenArticle: 53701
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b58ok8 (snip) regarding: > > http://www.xilinx.com/company/press/products/archive.htm > > What I find interesting is the Virtex die image. If you display a > Virtex bitstream as a rectangular binary image with appropriate rows and > cols (avail in the data sheet), the resemblance is uncanny. Right down > to the little "flecks" you see on each CLB, and the lines across the > centre of the chip. It shouldn't be a surprise, but the mapping between > the bitstream format and the physical layout of the chip is more or less > 1:1. Which probably explains Xilinx' desire to keep it to themselves. It probably has to be that way to make the chip reasonably routable. -- glenArticle: 53702
the board is made distrobuted by segor electronics, it is called x2s_usb. Im relatively new to fpgas so I dont know how well it performs, but the specs i read on the webpage seem fine to me. I believe they have other usb solutions with ddr etc. I think the pico sounds good seeing its free it would be excellent to practice with. Was hoping maybe u had some information on how to interface a fpga cpu core with a pc application so I can send data to and from the pc app to the fpga for calculations. This would be ideal to find out. Thanks. "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:3E787A87.504CF524@egr.msu.edu... > Take a look at the pico-blaze. It is a free simple 8 bit micro. On a > different issue... What is the board. We are looking at redesigning a > spartan2e board to use the cypress ez chip and the usb interface might > be of interest. > > Thanks, > Theron Hicks > > newdevkit wrote: > > > Hello, > > I recently aqquired a spartan2e dev board with a usb programming > > interface (uses cypress ez chip). I am very new to fpgas and curious > > as to where I can find a fpga core that is a cpu such as risc or cisc. > > Something just very simple so that I can attempt to send the cpu a > > command such as add two values or decrementing/incrementing a value. > > If anyone can help me with this I would be very grateful with any > > suggestions. Thank you. >Article: 53703
> > I have used the altera ACEX 1K product line and after studing the new > Cyclone products ... except for possibly the very lowest cost 1K > products which still seem to be cheaper than the lowest cost Cyclone > .. is there any reason to still consider the 1K products for new > designs over the Cyclone ? thanks for any insight CB > I think you can replace the 1K with Cyclone. One difference I found: The memory block don't allow async data, address and aen in. Which was possible in the ACEX 1K family. Data out can still be unregistered. If you have a design with asynch. memory usage (like lookup table) you have to change it to synchron or 'pseudo asynchron'. Pseudo-Asynchronous means that you use an inverted clock for the input registers. And you cannot read the new data during write. I think this was possible in the ACEX family. See AN210 and AN252 from Altera. Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 53704
In alt.folklore.computers Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > > "Niranjandas" <nidar@rediffmail.com> wrote in message > news:4f155288.0303192119.1770abb6@posting.google.com... >> hi rosen, >> i am looking for tetsting that age old product thru a letest low cost >> ATE. so for tetsting opens test i req to know if they have ESD thats >> it. >> any way can u suggest better Group who discusses elated areas >> Questions? > > alt.folklore.computers > > "elated areas"? sounds like alt.sex to me. ;P pete -- pete@fenelon.com "there's no room for enigmas in built-up areas" HMHBArticle: 53706
"David Binnie" <david.binnie@btinternet.com> wrote in message news:<b55260$5t9$1@knossos.btinternet.com>... > M9anly Architecture. > > A CPLD is a number on PAL like sructures networked on the same chip, > > An FPGA has finer grain logic blocks with integrated routing. > > > Santa <santa19992000@yahoo.com> wrote in message > news:60e37826.0303131024.77a1fe15@posting.google.com... > > Guys, > > > > what is FPGA?. Also what is the difference between FPGA, CPLD and > > ASIC?. Especially the functionality diff between ASIC and FPGA?. > > Thanks in advance. You may find some information on this here: http://www.fpga-faq.com/FAQ_Pages/0007_Device_type_comparisons.htm http://www.fpga-faq.com/FAQ_Root.htm http://www.vcc.com/fpga.htmlArticle: 53707
"Roberto Gallo" <robertogallofilho@hotmail.com> wrote in message news:<b3ol7t$9nb$1@aracaju.ic.unicamp.br>... > Hello everyone. > > > > I have no experience on FPGA programming, thus many questions. I am > developing hardware for modular math operations that have big area > requirements. Given that, only high density FPGAs, which are volatile, > appear to meet these requirements. So, I have some questions: > > > > * Are there high density non-volatile FPGAs? > > * What are the ways to program a FPGA like APEX as my hardware is > powered up? One option could be using SystemBIST processor IP by Intellitech (http://www.intellitech.com). It enables in-the-field self-testable and reconfigurable products. It is vendor independent. It replaces the existing method of configuring your FPGAs and give you an easy way to upgrade the boards in the field. The embedded self-test capabilities of SystemBIST are gained for free, giving you and your customers the ability to apply all boundary-scan tests throughout the product's life cycle. Intellitech also provides software for validation of your code both on Unix and Windows. > > * How long does it take typically? > > * How big are the typical memory requirements to hold a FPGA > configuration data? > > * What is the protocol for this programming? > > > > Thank you in advance, > > Roberto GalloArticle: 53708
On Thu, 20 Mar 2003 00:19:22 -0500, Niranjandas wrote: > hi rosen, > i am looking for tetsting that age old product thru a letest low cost > ATE. so for tetsting opens test i req to know if they have ESD thats it. > any way can u suggest better Group who discusses elated areas Questions? > > > Niranjandas > > > > "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message > news:<pan.2003.03.17.21.03.37.306278.2313@polybus.com>... >> On Mon, 17 Mar 2003 14:18:11 -0500, John Eaton wrote: >> >> >> I don't think that the OP was talking about an old system, why would he >> have been interested in ESD protection if all he was doing was >> repairing an antique system. The right place to ask a question like that is the manufacturer not a newsgroup. It looks like Fairchild is still making the part, contact them. Some of us old folks can wager a guess based on our hazy recollections of the distant past but things may have changed since the time when we used that part.Article: 53709
praveen wrote: > Hello Sir, > I am designing a PCI target in an FPGA. The module i am going to > implement include > 1.Configuration Multiplexer Block. > This block implements the PCI Target configuration registers, and the > PCI data output > MUX. > 2.Retry Counter Block: > If the PCI Target acknowledges a Read or Write cycle it must provide > or accept data > within 16 clock cycles of asserting DEV_SEL. > 3.Miscellaneous Glue Logic Block: > This module contains the miscellaneous glue logic required for the > design. It contains the > PCI address registers, CBE registers, and the IDSEL register. > 4.Base Address Check Block > 5.State Machine > It controls the bus > cycle timing of all data flow paths to and from the PCI Bus and Back > End Bus. > 6.Parity Generation Block > Parity is generated on Configuration read, and Memory-I/O reads > cycles. > > Is this much module enough. Where to include FIFO for burst > write.Which FPGA to go whether Altera or Xilinx > > Waiting for your reply > praveen following my experience with our pci target core, board and win drivers, in reality, you will be able to access the burst mode only for a master pci core. The problem is coming between the OS and the PCI chipset on the classic PC motherboard (don't lose to many time in the burst mode functionality of your target core if the application is for classic pci pc card, because you will be not able to initiate a burst access from you pc). But you maybe thinking about an embeded pci application of your target pci core, in this case you can take time on the burst mode implementation, but make sure your host pci chipset can be configurated to initiate a burst mode! Laurent Gauch www.amontec.comArticle: 53710
hi, I want to program a XC9572 with a Hi-Lo system All-07 programmer. Has anyone any idea of the connections for an adapter from PLCC84 to DIL 48 ?? Thanks -- the Ing.Article: 53711
Jerry wrote: > Does anyone know of a FPGA dev board that can be expanded? > what I'm looking for is a board that can connect to other boards Look at our ASIC prototype board: http://www.hardi.se/haps Regards, Jonas Nilsson HARDI Electronics ABArticle: 53712
We assumed the follow situation: I floorplanned two regions for putting two modules: a reconfigurable and a fixed module. This modules are independents, without any communication between them. However, there are pins that reconfigurable module need to use, but these pins are above floorplaned area of fixed module. In this case, Do I need to install BUS MACROS or some BUFFER? Do I always need to fix BUS MACROS when I use two modules using Partial Reconfiguration with the performing of Modular Design flow, in any case? Please, I need to help. EduardoArticle: 53713
Hi, Has anyone tried to use PrimeTime tool from Synopsys as their Static Timing Anaylsis tool? I am currently trying to use this flow and running into 'learning curve' difficulties. Is it worth putting in all the effort to use PrimeTime instead of TRCE tool from Xilinx? Thanks, JSinghArticle: 53714
"Laurent Gauch, Amontec" <laurent.gauch@amontec.com> wrote in message news:3E79D67D.8090405@amontec.com... > > in reality, you will be able to access the burst mode only for a master > pci core. The problem is coming between the OS and the PCI chipset on > the classic PC motherboard (don't lose to many time in the burst mode > functionality of your target core if the application is for classic pci > pc card, because you will be not able to initiate a burst access from > you pc). Our experience is very different from this. Testing was done on a computer that weI do not ave access to right now, and I do not recall the exact configuration. The test computer did have a 64bit PCI bus. The test application performed 32bit acccesses, both a series of reads, and a series of writes, in a simple for loop. We observed, using a VMetro Bus Analyzer, that the PCI Bridge in the computer was grouping these individual accesses into bursts. Given that the PCI bus is very slow relative to the front side bus on the computer, I would assume that most new motherboards do this sort of assembly. My conclusion is based on an N of 1, so rely on it at your own risk. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 53715
After configuration, what happens to the DCLK and DATA lines? Are they pulled high or low or are they tristate?Article: 53716
Hi, you did not get a response in a long time, so here are some general hints. Roberto Gallo wrote: > > Hello everyone. > > I have no experience on FPGA programming, thus many questions. I am > developing hardware for modular math operations that have big area > requirements. Given that, only high density FPGAs, which are volatile, > appear to meet these requirements. So, I have some questions: > > * Are there high density non-volatile FPGAs? Not really. The max density of non-volatile antifuse-based FPGAs from Actel and Quicklogic is significantly lower than the max density of FPGAs from Xilinx and Altera. > > * What are the ways to program a FPGA like APEX as my hardware is > powered up? Just look at teh datasheets from Altera and Xilinx, they describe this in detail. Lokk at tehir web pages (www.altera.com and www.xilinx.com ) > > * How long does it take typically? from milliseconds to hundreds of milliseconds. > > * How big are the typical memory requirements to hold a FPGA > configuration data? from less than a megabit to 20 megabits ( i.e. max 2.5 megabytes) > > * What is the protocol for this programming? see the manufacturers' documentation. > > We all like "novices", since they represent a new business opportunity. But I also feel that any novice should first explore the available literature. The web makes this so very easy! Peter Alfke, Xilinx ApplicationsArticle: 53717
Hi - I know of a couple customers in India successfully using PrimeTime for STA of Xilinx FPGAs. Synopsys PT was supported by Xilinx starting 4.1i release. XAPP411 on support.xilinx.com might give you some tips, if you haven't seen it already. --Neeraj <JSingh> wrote in message news:ee7c778.-1@WebX.sUN8CHnE... Hi, Has anyone tried to use PrimeTime tool from Synopsys as their Static Timing Anaylsis tool? I am currently trying to use this flow and running into 'learning curve' difficulties. Is it worth putting in all the effort to use PrimeTime instead of TRCE tool from Xilinx? Thanks, JSinghArticle: 53718
Thanks for the info. I do have acess to the document you are mentioning. However presently my run time in Prime time is hours. For the ASIC flow primetime would be done in minutes. I am suspecting that xilinx2primtime is not doing a good job in translating the verilog and the sdf files.Article: 53719
"Maxx" <bla@bla.com> schrieb im Newsbeitrag news:3e797e7f$0$1141$4d4ebb8e@read-nat.news.nl.uu.net... > Well I guess it shows I'm a newby... yes I assigned that clock signal to a > GCK, but how do I assign it to an IBUFG? Up till now, ISE did it for me Normally, XST (thes Webpack Synthesizer) does this autiomatically. > automagically (with the normal clock it did atleast). The xilinx website > says I need to instantiate one.. sure. but how? :) > also, what would be the definition of a "pure" clock? -> one where I check > for 'event ? Yes. Dont use things like my_internal_clock <= clock_from_outside AND control_signal; This is clock gating and in most cases no good and not neccessary. -- MfG FalkArticle: 53720
"geeko" <jibin@ushustech.com> wrote in message news:<b59a36$26ikrl$1@ID-159027.news.dfncis.de>... > hi all > Anybody familiar with Excalibur bus functional model where is it available > is it free.Can it be used for functional simulation in 3rd party tools > re > gee Hello, The Bus Functional Model is available with the Quartus II software in the simulation libraries for the Excalibur Device. You can download the Quartus II Web Edition for free from www.altera.com and access the BFM which is located in <Quartus Install Dir>/eda/sim_lib/altera_mf.v(vhd). Please see the BFM User Guide located at http://www.altera.com/literature/ug/ug_bus_functional_model.pdf. There is also an example design, Excalibur Hardware Design Tutorial, located on the same page which demonstrates how to create stimulus and use the model. Yes, the BFM can be used in 3rd party simulators because it is clear-text Verilog or VHDL. Best Regards, SabrinaArticle: 53721
Hi Does anyone have any recomendations for which "device" to use for the implementation of a simple CPU I have implemented in VHDL. This is a university project I have to complete as a result the number gates is very low so the simplest device possible would probably be most suited. Assuming I have chosen a suitable FPGA, what do I need to purchase to implement the code in the FPGA, do I need a development board or just a programmer, I need to spend as little as possible. What is the bare minimum to program it. Can I send the code off to an external company in the UK to program it for me??? <- very much prefered. Also after reearching the various FPGA manufacturers, Ive found that to order a FPGA or deelopement board requires ordering from the US to the UK. Are there no suppliers in the UK where I can get these products from simply by placing an online order as I would with any other component. Cheers joolsArticle: 53722
I would use either Spartan-II or Virtex-II from Xilinx ( I am biased, that's where I work). I would use an existing evaluation board, available from local distributors. Pickthe smallest and cheapest you can get. Also, scan this newsgroup. There has been extensive discussion of various evaluation boards. Development software for your kind of complexity is free, but you should have a PC to develop and download the design bitstream. (That's really your contribution). Major manufacturers are well-represented in the UK. Here is the list of Xilinx distributors, I just picked that from our website. http://www.xilinx.com/company/sales/ww_disti.htm#UNITED Have fun... Peter Alfke, Xilinx Applications ================== jools wrote: > > Hi > > Does anyone have any recomendations for which "device" to use for the > implementation of a simple CPU I have implemented in VHDL. This is a > university project I have to complete as a result the number gates is > very low so the simplest device possible would probably be most > suited. > > Assuming I have chosen a suitable FPGA, what do I need to purchase to > implement the code in the FPGA, do I need a development board or just > a programmer, I need to spend as little as possible. What is the bare > minimum to program it. Can I send the code off to an external company > in the UK to program it for me??? <- very much prefered. > > Also after reearching the various FPGA manufacturers, Ive found that > to order a FPGA or deelopement board requires ordering from the US to > the UK. Are there no suppliers in the UK where I can get these > products from simply by placing an online order as I would with any > other component. > > Cheers > > joolsArticle: 53723
"jools" <j.p.murphy@ncl.ac.uk> wrote in message news:7fb35ec4.0303201113.2036367e@posting.google.com... > Hi > > Does anyone have any recomendations for which "device" to use for the > implementation of a simple CPU I have implemented in VHDL. This is a > university project I have to complete as a result the number gates is > very low so the simplest device possible would probably be most > suited. > > Assuming I have chosen a suitable FPGA, what do I need to purchase to > implement the code in the FPGA, do I need a development board or just > a programmer, I need to spend as little as possible. What is the bare > minimum to program it. Can I send the code off to an external company > in the UK to program it for me??? <- very much prefered. > > Also after reearching the various FPGA manufacturers, Ive found that > to order a FPGA or deelopement board requires ordering from the US to > the UK. Are there no suppliers in the UK where I can get these > products from simply by placing an online order as I would with any > other component. > > Cheers > > jools Hello, Farnell www.farnell.com sell an Atmel kit for £82 and take credit card orders. If you look on the Xilinx website and locate their UK distributors you can get dev boards from them. I have a Xinlinx board (for Spartan) which came from Insight www.insight.uk.memec.com but I think it costs more at about $195 Good luck. Michael KellettArticle: 53724
Praveen,
praveen wrote:
>
> Hello Sir,
> I am designing a PCI target in an FPGA. The module i am going to
> implement include
> 1.Configuration Multiplexer Block.
> This block implements the PCI Target configuration registers, and the
> PCI data output
> MUX.
> 2.Retry Counter Block:
> If the PCI Target acknowledges a Read or Write cycle it must provide
> or accept data
> within 16 clock cycles of asserting DEV_SEL.
> 3.Miscellaneous Glue Logic Block:
> This module contains the miscellaneous glue logic required for the
> design. It contains the
> PCI address registers, CBE registers, and the IDSEL register.
> 4.Base Address Check Block
> 5.State Machine
> It controls the bus
> cycle timing of all data flow paths to and from the PCI Bus and Back
> End Bus.
> 6.Parity Generation Block
> Parity is generated on Configuration read, and Memory-I/O reads
> cycles.
>
I will say that you forgot to add a design block that checks for
a parity error.
Also, many PCI IP cores I know don't implement counters to enforce the
16/8 clock rule probably because supporting it will complicate the
implementation.
> Is this much module enough. Where to include FIFO for burst
> write.
One idea is to attach a separate FIFO module to the backend.
> Which FPGA to go whether Altera or Xilinx
>
> Waiting for your reply
> praveen
Keep everything generic.
Avoid using vendor specific library primitives as much as possible.
If you have to use vendor specific library primitives, you should also
have a way to disable it, so that it can be ported to another platform
easily.
For my experience, Xilinx Virtex family is a lot more PCI friendly than
Altera APEX20K or FLEX10K series, so I recommend going with Xilinx.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
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Compare FPGA features and resources
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