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Messages from 85525

Article: 85525
Subject: Re: pcb layers on BGAs Spartan-3
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 17:42:48 +0200
Links: << >>  << T >>  << A >>

"dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag
news:1118373181.586925.297720@f14g2000cwb.googlegroups.com...

> I have laid out my first board using the FT256. I have not had it
> fabricated yet. It is 4 layers 6/6mil track/space.  The real killer was
> the size of the vias.  I used 1 solid groundplane and planelets for

??? How is it possible to fanout the balls on just 2 signal layers (1 layer
is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
(which leaves 4 layers for signals)?

Regards
Falk




Article: 85526
Subject: Re: Gated clock question
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 17:49:44 +0200
Links: << >>  << T >>  << A >>

<stoyan.shopov@gmail.com> schrieb im Newsbeitrag
news:1118403028.509240.312620@z14g2000cwz.googlegroups.com...
> Thanks to all of you, guys, you have been really very helpful!
> Actually, I suspected there might be glitches when gating a clock, now
> things are quite more clear.

If done propperly, also clock gating is safe. But is has to be done
PROPERLY!. As otheres already noted, FPGAs are not directly designed to
support clock gating. Use clock enable and you will sleep well ;-)

Regards
Falk





Article: 85527
Subject: computer upgrade time.
From: Ray Andraka <ray@andraka.com>
Date: Fri, 10 Jun 2005 11:51:02 -0400
Links: << >>  << T >>  << A >>
Time has come for a computer upgrade (I'm currently using a dual Athlon 
1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, 
matrox dual head video with a pair of 19" monitors), but I haven't kept 
up at all with the computer market.  I'm wondering what people are using 
these days for high end designs (for simulation and PAR especially).  
I'd like something that doesn't sound like a vacuum cleaner and heat the 
room like a space heater this time around too, perhaps I need to 
consider liquid cooling?  ANy comments would be appreciated.  Yes, I 
admit I am being lazy.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 85528
Subject: Re: SPD interface(Serial presence detect)
From: "Gabor" <gabor@alacron.com>
Date: 10 Jun 2005 08:51:03 -0700
Links: << >>  << T >>  << A >>


praveen.kantharajapura@gmail.com wrote:
> Hi all,
>
> I am implementing a SPD interface in an FPGA. The DDR SDRAM is from
> MICRON.
> Now to redd the EEPROM content(first 128 bytes) , first i will send the
> slave addres of EEPROM over I2C(with r/w='1' , which indicates a
> read).Now my question is will the EEPROM send all the bytes serially at
> one shot, OR should i address which byte i want to read explicitly ??
>
>
> Regards,
> Praveen

I2C EEPROMs come in more than one flavor.  The simplest with up to 256
bytes use a single byte address.  Larger ones need more address bytes.
To access the data starting at zero, you must write zero to the EEPROM
address register, if not you can get data starting at some random
address.

For the small EEPROMs (which are big enough to store SPD for most
applications) you would write zero (one byte) then read any number
of bytes.  The address increments after each read, whether or not
you send them within one start-stop sequence.  This is why you need
to reset the address before you start reading.

You don't need to use a repeated start sequence to read the EEPROM.
You can just do a simple write (one byte of address for small EEPROMs
two or more for larger ones) followed by simple reads.  Beware that
writing too many bytes to the EEPROM can cause data to be written
if the device is not write protected.  i.e. if you have a 24C02 and
send two bytes of zero, you'll clear the first byte in the EEPROM.
Also if you write too many bytes you'll start reading after the byte
written (byte 1 in the example just mentioned).

So to sum it briefly.  Writing multiple bytes starts with the address
register and continues with data.  If the address register is one byte,
only the first byte after the I2C address cycle goes to the address
register and subsequent bytes go into the EEPROM starting at the
address
just written and incrementing with each byte.  After the writes are
done,
the address register keeps its value which will point to the location
after the last one written (or to the address written if no bytes were
written to the EEPROM).  Reading always starts from the location in
the address register, which increments after each byte.  You must write
to force the address register to a known value before you start to
read.

Regards,
Gabor


Article: 85529
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: "MK" <nospam.please@here.ever>
Date: Fri, 10 Jun 2005 16:56:22 +0100
Links: << >>  << T >>  << A >>

"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:cenia1pc7q3ptsc4rrhts8phl8085g2smh@4ax.com...
> Wondering if anyone else has experienced this....
> After the recent X-Fest seminar in Cambridge UK, I ordered the Memex FPGA
Design Starter kit on the
> x-fest special offer, as it was a cheap way to get the BaseX software.
> I'm now told that the kit won't be shipped til mid-August. I have no
problem with that as I don't
> need the hardware immediately & already have the S3 starter kit..
>
> However when I contacted Memec to ask if they could ship the software
immediately (which
> Incidentally they charged my card for 2 weeks ago), they claimed that this
wasn't possible, and when
> I pressed them they said they'd ask Xilinx but were fairly sure they
wouldn't do it.
>
> I'm sure I'm not the only one who ordered this offer as it was a very good
deal compared to the
> normal price - has anyone else had any joy getting the software out of
them ahead of the hardware ?
>
> Seems like a pretty daft situation.....


Hi Mike,

I haven't ordered mine yet (still in shock at the 8-10 weeks delivery). I'm
fairly horrified that they charged your card before they had the stuff to
send.

I'm going to copy this to the Xilinx Apps manager and see what happens.

On past experience (are you there Xilinx !!) it won't be much - I'm still
waiting for price and delivery from Memec re S3E parts from an enquiry I
made on 20th May.

Michael Kellett



Article: 85530
Subject: Re: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 10 Jun 2005 16:56:50 +0100
Links: << >>  << T >>  << A >>
If you use FPGA Editor you can select the clock signal and list what pins 
are on it. Look for odd pin names on the list is one way. On a clock you do 
get a lot of pins listed. Organised by delay the non-clock pins may be also 
at one end of the list. If you look at the logic naming where the clock is 
used as logic input then you should hopefully get an idea where the problem 
lies.

One possibility is that it has been used as a gated clock and it will go 
into a LUT with some other signals. You often find this in IP that was 
originally written for ASIC. Another possibility is that a clock inversion 
has not been properly pulled into the slice logic and a LUT has been used.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"MM" <mbmsv@yahoo.com> wrote in message 
news:3gtpr1Feefu1U1@individual.net...
>I am getting the following warning on a Virtex-II design:
>
> WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1
> NON-CLK pins failed to route using a CLK template.
>
> My question is how can I find the problematic pin?
>
> A similar question was asked here in the past, but the discussion slipped
> into design practices. My design is pretty big and the biggest part of it 
> is
> third party core, for which I don't have source code. So, I need to figure
> out what exactly causes this warning...
>
> Thanks,
> /Mikhail
>
> 



Article: 85531
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 10 Jun 2005 15:58:24 GMT
Links: << >>  << T >>  << A >>
On Fri, 10 Jun 2005 16:56:22 +0100, "MK" <nospam.please@here.ever> wrote:

>
>"Mike Harrison" <mike@whitewing.co.uk> wrote in message
>news:cenia1pc7q3ptsc4rrhts8phl8085g2smh@4ax.com...
>> Wondering if anyone else has experienced this....
>> After the recent X-Fest seminar in Cambridge UK, I ordered the Memex FPGA
>Design Starter kit on the
>> x-fest special offer, as it was a cheap way to get the BaseX software.
>> I'm now told that the kit won't be shipped til mid-August. I have no
>problem with that as I don't
>> need the hardware immediately & already have the S3 starter kit..
>>
>> However when I contacted Memec to ask if they could ship the software
>immediately (which
>> Incidentally they charged my card for 2 weeks ago), they claimed that this
>wasn't possible, and when
>> I pressed them they said they'd ask Xilinx but were fairly sure they
>wouldn't do it.
>>
>> I'm sure I'm not the only one who ordered this offer as it was a very good
>deal compared to the
>> normal price - has anyone else had any joy getting the software out of
>them ahead of the hardware ?
>>
>> Seems like a pretty daft situation.....
>
>
>Hi Mike,
>
>I haven't ordered mine yet (still in shock at the 8-10 weeks delivery). I'm
>fairly horrified that they charged your card before they had the stuff to
>send.

I did order a 9500 kit on the same order which is due to ship now so I'm not especially bothered
about that aspect. 

>I'm going to copy this to the Xilinx Apps manager and see what happens.
>
>On past experience (are you there Xilinx !!) it won't be much - I'm still
>waiting for price and delivery from Memec re S3E parts from an enquiry I
>made on 20th May.
>
>Michael Kellett
>


Article: 85532
Subject: Re: fast universal compression scheme and its implementation in VHDL
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 18:01:09 +0200
Links: << >>  << T >>  << A >>

"Jens Mander" <quinn_the_esquimo@freenet.de> schrieb im Newsbeitrag
news:d8bbs2$mme$1@mamenchi.zrz.TU-Berlin.DE...

> my name is Jens and I am student of the Technical University Berlin.
Through

Hello Jens,

> am now starting my first "private" implementations. Just to give you a
short
> intro... ;-)
>
> I  am interested in implementing compression algorithms using VHDL on an
> FPGA. I want to build a data transmission system that compresses portions
of
> the incoming data (not the whole data but "frames" of like 800 bytes)

First things first. Do you have a reasonable amount of expirience using VHDL
and FPGAs? I mean, are you able to do more than just flashing a LED using a
FPGA? Something in the range of building a UART, using FIFOs (maybe building
a synchronous FIFO your own) etc. IF so, ok go ahead. IF NOT, I strongly
suggest to get to this level first before continuing.

> on-the-fly. In my search for a fast (i.e. real-time capable at a "desired"
> data rate of - let's say - 300 MHZ?) "universal" compression scheme I came

300 MHz isn't a data rate. (that why my comment above). So whats your
desired data rate? 300 Mbit/s? 300 Mbytes/s?

> - is there any free example code for compression algorithms available in
> VHDL to get an overview and a first impression of implementation
complexity?

Do you had a look at software compession routines? Study them. Understand
them. Convert them. Start with an easy one.

> - what would you think are the most promising algorithms for my purpose
> (i.e. when statistics and semantics of the input data are unknown), first
of
> all I thought of delta encoding, sorted RLE, LZ, ....?

> - as the input data is unknown the álgorithm must be lossless, reducing
> redundancy (if possible), not irrelevancy. what are the theoretical limits
> of "universal" compression, not emphazizing one particular statistical
> property (like similar by values in succession)?
>
> - what is meant by the keyword "systolic implementations" and "pipeling"
in
> that particular context? I came across that very often lately

Pipelinig is a technique to spread the data processing over multiple clock
cycles. Doing so allows to increase the clocking speed, since the individual
logic operations are simpler (and so faster). Penalty is increased latency.
This should be enough to start a research, isnt it?

> - what if my code gains different compression ratios for consecutive data
> portions? surely a FIFO can decouple input and output rate but eventually
> the FIFO will underflow?

Bad luck. FIFO too small and compression routine too bad.

Regards
Falk




Article: 85533
Subject: linker script!!!
From: "kittyawake@gmail.com" <kittyawake@gmail.com>
Date: 10 Jun 2005 09:03:43 -0700
Links: << >>  << T >>  << A >>
hi all,
  i am trying to collect some data and store in the memory.I want this
data to be continuous.Can i write my own section like
(.text,.sdata,.bss,etc..) in the linker script??and then assign a
pointer which points to this section and store the data using this
pointer???I have never written a linker script before.Please give me
some suggestions if i want to write such a section in linker
script.What does ALIGN(8) or ALIGN(4) mean?
thanx


Article: 85534
Subject: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 18:09:15 +0200
Links: << >>  << T >>  << A >>

"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag
news:ee8eb30.4@webx.sUN8CHnE...

> have multipled it by 2 and used to run another FIR filter (32 tap
decimation available from core gen) this is a fixed tap one
>
> Now i multipled 70.656 MHz output of my first DCM again by 2 to get
140.312 MHz which is given to the new 32 tap FIR filter i made as described
above (ie using descrite components , multipler,BRAM etc)

You better use just one DCM and use CLK2X and CLKFX (with M set to 4). This
way your clocks are well phase aligned. This can also work with two DCMs,
but more things can get messed up (And I guess two cascaded DCMs generate
more jitter than just one, right?).

> but during timing simulation i am getting this error in my model sim
simulator
>
> ===================================
>
> Time: 9898215 ps Iteration: 3 Instance:
/tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu138 # **
Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected :=
0.381 ns; Observed := 0.055 ns; At : 9898.226 ns # Time: 9898226 ps
Iteration: 3 Instance:
/tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu142 # **
Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; # Expected :=
0.381 ns; Observed := 0.328 ns; At : 9898.5 ns # Time: 9898500 ps Iteration:
3 Instance:
/tb_gl/uut/glrx_1_tde_filter_comp_tde_filter1_multiply_comp_bu152 # **
Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;
>
> ==================================
>
> what is this error means. i think there is some set-up violation but how
do i debugg this problem

It says something about a HOLD violation, not a setup violation. Make sure
your input signals change NOT exactly in the same moment as your clock.
Delay the input signals by lets say 3ns after the active (rising ?) clock
edge.

> how can i see the internal signals during timing simulation ?

You have to add them to the wave window (Befor you start simulation,
otherwise no data is recorded for these signals)?

Regards
Falk




Article: 85535
Subject: re:pcb layers on BGAs Spartan-3
From: calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid (calaf)
Date: Fri, 10 Jun 2005 11:18:18 -0500
Links: << >>  << T >>  << A >>
[I have laid out my first board using the FT256. I have not had it
fabricated yet. It is 4 layers 6/6mil track/space. The real killer
was
the size of the vias. I used 1 solid groundplane and planelets for
VCCIO VCCAUX and VCCCORE. All IO voltages are the same which helps. I
was not able to route out all the IO. I have posted a PDF file
containing the PCB layers at http://dlharmon.com/dspcard.pdf Any
comments on whether or not it will have decent signal integrity would
be appreciated. Maybe it can provide some ideas.]

As far I can gather I find some issues: There are some disposition of
vias on the 2.5V planelet that reduce significatively the path's
width for currents (and therefore it raises the impedance. I have
found quite interesting the method used to take the 3.3V to the VCCO
pins but I wonder whether a trace (instead of a plane is not a
problem. Shouldn't a power plane be below or above all the pins of
the FPGA as it happens with ground planes?


Article: 85536
Subject: Re: computer upgrade time.
From: billh40@aol.com
Date: 10 Jun 2005 09:19:00 -0700
Links: << >>  << T >>  << A >>


Ray Andraka wrote:
> Time has come for a computer upgrade (I'm currently using a dual Athlon
> 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K,
> matrox dual head video with a pair of 19" monitors), but I haven't kept
> up at all with the computer market.  I'm wondering what people are using
> these days for high end designs (for simulation and PAR especially).
> I'd like something that doesn't sound like a vacuum cleaner and heat the
> room like a space heater this time around too, perhaps I need to
> consider liquid cooling?  ANy comments would be appreciated.  Yes, I
> admit I am being lazy.
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>     I am using a 2.6 GHZ P4 , XP PRO, DELL GX270, 2GB RAM, 7200 RPM IDE.
It takes 7 hours to  PAR for a V6000 at 83% utilization (28,400
slices).
Bill
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 85537
Subject: Re: Microblaze 4.0 with uClinux is ok or not?
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 10 Jun 2005 18:33:17 +0200
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag
news:42a9ae19$0$11352$3b214f66@tunews.univie.ac.at...
> >
> > Antti
> > PS after downgrading the microblaze to 3.0 www.hydraxc.com started to
work
> > fully with networking support!!
> >
> Antti,
>
> the features of hydraxc look good, but when will it be available?

pretty soon now, we had initital problems with the suppliers so there is
only a small batch manufactured but for actual production batch the date is
depending on the deliveries from two companies, the dates are confirmed
within 1 or 2 weeks from today, so shortly after that the product would be
available as well. The product is using pretty much smallest form factor
components from everything (well 0402 not 0201 but otherwise smallest
packages), so those tend to be hard to get. Like the 12MHz oscillator is
2.5mm x 2mm size, pretty cool! 3mm x 2.5 is nice already, but 2x2.5 really
funny thing.

As of today I can only confirm that the product is not just a PR
photoshooting dummy (as on the webpage!) but really assembled and working
unit. It boots uClinux from latest cvs update including networking support
and the USB HS OTG Chip is functional as well.

> What about pricing info?
>
pricing is somewhere on the web, or you can aske, I am not involved on the
marketing side

> One more point: Are you aware of the name clash of your product
> with an FPGA based chess engine. Probably the strongest chess machine
> at the time: http://www.hydrachess.com/

its known.

> Martin
>

Antti



Article: 85538
Subject: Re: pcb layers on BGAs Spartan-3
From: Sylvain Munaut <com.246tNt@tnt>
Date: Fri, 10 Jun 2005 18:39:51 +0200
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> "dlharmon" <harmon.darrell@gmail.com> schrieb im Newsbeitrag
> news:1118373181.586925.297720@f14g2000cwb.googlegroups.com...
> 
> 
>>I have laid out my first board using the FT256. I have not had it
>>fabricated yet. It is 4 layers 6/6mil track/space.  The real killer was
>>the size of the vias.  I used 1 solid groundplane and planelets for
> 
> 
> ??? How is it possible to fanout the balls on just 2 signal layers (1 layer
> is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
> (which leaves 4 layers for signals)?

With 4mil track/space, it's possible to escape all but a few of the 
signals on the top layer only. And you can connect the IO you can't 
escape directly to VVCO or GND to improve SSO.
You obviously don't escape all balls, only the signals. The power balls 
are connected thru via directly to the plane.

IIRC the "official" escape pattern for FT256 is 6/6 and uses top & 
botton layer only.


For the posted PDF, I find that the via restring is a little big and 
makes big hole in the powerplane. Most notably, the power distributed by
the "annular" power plane looks like it's seriously cut at some place.



	Sylvain

Article: 85539
Subject: Re: pcb layers on BGAs Spartan-3
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 18:43:32 +0200
Links: << >>  << T >>  << A >>

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42a9c242$0$329$ba620e4c@news.skynet.be...

> With 4mil track/space, it's possible to escape all but a few of the

Iam working on a design right now where we have to push a differential pair
between 1mm pitch balls. **** pinout.
But 4mil stuff isnt the thins you want. Expensive and not available from too
many companys.

> signals on the top layer only. And you can connect the IO you can't
> escape directly to VVCO or GND to improve SSO.
> You obviously don't escape all balls, only the signals. The power balls
> are connected thru via directly to the plane.

> IIRC the "official" escape pattern for FT256 is 6/6 and uses top &
> botton layer only.

I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the
number of rows/columns (assuming you have a complete ball grid without space
in the center. So for a 16x16 (FG256) you need 7 signal layers. To our
advantage, the inner balls are just VCC/GND, so you get away with 4 signal
layers.

Regards
Falk




Article: 85540
Subject: Re: re:pcb layers on BGAs Spartan-3
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 18:46:51 +0200
Links: << >>  << T >>  << A >>

"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> schrieb im
Newsbeitrag news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

> problem. Shouldn't a power plane be below or above all the pins of
> the FPGA as it happens with ground planes?

This is the better solution (if you have the layer available) but split
power planes are OK too. Just be carefull, dont use these as reference
planes for high speed lines, this can bite you.

Regards
Falk




Article: 85541
Subject: Re: Gated clock question
From: "Berty" <wooster.berty@gmail.com>
Date: 10 Jun 2005 10:01:28 -0700
Links: << >>  << T >>  << A >>
More over sometime gated clock is the only way as clock enable will not
stop the power consumption.
If not all than most of the cellular phone in the market and similar
product which you want to work for long time but have limited power
supply work with gated clock.
So you CAN have RELIABLE gated clock design.
Saying so obviously this should not be the normal route but the
exception one.
Have fun.


Article: 85542
Subject: Re: pcb layers on BGAs Spartan-3
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 10 Jun 2005 17:01:37 GMT
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3gtr2mFe8vkdU1@individual.net...
>
> ??? How is it possible to fanout the balls on just 2 signal layers (1
layer
> is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board
> (which leaves 4 layers for signals)?
>
> Regards
> Falk

Top layer takes front 2 rows of balls out without vias.
The next two rows come out the bottom layer with vias.
Both situations take 1 signal between ball or via.

Now - there are 4 signals left in the 5th row for the Spartan3 in the FT256
package - what about them?

By spreading the fanout from the center out, there's a cross where vias
aren't populated.  If one can fit two extra signals where the via would have
been (easy) the inside 2 vias on the 5th row can route to the open channel
and the 4th row vias for the center 2 rows fan out toward the center.  The
outside 2 vias on the 5th row fan out, changing the 4th row vias from inward
fanout to outward fanout.

Looks clean.  There's still room for another signal on the top layer in the
middle where the fanouts spread away from the center.

The ASCII art will look clean only if viewed with a fixed-space font:

| | | | | | | | | | | | | | | | | | | |
| O | O | O | O | |.| | O | O | O | O |
 \   \  |  /   / /   \ \   \   \  |  /
  O   O | O   O /  .  \ O   O   O | O
            .--'       `--.      /
  X   O   O'  X    .    X  `O   O   X



Article: 85543
Subject: Re: computer upgrade time.
From: Eric Smith <eric@brouhaha.com>
Date: 10 Jun 2005 11:11:57 -0700
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:
> I'd like something that doesn't sound like a vacuum
> cleaner and heat the room like a space heater this time around too,
> perhaps I need to consider liquid cooling?

I've been thinking about using a Zalman Reserator fanless watar
cooling kit when I upgrade my machine to an Athlon 64 X2 4400+
(dual core 2.2 GHz), but I haven't tried it yet so I can't personally
confirm the claims.

    http://www.zalman.co.kr/eng/product/view.asp?idx=63&code=021

I've been happy with Zalman's other products, though.  I'm using their
CNPS7000B-Cu heatsink/fan on a Athlon 64 3500+, and it does a great
job of keeping the temperature down without much noise.

    http://www.zalman.co.kr/eng/product/view.asp?idx=141&code=005

But the X2 uses a lot more power (up to 105W, IIRC), and I suspect that
the Reserator will be able to keep it cooler than the CNPS7000B-Cu
would.

Zalman recommends distilled water for the Reserator.  I wonder whether
it's a good idea to add something to inhibit growth of microorganisms,
like a tiny amount of bleach?  If the thing is working properly, the
water won't get hot enough to kill all the critters.

Eric

Article: 85544
Subject: Re: computer upgrade time.
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 10 Jun 2005 20:24:07 +0200
Links: << >>  << T >>  << A >>

"Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag
news:qhwtp2qdxu.fsf@ruckus.brouhaha.com...

> Zalman recommends distilled water for the Reserator.  I wonder whether
> it's a good idea to add something to inhibit growth of microorganisms,
> like a tiny amount of bleach?  If the thing is working properly, the
> water won't get hot enough to kill all the critters.

Use alcohol.
NOO.
It would be a waste!!
;-)

Regards
Falk




Article: 85545
Subject: Re: pcb layers on BGAs Spartan-3
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 10 Jun 2005 11:34:58 -0700
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3gtukiFebfpaU1@individual.net...
>
> Iam working on a design right now where we have to push a differential
pair
> between 1mm pitch balls. **** pinout.
> But 4mil stuff isnt the thins you want. Expensive and not available from
too
> many companys.
>
Are you sure? I thought this was industry standard now. It's a 'no added
cost' feature from our pcb house.
>
> I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the
> number of rows/columns (assuming you have a complete ball grid without
space
> in the center. So for a 16x16 (FG256) you need 7 signal layers. To our
> advantage, the inner balls are just VCC/GND, so you get away with 4 signal
> layers.
>
Which is why you should use uvias. 4 mil track gap and microvias gets 8
balls deep out without a through via. The money you spend on uvias is easily
recouped on layers saved. And your SI is much better. Great for diff pairs.
Cheers, Syms.



Article: 85546
Subject: Re: re:pcb layers on BGAs Spartan-3
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 10 Jun 2005 11:41:31 -0700
Links: << >>  << T >>  << A >>
"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> wrote in message
news:jYGdnT7auunXIDTfRVn_vg@giganews.com...

> As far I can gather I find some issues: There are some disposition of
> vias on the 2.5V planelet that reduce significatively the path's
> width for currents (and therefore it raises the impedance.
>
The vias are plated through. With metal. Like Khan, you're thinking too two
dimensionally. Think like Mr. Spock.
>I have
> found quite interesting the method used to take the 3.3V to the VCCO
> pins but I wonder whether a trace (instead of a plane is not a
> problem. Shouldn't a power plane be below or above all the pins of
> the FPGA as it happens with ground planes?
>
No. That's why they invented bypass caps.
Cheers, Syms.



Article: 85547
Subject: Re: Mapping Dual Port Ram into Microblaze address space
From: "Marco" <marcotoschi_no_spam@email.it>
Date: Fri, 10 Jun 2005 20:49:15 +0200
Links: << >>  << T >>  << A >>
Many Thanks
Marco


"Frank van Eijkelenburg" <someone@work.com> wrote in message 
news:d477a$42a86ba6$3e3aa7a5$12385@news.versatel.net...
>
> "Marco" <marcotoschi_no_spam@email.it> wrote in message 
> news:d89oml$j4e$1@news.ngi.it...
>> Hallo,
>> I have created a user logic template for obp bus with Create/Import 
>> Wizard of EDK with the feature: user logic address range support.
>>
>> Into file user_logic.vhd I have created a Dual port ram with core 
>> generator to replace the ram example.
>>
>> Is it possible to map port B of dual port ram into microblaze address 
>> space?
>
> Yes, connect the address bits of the opb bus to your bram port. Make a 
> state machine which steers the enable and write_enable and the acknowledge 
> to the opb bus.
>
>>
>> In this way I could use a C pointer that points to microblaze mapped 
>> address space.
>
> Yes you can.
>
>>
>> Otherwise the only way to access it is to use Xio_in  and Xio_out ?
>
> AFAIK, you should always be able to access your custom device by using 
> pointers
>
>>
>> Many Thanks in advance to everyone
>> Marco
>>
>> Sorry for my bad english
>>
>
> 



Article: 85548
Subject: Re: computer upgrade time.
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 10 Jun 2005 18:50:56 GMT
Links: << >>  << T >>  << A >>
On Fri, 10 Jun 2005 11:51:02 -0400, Ray Andraka <ray@andraka.com>
wrote:

>Time has come for a computer upgrade (I'm currently using a dual Athlon 
>1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, 
>matrox dual head video with a pair of 19" monitors), but I haven't kept 
>up at all with the computer market.  I'm wondering what people are using 
>these days for high end designs (for simulation and PAR especially).  
>I'd like something that doesn't sound like a vacuum cleaner and heat the 
>room like a space heater this time around too, perhaps I need to 
>consider liquid cooling?  ANy comments would be appreciated.  Yes, I 
>admit I am being lazy.

I've just upgraded to a 3GHz Prescott Pentium 4 system.  Prior to this
I'd used dual-processor systems, but the hyperthreading feature seems
to let me run small stuff painlessly while a simulation or route is
running.  And speed is good, too.

Sad to say, it doesn't meet your "no space heater" criterion.  The
Prescott CPUs run very, very hot.

Bob Perlman
Cambrian Design Works


Article: 85549
Subject: Re: floorplanning
From: "Marc Randolph" <mrand@my-deja.com>
Date: 10 Jun 2005 12:43:02 -0700
Links: << >>  << T >>  << A >>
Paul Boven wrote:
> JJ wrote:
[...]
> > I wonder how much demand there would be for a realy slick and
> > commercial FPGA layout tool that had at least a basic model of the LUTs
> > and wiring delays that could be correlated with actual devices. I have
> > some ideas on this but other projects come 1st.

The following layout tools have correlated models of LUTs and wiring
delays:

Amplify from Synplicity
Precision from Mentor
And has Gabor said, PlanAhead, which now belongs to Xilinx.

> Having studied the datasheet quite well before getting into this, it is
> a lot easier for me to map a desired circuit into FFs, LUTs and the
> like.

Howdy Paul,

Mapping is a different issue than having good visability into actual
delays or floorplanning as the others have been discussing.
Interesting, but different.

> Learning VHDL or even using the schematic editor, feels like a
> terribly involved way to convince the software to configure those LUTs
> the way I want them.

Sorry - how exactly are you going to input your design?  Using FPGA
editor?  User/input-error would kill you, not to mention portability is
basicly zero - so you get to do it all again when you move from a
Spartan II to a Spartan IIE.

But to address your main point, the vendors typically DO provide a way
to do what you describe: you can instantiate the LUTs or FF's
individually with HDLs or schematic tools.  Then you're in full control
of how stuff is mapped.  Of course, this greatly hampers portability as
well because different chips have different primitives.

For designs of a few hundred to maybe a few thousand LUTs, I guess I
could see being able to map logic to LUTs manually.  For anything more
than that, do you really want to spend hours upon hours for even the
simpliest of designs doing what the tool could do in mere minutes with
(usually) acceptable results?

You'll also be missing out on non-obvious optimizations that the tools
could do for you.

In my mind, the main goal of HDL is to provide a standard method of
inputting a design that is mostly vendor independant.  A side benefit
is that in some cases, it provides efficient ways to describe more
complex functions.  If the tools aren't mapping logic correctly or
efficiently, they need to be improved, not thrown out.

> So yes, I can imagine some demand for a FPGA layout
> tool that stays this close to the hardware. But 'realy slick and
> commercial' probably would put it out of my reach.

The above three tools would probably fall into the really slick and
commerical category.

Have fun,

  Marc




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