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Let's get back to basics: As configuration approaches its end, there are three things that must happen: The internal global reset must be released The universal 3-stating of all outputs must end DONE must go High. The configuration options allow you to rearrange the sequence of these events anyway you like. Obviously, the clocking must continue until the last of these events is finished. And a few extra clocks never hurt. These are basic things that have been known and described ever since the early XC4000 days, more than 10 years ago. Peter Alfke Dave Garnett wrote: > "Berty" <wooster.berty@gmail.com> wrote in message > news:1119024451.072046.217090@z14g2000cwz.googlegroups.com... > > Some time ago I wrote a loader to load the Xilinx Spartan2 but this > > should be the same for the Virtex2 and Spartan3 as far as I know and > > when I checked back than the signal behave the done should only go > > active after the whole bitstream was loaded and the crc was ok. > > You can control when it will go using the Startup Option (By default it > > come before the output are enable and the internal reset is released). > > > > If the reason you are concern about good CRC is that if it is bad you > > want to try and reload or maybe load different bitstream than what I > > did was once I ended loading the bitstream I let 16 clocks pass and > > than checked the done. > > I don't recall why I use 16 clock as the startup don't let you > > delay for so long and probably count to 6 should be enough but ... > > > > Have fun. > > > > > > I too have written a loader for Spartan II, and I can confirm that DONE > becomes active before the correct number of bits is loaded. At one point my > load code stopped clocking when it saw DONE go high - but the fpga would > then not operate. I now always send the correct number of clocks and then > check DONE and everything is fine ... > > Dave > > > > > Posted Via Nuthinbutnews.Com Premium Usenet Newsgroup Services > ---------------------------------------------------------- > ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY ** > ---------------------------------------------------------- > http://www.nuthinbutnews.comArticle: 85901
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:f7o0b19ausim06im1kgts07e9a5abhjfar@4ax.com... > On Wed, 15 Jun 2005 09:49:36 -0700, "Symon" <symon_brewer@hotmail.com> > wrote: > > > Here's one of our gadgets, built for the NIF laser... > > http://www.highlandtechnology.com/DSS/V880DS.html > > All the fast stuff is EclipsLite logic, pecl mode, and most of it is > single-ended except for a major clock which is a diff microstrip. > > If you want low jitter, you have to know The Secret. > I guess you might need to know more than one Secret!! I see why you refer all your stuff to the power plane, makes sense with the single ended stuff in your logic family of choice. (ECL is referred to ground, so PECL is referred to the power plane.) I tend to use exclusively diff pairs, LVDS, PECL and CML, referred to ground. Works fine. I wonder if diff pairs work slightly better referred to VCC? Hmmm. I see the single digit jitter you mentioned is RMS, not pk-pk. That makes it a little easier. Not that I'm not still very impressed! Cheers, Syms. p.s. As for Secrets, do you know where Syd Barrett lives?Article: 85902
In a crosspost apparently to cover all the bases, specifically to alt.sci.physics,comp.arch.embedded,comp.arch.fpga,comp.dsp,sci.image.processing, On Fri, 17 Jun 2005 10:07:50 +0800, "Kris Neot" <Kris.Neot@hotmail.com> wrote: >This idea is used to serve my old idea of "Image stabilization by means of >software.". What does that mean? You want to generate a signal that represents a change in the position (orthogonal or angular? both?), and use this to translate a digital real-time video image from a digital camera sensor to make it appear stable? >I was aware that it was difficult to find angular sensor that can run at >1MS/s. I will >have a cubic enclosure, two perpendicular walls are made of small/fast image >sensors. >I use a hanging ball and a laser to shine upon it. The image sensors will >detect the >exact location of the ball (hopefully 1000 times a second). When the >enclosure(thus >camera body) shakes, the ball will remain inert for that short period, Thus >the image >sensors can give a reading of the balls location and calculate the >displacement. This will give positional displacement, not angular displacement. Is that what you want? Also, I can think of several other ways of doing this. I'd probably use these things: http://www.analog.com/en/cat/0,2878,764,00.html > >Does this idea work? :) Yes, probably, sort of. ----- http://www.mindspring.com/~benbradleyArticle: 85903
I believe you are mixing two things, the DONE go high after the CRC is checked. The fact you need to give extra clock have nothing to do with the CRC checker. It has to do with the fact that the FPGA require few more clocks after the last data bit was received. Have Fun.Article: 85904
Un bel giorno Kolja Sulimma digiṭ: > There are three correct formulations possible for these facts: > - The devices will be be available for under US$2. > - The devices are not available for under US$2. > - The devices are available for <insert real price> 4- The devices are not available at all. -- asdArticle: 85905
Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I want to back into design, and instead of doing the same old uart/SERDES design I did years ago, I wanted to do something more challenging. Thanks, *** Alfredo.Article: 85906
On Fri, 17 Jun 2005 10:16:10 -0700, "Symon" <symon_brewer@hotmail.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:f7o0b19ausim06im1kgts07e9a5abhjfar@4ax.com... >> On Wed, 15 Jun 2005 09:49:36 -0700, "Symon" <symon_brewer@hotmail.com> >> wrote: >> >> >> Here's one of our gadgets, built for the NIF laser... >> >> http://www.highlandtechnology.com/DSS/V880DS.html >> >> All the fast stuff is EclipsLite logic, pecl mode, and most of it is >> single-ended except for a major clock which is a diff microstrip. >> >> If you want low jitter, you have to know The Secret. >> >I guess you might need to know more than one Secret!! I see why you refer >all your stuff to the power plane, makes sense with the single ended stuff >in your logic family of choice. No, I refer my stuff to *any* plane that happens to be handy! > (ECL is referred to ground, so PECL is >referred to the power plane.) I tend to use exclusively diff pairs, LVDS, >PECL and CML, referred to ground. Works fine. I wonder if diff pairs work >slightly better referred to VCC? Hmmm. Doubt it. Planes is planes. >I see the single digit jitter you mentioned is RMS, not pk-pk. That makes it >a little easier. Not that I'm not still very impressed! Well, you can't actually measure p-p jitter. >Cheers, Syms. >p.s. As for Secrets, do you know where Syd Barrett lives? > Pink Floyd? Now *that* is a noise source! JohnArticle: 85907
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1119026650.260592.64880@g44g2000cwa.googlegroups.com... > Let's get back to basics: > As configuration approaches its end, there are three things that must > happen: > > The internal global reset must be released > The universal 3-stating of all outputs must end > DONE must go High. > > The configuration options allow you to rearrange the sequence of these > events anyway you like. > Obviously, the clocking must continue until the last of these events is > finished. And a few extra clocks never hurt. So far so good. But the OP stated something like "When downloading the code, everything works fine except the fact that the DONE pine is going high before the last data is written (tested on XC2V250fg456 or XC3S50vc100: DONE goes high after writing the N-13th byte)." Maybe a miscount in the software routine? Which file format is used for downloading? *.bit, *.hex or *.mcs? Remember that *.bit has some (non constant) "garbarge" at the beginning, the real data stream starts after the sync sequence. Just my two (Euro)cents Regards FalkArticle: 85908
hi all, sorry to be a bit vague chaps, but where is the information about modular design - in particular the appnote/manual that talks about partitioning of clocks across quadrants, sharing buffers across quadrants, use of bufgmux (i think), that sort of thing. i can't find it anywhere online or in the ise install tree today - it's in the docsan section of the website i'm sure of it... thanks, timArticle: 85909
Falk Brunner wrote: [...] > So far so good. But the OP stated something like > > "When downloading the code, everything works fine except the > fact that the DONE pine is going high before the last data is > written (tested on XC2V250fg456 or XC3S50vc100: DONE goes high > after writing the N-13th byte)." > > Maybe a miscount in the software routine? Which file format is used for > downloading? *.bit, *.hex or *.mcs? Remember that *.bit has some (non > constant) "garbarge" at the beginning, the real data stream starts after the > sync sequence. I don't think it is a miscount... Berty has it right - the DONE pin going high doesn't indicate you've completed all the clocking that the FPGA requires. MarcArticle: 85910
David Brown wrote: > John_H wrote: > >> The text ALWAYS clearly states what the pricing timeframe and quantity >> are for the price. >> >> Engineers looking to design in a new part in large quantities are >> typically looking for production a little ways out. I would prefer to >> see 1H2006 pricing, but still... they make it clear. >> >> The pricing method is used by too many vendors so why should Xilinx >> say this snazzy new part is available for $XX now in small quantities >> when others are advertizing the "mature volume" pricing? >> >> If you know what the "typical markup" is for early adoption of a >> device or for small quantities of the part as purchased by your >> company, you can get a ballpark to the pricing without having to call >> for specifics. >> >> I'm surprised that the UWG makes illegal the practice of giving a >> price where the price is clearly marked with a note and that note >> supplies the timeframe and quantitiy. This is misleading why? We do >> have market realities to consider, after all. >> > > It is clearly misleading to say " *are* available" for a particular > price, when they are most definitely not available. Giving a 500k price > for a year in the future is stretching "mature volume pricing" quite a > bit, although it would not be unreasonable if the date and quantity were > quoted in the text, rather than as a small-print footnote. I don't > think anyone would consider the Altera Cyclone II press release to be > misleading or illegal: <snip> There are legal precedent cases where the fine print has been too fine, or too far removed, from the headlines, and also where the fineprint essentially contradicts the headlines. Lets look at a Xilinx example, [ to keep it balanced :) ] Headlines: Spartan 3E Get 100K gates for $2 Reduce system costs... Start saving today with devices now shipping fine print is on another page, where it finally * links to 2H2006. Since they cannot place that price on an invoice today, it puts them on thin-ice. ie you cannot _actually_ GET 100K gates for $2, but the headline clearly states you can. What next, prices for 2016, in euros? "Get 100K gates for 0.5e"* * estimated price, based on forecast yields, packaging laws, and current exchange rate trends... I'll leave it to others to follow the veracity of "Start saving today with devices now shipping" ... :) -jgArticle: 85911
"Berty" <wooster.berty@gmail.com> writes: > I believe you are mixing two things, the DONE go high after the CRC is > checked. The fact you need to give extra clock have nothing to do with > the CRC checker. It has to do with the fact that the FPGA require few > more clocks after the last data bit was received. > Have Fun. Thanks for all the comments so far. I know that the bitgen options can modify the startup behaviour and therefore a different number of clocks are required to finish the configuration process. Anyway, what I want to know is: When do I have to stop checking for CRC errors on the INIT pin? The loader I write should be used with different FPGA families and the project that creates the bitstream is not under my control, so I probably can't define the bitgen options. Even the hardware connections are not fixed, so there is some need for CRC checking during configuration. The bitsream I use is generated from an ASCII configuration file (.rbt). Here's a little correction of what I've observed: After writing the n-13th byte one of the I/Os that is an output goes high. After the next byte INIT changes to low and DONE changes to high. INIT is also used as an I/O in the design. Therefore I would suspect that at this time the internal GTS and/or GSR signals toggle and INIT switches from configuration to I/O. Therefoe the INIT toggling shouldnt be considered as a CRC error. So let's redefine the question as follows: How can I determine when to stop polling INIT for CRC errors? Do I have to know the bitgen options with which the bitstream was generated? Or can I simply ignore the INIT pin one (or more?) clock(s) before DONE goes high? Perhaps there is some application note that shows a little bit more details than the usual datasheets? GuenterArticle: 85912
On Fri, 17 Jun 2005 19:46:22 GMT, not@home.com (Tim) wrote: ok, found it - a combination of v2 platform guide and constraints guide (all the info just seems to flow into one when you're online). >hi all, > >sorry to be a bit vague chaps, but where is the information about modular design >- in particular the appnote/manual that talks about partitioning of clocks >across quadrants, sharing buffers across quadrants, use of bufgmux (i think), >that sort of thing. i can't find it anywhere online or in the ise install tree >today - it's in the docsan section of the website i'm sure of it... > >thanks, >timArticle: 85913
OP should look up "deblurring" algorithms. Ofcourse it helps to shoot a laser beam into space to get that vector. Also Micron (the DRAM guys) are in the cmos image sensor biz both commodity VGA camera stuff and apparently high end very high speed imagers that scan orders faster IIRC in the 1ms range. I am sceptical myself about cmos in general having bought some of that low end junk but Micron seem to have made real progress in bringing cmos upto ccd performance plus the integration. They bought out several imaging companies. I also looked at a job with a high speed ccd outfit, theres people out there trying to do 4kx4k in 1 ms with processors on the backside of the chip massively parallel, very interesting, very big $. perhaps that will help. johnjakson at usa dot comArticle: 85914
Take a look at the very end of http://www.xilinx.com/bvdocs/publications/ds099-2.pdf which is the Spartan-3 data sheet. It has a good description of the configuration process. It benefits from many previous generations, and it was compiled by Steve Knapp who has an excellent track record of providing good explanations. (used to be my claim to fame...) Peter Alfke, Xilinx ApplicationsArticle: 85915
I want to update my post on the availability of Spartan3. I called NuHorizons and was able to get a quote on XC3S200-4PQ208C097. I was told they are available in 6-8 weeks with a minimun order of 24 pieces - a tray. I regard this as good news, as the time frame is reasonable for my needs. Also I can validate that the information that Steve Knapp and Peter Alfke provided is correct, particularly in the benefit of adding the C097 suffix. I would add an observation. For those who are in the "inside" the information they have perhaps takes on a certain quality of reality that is different from those of us who are on the "outside." I am a small fish so far as selling products, so I rely on information posted on the disitributor websites. Over the course of the past several months I peridically logged on to see where supply was. As well I verified the availability through the Xilinx Web store. More recenly the supply seemed to disappear, which is what caused me some concern. I would concur with one poster about selling through the Xilinx store. I think this would be a good business decision, even if the sales benefit is nil or negative. Call it a marketing expense. There simply are times when a designer wants a couple of pieces and prefers to order directly rather than go through the hassle of dealing with a distributor (other than DigiKey.) I agree that this service, which is offered by Linear, Maxim, etc, makes a difference in terms of having assurance about supply. I hope Xilinx resumes this practice when supply from the 12" wafer stabilizes. So, thanks for the help.Article: 85916
Hello, I am trying to test file system on Compact Flash. Now, my configuration is following. 1. ML310 Board 2. Core : PowerPC (uni-processor system) 3. Boot : Using BRAM inside 4. OS : Standalone 5. Library added : XilFatFs The hw platform has been compiled and looks working. Also I have no problem to compile the code. Simply, the problem is that I can not open the file with "sysace_fopen" Is there anyone who has an example design that I can start with? Thank you in advance. Sewook WeeArticle: 85917
<someone92@hotmail.com> wrote in message news:1118955741.424815.78230@g47g2000cwa.googlegroups.com... > Hi, > I'm starting to learn FPGA programming (using a Xilinx Spartan II > 200K). I will use VHDL and already have bought VHDL books, but I think > I also need a general introduction to FPGA so I plan to buy a book on > FPGA. I found this one: > > FPGA-Based System Design by Wayne Wolf > > I would like to know if this book is any good, especialy for a beginer > like me. I also if it will be useful in the futur for some more > advanced stuff, or is it just a entry level book that you throw away > once you know the stuff. It's expensive, that's why I don't want any > chance. > > If you have any other suggestion it could be useful. what I'm really > looking for is an introduction on FPGA structure (CLB,IOB,BLOCK > RAM,etc..), not a VHDL or VERILOG programming book > > Thanks > CLB - Configurable Logic Block : Glob of logic. Different vendors will call their flavors different names, but typically there is logic and flip-flop(s); sometimes small memroy. Related terms: LUT, LE, PFU. IOB - Input-output Block : Goes in, goes out; sometimes both. Some vendors may throw some extra neat features in, such as termination, variable drive strength, selectable delays... Block RAM - small memory, but much bigger than what can fit in a CLB. Typically registered; often, variable dimensions. Sorry, I actually haven't read any "books" on FPGAs; I've just been designing with them for a decade. Xilinx, Altera, Orca (ATT/Lucent/Agere/Lattice?). PALs/PLDs before that. In the future, who knows. Would a book be all that useful? Might be, but I don't think it's necessary. There is a wealth of information (app notes, user guides, data sheets, tutorials) available for free on the internet, but sometimes it's useful to have all the information in one place. JasonArticle: 85918
"Peter Alfke" <peter@xilinx.com> wrote in message
news:1119046531.946406.80680@g44g2000cwa.googlegroups.com...
> Take a look at the very end of
>
> http://www.xilinx.com/bvdocs/publications/ds099-2.pdf
>
> which is the Spartan-3 data sheet. It has a good description of the
> configuration process. It benefits from many previous generations, and
> it was compiled by Steve Knapp who has an excellent track record of
> providing good explanations. (used to be my claim to fame...)
> Peter Alfke, Xilinx Applications
>
And if I am allowed a supplementary question ... I've recently been bitten
when upgrading ISE versions because the 'Compress Bitstream' option got set.
If this is on, then a .rbt file is produced which is shorter (not too
suprising !). Is there any way to determine whether a given .rbt file has
been compressed ? How has the compression been done - if I just send the
bitstream to the device will it decompress automatically ? How do I
determine how many clocks will be needed ?
Dave
Posted Via Nuthinbutnews.Com Premium Usenet Newsgroup Services
----------------------------------------------------------
** SPEED ** RETENTION ** COMPLETION ** ANONYMITY **
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Article: 85919when u become experienced in xilinx, they ain't useless files. every file serves a purpose. "Qi Sun" <qisun@NOSPAM_itee.uq.edu.au> wrote in message news:d8td87$sr3$1@bunyip2.cc.uq.edu.au... > Too many useless files. >Article: 85920
>Moreover a LUT of 256 byte has an acceptable size or is too big? >I know this is a stupid question, but I'm a newbye Get the data sheet for the chip you are considering using. Most recent FPGAs have blocks of RAM. If you aren't using them for anything else then a big LUT/ROM is a great use for them. If you have better uses for all of the then maybe you should do something else for this part of the problem. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 85921
"xilinx_user" <barrinst@ix.netcom.com> wrote in message news:1119048963.810504.59660@z14g2000cwz.googlegroups.com... >I want to update my post on the availability of Spartan3. > > I called NuHorizons and was able to get a quote on XC3S200-4PQ208C097. > I was told they are available in 6-8 weeks with a minimun order of 24 > pieces - a tray. > > I regard this as good news, as the time frame is reasonable for my > needs. Also I can validate that the information that Steve Knapp and > Peter Alfke provided is correct, particularly in the benefit of adding > the C097 suffix. > > I would add an observation. For those who are in the "inside" the > information they have perhaps takes on a certain quality of reality > that is different from those of us who are on the "outside." I am a > small fish so far as selling products, so I rely on information posted > on the disitributor websites. > > Over the course of the past several months I peridically logged on to > see where supply was. As well I verified the availability through the > Xilinx Web store. More recenly the supply seemed to disappear, which is > what caused me some concern. > > I would concur with one poster about selling through the Xilinx store. > I think this would be a good business decision, even if the sales > benefit is nil or negative. Call it a marketing expense. There simply > are times when a designer wants a couple of pieces and prefers to order > directly rather than go through the hassle of dealing with a > distributor (other than DigiKey.) > > I agree that this service, which is offered by Linear, Maxim, etc, > makes a difference in terms of having assurance about supply. I hope > Xilinx resumes this practice when supply from the 12" wafer stabilizes. > > So, thanks for the help. Received a notification yesterday that the Xilinx spartan3e starter kits won't be available until september 2005. AlexArticle: 85922
Lets consider an abstract machine generating a new word from in a finite
space at every its step in a deterministic way. We have a golden word (a
key). The goal is to get its index in the sequence of the words. That is,
once the generator has produced the key word, the machine stops and the word
counter keeps the resulting index.
The implementation of the design involves a "clock enable" MUX at each FF.
That is, the running generator will load next state on every clk while
stopped FSM will persist it state. The MUXes in this architure will be
controlled by the feedback signal
done = (current_word = golden_key)
Well, my question is about "clocked enable" efficiency in the ordinary
FPGAs. I am considering a design avoiding the feedback in order to maximize
generator's speed (and reduce hardware demands). We could start the
generator by pushing its reset input. Once the generator produces the
anticipated word at its output at some moment of time, we would latch the
index (result of computation) letting the machine rush further. We are not
interested in the machine anymore, we have obtained the result and can let
it blow up. How advantageous would be this 2nd design?
Article: 85923
Hi,
can we disconnect the power suppy to some Macrocells which
are not using in the design or functionality for a perticular time or
all the time, So that I can save the overall power consumption
Is there any arrangement is available in the CPLD to cut off
the power supply for unused Macrocells by using clock gating.
Please Answer this.
Regards,
Hima.
Article: 85924I recently attended an FPGA vendor seminar that included some discussion of SystemC, HandelC and MentorGraphicsC. I tried real hard, honest I did, to shift my mental paradigms, and try to see the benefit of the use of C to abstract-away the clock aspects of vhdl rtl. I would say the systemC marketeers did a real poor job bringing the hardware people along to their way of thinking. I suspect, however, that their arguements seem pretty common sense and obvious to software engineers, who know C and aren't familiar with what VHDL is all about (as well as hardware timing issues in general). Even some of the software engineers in the audience explicitely stated that they thought that C/C++ was NOT a rapid development language, which is why they switched away from C to begin with, to Python, etc. to begin with. Having sai all the above, let me now state the following: I find writting that writing clk'ed "PROCESS"s in vhdl to be both easy to do as well as very reliable - that is, vhdl processes JUST work as long as you know what your doing and set realistic timing constraints. Thats no problem for me. Most of my problems, however, are more "transactional" in nature - i.e. they have to do with communications between entities/processes across clock boundaries and/or interactions between data/signal producers/consumers driven by different external events. Not the timing within a process itself. So, driven by the nature of most of the tricky problems I have to deal with, I am obviously open to some way of analyzing my system on a transactoinal level so as to gain insight to the various design architectural issues - i.e. analyzing the tradoffs of different possible solutions to the problem at hand. However, being the engineer responsible for making the god damn thing work, I am obviously: 1. primarily interested in timing. Thats what I do - design "timing". 2. also interested in "implementation details" - though not necessarily vendor specific, I NEED to have the design process also participate in the implementation, otherwise its just taking project time away from the engineers and giving it to architects, without adding any value. 3. Its got to facilitate debugging. So if anyone has any introductory transactional analysis references, which aren;t SystemC vendor or approach specific, I'd appreciate it. Thanks for listening to my rant!
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