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Dear all, I would like to know if it's possible to create an interface from Virtex II-FPGA's to serial RS485 or RS232,please ? Do you have some application notes or technical issues for this problem,please? Thank you very much for your help. Best regards, Davide CaninaArticle: 63676
"trce -v" limits the report only reports on constrained nets. My guess is "trce -u -v", I am trying this now but I wanted to check if someone else had played with these options. Thanks, *** AlfredoArticle: 63677
Look at: www.fpga4fun.com
=> serial interface.
Good luck
Article: 63678you're right it is a bad design, but like i mentioned in my subject, i'm just a newbie getting to know VHDL and FPGA's... thanx for the tips ... found some good info (not only concering this problem) ... so thanx for your answer! kind regards y "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:sSsxb.26673$9P7.1856@newssvr29.news.prodigy.com... > "Yttrium" wrote: > > > ddr_clkx2 <= ddr_clkx2_out and locked; > > That's BAD design, as the the tools are saying. How bad? If someone > working for me did that they'd be on the street faster than the PERIOD > constraint on the design. > > Do a newsgroup/google/yahoo search for "gated clock" for more info. > > > > so how should i implement it and what they mean with CE pin? well i know > > what they mean but how should i implement it in VHDL for a VIRTEXII? > > This is right out of the "Language Templates" found under the "Edit" menu: > > -- D Flip Flop with Clock Enable > -- CLK: in STD_LOGIC; > -- ENABLE: in STD_LOGIC; > -- DIN: in STD_LOGIC; > -- DOUT: out STD_LOGIC; > > process (CLK) > begin > if (CLK'event and CLK='1') then > if (ENABLE='1') then > DOUT <= DIN; > end if; > end if; > end process; > > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 63679
i'll check it out ... thanx for the tip kind regards, y "Marc Randolph" <mrand@my-deja.com> wrote in message news:dotxb.3054$NK3.1109@newssvr24.news.prodigy.com... > Martin Euredjian wrote: > > > "Yttrium" wrote: > > > > > >>ddr_clkx2 <= ddr_clkx2_out and locked; > > > > > > That's BAD design, as the the tools are saying. > > Agreed, it is not good FPGA design. > > But the crazy thing is that Xilinx has the ability to do this relatively > safely... but they don't seem to push it very hard and the tools don't > automatically use it for you. Check out the BUFGCE in the V2 and S3 > devices. > > Not portable, but usable. > > Marc >Article: 63680
In article <fXvxb.10154$ws.902245@news02.tsnz.net>, Jim Granville <no.spam@designtools.co.nz> wrote: >> Any processing rule which had two Vts for the different transistors >> would probably require a fairly substantial spacing between the two >> types. > >Why ? Sure, more steps will be needed - but spacing ? I'ts just an observation that anything special tends to require greater spacing as well as greater steps. I don't have/haven't seen any actual design rules with multiple Vt threshholds, but the most sophisticated I've delt with is .18 micron. Additionally, for all but FPGA, mixing high Vt and low Vt transistors very close would not be a huge benefit compared with just having the two. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 63681
"Yttrium" wrote: > you're right it is a bad design, but like i mentioned in my subject, i'm > just a newbie getting to know VHDL and FPGA's... To be sure it went across correctly, I wasn't criticizing you personally...just wanted to stress that this isn't a good idea in general. Think hardware design without an FPGA. Most of the same rules apply. A clock mux on a V2 will switch between clocks cleanly. That's a resource you can use. However, you need to have the right reasons to do so. If it's simply to keep a FF from latching an input, it's probably safe to say that this would be a bad idea. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63682
Hi there Anyone got experience with bying fpga dev. boards from www.digilientinc.com ? I ordered one a week ago but haven't heard from them yet (I also tried to send an email ) GNArticle: 63683
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:dlPxb.27551$ZS.24820@newssvr29.news.prodigy.com... > "Yttrium" wrote: > > > you're right it is a bad design, but like i mentioned in my subject, i'm > > just a newbie getting to know VHDL and FPGA's... > > To be sure it went across correctly, I wasn't criticizing you > personally...just wanted to stress that this isn't a good idea in general. Yes, i know ;-) ... just wanted to stress that fact hehe ... > > Think hardware design without an FPGA. Most of the same rules apply. > indeed indeed, i think the main problem was getting used to the fact that VHDL is a programming language but it designs hardware. so you tend to think to much in a software way, but i'm learning not to :-) > A clock mux on a V2 will switch between clocks cleanly. That's a resource > you can use. However, you need to have the right reasons to do so. If it's > simply to keep a FF from latching an input, it's probably safe to say that > this would be a bad idea. > > i couldn't use the solution with the ce FF because the system clock is on the same clock as on of the output clock signals from the DCM so that would have divided the frequency by 2. but i looked at the BUFGCE component and that seems to have solved the problem (warning) but i'm still looking if the BUFGMUX. but for now the BUFGCE seems to be the solution ... thanx, for the comments and help, kind regards, Yttrium > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 63684
"GN" <Guenther@FJERNES.softhome.net> wrote in message = news:y2Qxb.7290$yI6.1545@news.get2net.dk... > Hi there >=20 > Anyone got experience with bying fpga dev. boards from = www.digilientinc.com > ? > I ordered one a week ago but haven't heard from them yet (I also tried = to > send an email ) >=20 > GN No problems what so ever. Did you try emailing sales ? Usually respond within a few days the couple of times I emailed them. Ring them, it can't hurt. AlexArticle: 63685
On a sunny day (Fri, 28 Nov 2003 23:31:32 +0100) it happened "GN" <Guenther@FJERNES.softhome.net> wrote in <y2Qxb.7290$yI6.1545@news.get2net.dk>: >Hi there > >Anyone got experience with bying fpga dev. boards from www.digilientinc.com >? >I ordered one a week ago but haven't heard from them yet (I also tried to >send an email ) > >GN Yes, arrived in Europe within a couple of days. It may be at customs, you will be contacted and will have to pay ....Article: 63686
Hello, As someone had previously posted, the warning messages that are issued by NGDBUILD when the core netlist is merged with your user-design are expected and normal. Any kind of "abnormal program termination" is never expected, and never normal. Quite simply, you should never receive a coredump or other abnormal program termination. Period. However, complex software systems are rarely ever perfect, so sometimes this kind of stuff happens. I urge you to file a case with the Xilinx support hotline to resolve the issue. Thanks, Eric Crabill Dean Armstrong wrote: > > Hi All, > > I am trying to synthesise the Xilinx example "ping" PCI LogiCORE using > Synplify Pro 7.0 and Xilinx ISE 5.2. > > I operate Synplify as detailed in the LogiCORE PCI Implementation > Guide, and then start the ISE Project Navigator to implement the > design. ISE fails at the translate stage with the output shown at the > bottom of this post. > > I am unclear as to where the error is in this process. The second > launcher message about PCI_LC_I.ngo seems a bit suspect, but does not > seem to be an error. > > I would appreciate any help that anyone could give me on getting past > this. I'm more than a little bit puzzled after playing with all the > options I can find to no avail. > > Regards, > Dean Armstrong. > > Started process "Translate". > > Command Line: ngdbuild -quiet -dd > e:\working\wireless\vhdl\pci\ping\synthesis/_ngo -uc > E:/working/wireless/vhdl/pci/xc2s100fg456_32_33.ucf -sd > E:\working\wireless\vhdl\pci\vhdl\src\xpci -p xc2s100-fg456-6 > pcim_top.edf > pcim_top.ngd > > Launcher: "pcim_top.ngo" is up to date. > Reading NGO file > "e:/working/wireless/vhdl/pci/ping/synthesis/_ngo/pcim_top.ngo" > ... > Reading component libraries for design expansion... > Launcher: The source netlist for "PCI_LC_I.ngo" was not found; the > current NGO > file will be used and no new NGO description will be compiled. This > probably > means that the source netlist was moved or deleted. > > abnormal program termination > ERROR: NGDBUILD failed > Reason: > > Completed process "Translate".Article: 63687
"Yttrium" wrote: > indeed indeed, i think the main problem was getting used to the fact that > VHDL is a programming language but it designs hardware. Well, technically it is an HDL ... "Hardware Description Language". The trick is to not think "sofware" at all and think that you are describing hardware constructs. That alone should keep you honest. > i couldn't use the solution with the ce FF because the system clock is on > the same clock as on of the output clock signals from the DCM so that would > have divided the frequency by 2. I'm not sure I follow this without having more context in terms of what the design is attempting to do. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63688
Digilent is a trustworthy company, we have dealt with them for years. But this is Thanksgiving week in the U.S., and many people are on a short vacation. Call or e-mail on Monday... Peter Alfke ============ GN wrote: > > Hi there > > Anyone got experience with bying fpga dev. boards from www.digilientinc.com > ? > I ordered one a week ago but haven't heard from them yet (I also tried to > send an email ) > > GNArticle: 63689
I write a module as below. Let's look the last ALWAYS block. In the case statement, It worked not as expected when I replaced the binary form's condition(2'b00,2'b01,2'b11, etc) with Parameter(IDLE_PHASE,NONSEQ_PHASE, SEQ_PHASE) each other, the FSM's state(ahb_state) always loop in the last state(default 2'b11). while writing as below, It seemed worked well. Simulating in the modsim SE PLUS 5.6, the waves showed the value of ahb_state always be 2'b00. whys? Thanks `timescale 1 ns / 100 ps module dma_controller( buffer_address, num_words, enable_dma, dma_req, dma_dir, //ahb master interface signals reset_n, dma_clk, dma_grant, dma_ready, dma_rdata, rddata, dma_lock, dma_addr, dma_busreq, dma_size, dma_trans, dma_burst, dma_wdata, dma_write, dma_resp, dma_readyo, //data and control signals for output of DMA set_irq, err_int, wrdata, wraddr, wren, rdaddr, rden, ahb_state ); input [31:0] buffer_address; input [31:0] num_words; input enable_dma; input dma_req; input dma_dir; input reset_n; input dma_clk; input dma_grant; input dma_ready; input [31:0] dma_rdata; input [1:0] dma_resp; input [31:0] rddata; output dma_lock; reg dma_lock; output [31:0] dma_addr; reg [31:0] dma_addr; output dma_busreq; reg dma_busreq; output [1:0] dma_size; output [1:0] dma_trans; reg [1:0] dma_trans; output [2:0] dma_burst; output [31:0] dma_wdata; output dma_write; output dma_readyo; reg dma_readyo; output set_irq; output err_int; reg set_irq; reg err_int; output [31:0] wrdata; output [9:0] wraddr; output wren; output [9:0] rdaddr; output rden; output [1:0] ahb_state; reg [1:0] ahb_state; assign dma_write = ~dma_dir; //dma_dir:0->write to sdram, 1->read reg [9:0] wraddr_sig; reg inc_count; parameter IDLE_PHASE = 2'b00, NONSEQ_PHASE = 2'b01, SEQ_PHASE = 2'b10; assign dma_size = 2'b10; //we always do unspecified length bursts to get maximum bandwidth out of the //PLD-to_stripe bridge assign dma_burst = 3'b001; reg [31:0] buffered_hrdata; reg [31:0] count_dma; reg dma_req_delay; wire start_trans; assign start_trans = ~dma_req_delay & dma_req; always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n ) dma_readyo <=#2 1'b1; else dma_readyo <=#2 dma_ready; end always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n ) dma_req_delay <=#2 1'b0; else dma_req_delay <=#2 dma_req; end always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n ) buffered_hrdata <=#2 32'h0; else buffered_hrdata <=#2 dma_rdata; end always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n) begin count_dma <=#2 0; dma_addr <=#2 32'h0000_0000; wraddr_sig <=#2 0; end else begin if(start_trans) begin count_dma <=#2 0; dma_addr <=#2 buffer_address; wraddr_sig <=#2 0; end else if(inc_count) begin count_dma <=#2 count_dma + 1; dma_addr <=#2 dma_addr + 4; wraddr_sig <=#2 wraddr_sig + 1; end else begin count_dma <=#2 count_dma; dma_addr <=#2 dma_addr; wraddr_sig <=#2 wraddr_sig; end end end /*look here*/ always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n ) begin ahb_state <=#2 2'b00; inc_count <=#2 1'b0; dma_busreq <=#2 1'b0; set_irq <=#2 1'b0; err_int <=#2 1'b0; dma_lock <=#2 1'b0; dma_trans <=#2 2'b00; end else begin case(ahb_state) 2'b00: begin $display(ahb_state); if( start_trans && dma_ready) begin ahb_state <=#2 2'b01; dma_busreq <=#2 1'b1; end else begin ahb_state <=#2 2'b00; dma_busreq <=#2 1'b0; end inc_count <=#2 1'b0; set_irq <=#2 1'b0; err_int <=#2 1'b0; dma_lock <=#2 1'b0; dma_trans <=#2 2'b00; end 2'b01: begin $display(ahb_state); if( dma_ready) begin ahb_state <=#2 2'b10; inc_count <=#2 1'b1; end else begin ahb_state <=#2 2'b01; inc_count <=#2 1'b0; end dma_busreq <=#2 1'b0; set_irq <=#2 1'b0; err_int <=#2 1'b0; dma_lock <=#2 1'b1; dma_trans <=#2 2'b10; end 2'b10: begin $display(ahb_state); if(count_dma == num_words[15:0] ) begin set_irq <=#2 1'b1; ahb_state <=#2 2'b00; end else begin ahb_state <=#2 2'b10; set_irq <=#2 1'b0; end if( dma_ready) inc_count <=#2 1'b1; else inc_count <=#2 1'b0; if( dma_resp == 2'b01) //error err_int <=#2 1'b1; else err_int <=#2 err_int; dma_busreq <=#2 1'b0; dma_lock <=#2 1'b1; dma_trans <=#2 2'b11; end default: begin $display(ahb_state); ahb_state <=#2 2'b00; inc_count <=#2 1'b0; dma_busreq <=#2 1'b0; set_irq <=#2 1'b0; err_int <=#2 1'b0; dma_lock <=#2 1'b0; dma_trans <=#2 2'b00; end endcase end //end else end //end always assign wrdata = buffered_hrdata; assign dma_wdata = rddata; //assign dma_wdata = 32'h5555aaaa; //assign rden = incr_burst_beat_counter && ~dma_dir; assign rden = inc_count & ~dma_dir; assign wren = inc_count & dma_dir; assign wraddr = wraddr_sig; assign rdaddr = wraddr_sig; endmoduleArticle: 63690
I want to know if there is anybody implemented the mpeg2 decoder in the fpga? Are there some resource about this topic.Article: 63691
Can I get suggestions for FPGA development boards that house the XC2VP70/125 Virtex 2 Pro FPGA? I have read the DINI specs and they seem to be the only one I can find that supports this FPGA. I want a board I can use to test network protocols like gigabit ethernet, and hence want to hook up either fibre or coax-ethernet cable to the board. Thanks AnupArticle: 63692
Error accumulates. 1% means that receiver accepts 9.9bit long farmes while transmitter transmits 10.0 bit-long frames. After re-transmitting 100 bytes (frames) we get 10-bit error. 10 bit is one byte, so 1-byte buffer is not enaught. The longer the stream the lager the buffer required. Infinite buffer is required for continous stream. As masters stated, UART was not designed for this purpose.Article: 63693
The VirtexII data sheet requires an input jitter for the DCM smaller than + or - 300 ps (in Low Frequency Mode). Obviously this ensures the proper behavior across all permitted frequencies and modes. In my case I have an input clock with 1ns of pk-pk jitter, but it is a 40 MHz clock, that I only need to shift by 90 (clk90), and to multiply by 2 (clk2x) other than having a locked version (clk0) of the original clock. How can I verify if it still works reliabily ? Or is the going to DCM loose lock ? Or will the phase relationships btw the output clocks not met ? -- Tullio GrassiArticle: 63694
As rs232 requires +/-15v, rs422 should be simpler cos Virtex should support differential signaling.Article: 63695
You can try using Timing Analyzer... Erez. "Alfredo" <iluvfpgas@yahoo.ca> wrote in message news:afaad421.0311280701.7ede144c@posting.google.com... > "trce -v" limits the report only reports on constrained nets. > > My guess is "trce -u -v", I am trying this now but I wanted to check > if someone else had played with these options. > > > Thanks, > > *** > AlfredoArticle: 63696
"valentin tihomirov" > Error accumulates. 1% means that receiver accepts 9.9bit long farmes while > transmitter transmits 10.0 bit-long frames. After re-transmitting 100 bytes > (frames) we get 10-bit error. 10 bit is one byte, so 1-byte buffer is not > enaught. The longer the stream the lager the buffer required. Infinite > buffer is required for continous stream. As masters stated, UART was not > designed for this purpose. Some UARTs are designed for this purpose - look at the data for Philips 26C94 families, and esp. the area of Sending fractional stop bits. -jgArticle: 63697
On Fri, 28 Nov 2003 17:47:46 +1100, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >Hi, > >I have a question about the Xilinx Timing Analyzer (trce). > >Does it report the I/O timing at the die pad or the package pin / >ball? > >I believe the 5.x and earlier versions of the software referred timing >to the die pads, whereas 6.x seems to be taking the flight delay of >the package into account. >Could someone from Xilinx please confirm whether this is the case? My local FAE explained that the 6.x software includes the package flight time in the Tiopick and Tiockp parameters *for flip chip packages*, i.e. the timing is referred to the ball rather than the die pad. The 5.x software does not include the flight time, i.e. the timing is referred to the die pad rather than the ball. Regards, Allan.Article: 63698
Hi, group, I plan to buy digilent combo board DIO2 combo. Does anybody know if a download cable will be included in the package? also, do they provide the software like foundation or webpack? I plan to implement some work of dsp, like FFT, FILTER. Hope this spartan II (200k gates) FPGA on this board helps. Has anybody tried that on digilent's board either? Thanks!Article: 63699
you guys seem to miss the point.. Async RS232 ALWAYS has mismatched clocks ... ALL async UARTs MUST be capable of handling this.. that's why there's flow control. You will find that 99.9% of them start looking for the start bit 1/2 way thru the stop bit. If you want to build a repeater then you will need a fractional stop bit generator OR you can over spec the crystal by 1.5% (or the baud rate generator) OR you add RTS / CTS flow control like everybody else. Simon "valentin tihomirov" <valentinNOSPAM@abelectron.com> wrote in message news:bqd493$1ter3o$1@ID-212430.news.uni-berlin.de... > Error accumulates. 1% means that receiver accepts 9.9bit long farmes while > transmitter transmits 10.0 bit-long frames. After re-transmitting 100 bytes > (frames) we get 10-bit error. 10 bit is one byte, so 1-byte buffer is not > enaught. The longer the stream the lager the buffer required. Infinite > buffer is required for continous stream. As masters stated, UART was not > designed for this purpose. > > >
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Compare FPGA features and resources
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