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Hal Murray wrote:
[...]
> Your idea would probably get used a lot more if there was
> an example all worked out. In particular, you need an assembler
> so that other people can use it as a skeleton. And as others
> have mentioned, you need an example that shows how the microcode
> gets through the tool chain and merged into the FPGA bit stream.
>
> What's a good toy example? Can we think of something semi-useful
> (toy) that would run on a demo board? It would need 50-100 states.
> I might be willing to hack together some software if somebody would
> do the rest of the work.
How about something better than just a toy, but nearly as easy to
describe? Something that could be donated to opencores and would
actually be reused would surely be more worth someones time (while still
useful to students and/or others wanting to see a real world example of
this). I'd be interesting in helping on a project like that.
Here is my idea that takes up a non-trivial amount of space in an FPGA:
Ethernet (especially GbE) has the ability to send PAUSE frames (I'll
just call them packets since that is what many call them). While a
device is receiving one of these packets, it must verify that it is
valid (say 16 bits at a time, for 64 bytes, including CRC). Once
verified, it outputs a hold signal for the amount of time specified in
the PAUSE packet. The hold signal can be used to stop transmitting data
in the opposite direction.
This is a simple state machine and could easily be put into BRAM(s),
using the BRAM to compare and validate each 16 bit word. There are
actually two different packets that are valid to receive (they differ
only in the first six bytes), hence there there are two valid states for
the first couple words, after which they will recombine to a single
valid state thereafter.
Now imagine this for a multi-port system. 24 ports aren't uncommon on
systems anymore, and you'd need a state machine for each port (or one
larger [and much faster] one that does context switches) to verify the
reception of the packets (possibly simultaneously).
You also need a "multi-port" timer that signals when it is ok to start
transmitting data again. Having 24 stand-alone timers seems like quite
a waste (although they can be quite slow since the unit of measure of
the "pause time" field is 409.6 ns at GbE rates).
> Has anybody considered using LUT sized ROMs for state machines?
> It doesn't seem likely to be practical but might make an interesing
> exercise. The classic traffic light controller or vending machine
> might fit.
I'm not sure why it wouldn't be practical, except that the amount of
resources saved (a couple LUTS) may not be worth the effort involved
(unless there was a program that just spit out the LUT contents for you,
as you have been discussing).
Marc
Article: 63376
Ken wrote:
>>If you are using RLOC's, aren't you making it Xilinx specific?
>>
>>Not only that, are RLOC's guaranteed to even be the same from one Xilinx
>>family to another Xilinx family?
>
>
> I would rather not use RLOCs - I just want to inform the tools that using
> the carry chain in one column is more important than any fancy optimisations
> that save a few slices but cause the fast carry chain to broken.
I agree - if the FPGA supports it, there is no reason the synthesis tool
shouldn't. I'd talk with the synthesis vendors about it if I were you.
Synplicity seems quite responsive.
Or perhaps you could get the synthesis tool to do what you are wanting
by placing a tiny period constraint on that portion of the design,
thereby forcing the tool will do everything in its power to make it
absolutely as fast as possible.
Marc
Article: 63377Marc, > I agree - if the FPGA supports it, there is no reason the synthesis tool > shouldn't. I'd talk with the synthesis vendors about it if I were you. > Synplicity seems quite responsive. I have emailed Synplicity support - they have been very good in the past and I expect they will be on this too. > Or perhaps you could get the synthesis tool to do what you are wanting > by placing a tiny period constraint on that portion of the design, > thereby forcing the tool will do everything in its power to make it > absolutely as fast as possible. Probrably could - but, the problem would then fall to another adder that is 1 microsecond behind the one just fixed. In a design with many adders, I think global control is needed to force use of the carry chains in one column. Cheers, KenArticle: 63378
We have some well-established teaching laboratory kit, using Xilinx XC4013E (optionally XC4020E for project work), with download by JTAG and a clone of Xilinx Parallel Cable III (DLC5). As has been discussed here before, despite some statements on Xilinx Website, the latest (full-spec) Xilinx software includes an iMPACT downloader which doesn't support Parallel Cable III. Alternatively, latest Webpack 6 includes an iMPACT which supports the download, but not any flavour of XC4000 (although all the library and similar files seem to be present). Options appear to be: 1) A kludge whereby we instal only iMPACT from Wepack 6, to get the downloading but with no integration into Project Navigator / Design Manager (so we lose revision control's updating of where to get the .bit file from). (This is what we're doing at the moment - not brilliant, but it does work.) 2) Someone spends time messing around to produce a collection of batch files which provide equivalent P&R function to Project Navigator. Suggestions welcome - including suggestions for alternative hardware. We need to retain 5V-compatible I/O, since all our kit uses 5V levels for I/O, and much of the work involves interfacing with other bits of kit. We've also spent quite a bit of money on the XC4k ICs - total of 25 pin grid array chips, which were hideously expensive - and we'd like to get a decent return on this investment. (In case it is considered relevant: workstations are networked PCs with Windows XP Pro, rest of development environment is ModelSim and Synplify. Students work in pairs, 12 pairs at a time in a class.) -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 63379
Al, XPLA3 (CoolRunner) devices are not going away. Steve Al Clark wrote: >We have been using Max EPM3032 and EPM3064 devices for several of our >designs. > >The features I like with these devices is as follows: > >1. Very Cheap - $1.30 for 3032 devices in small quantities >2. Easy tools with 74 style schematic capture entry. >3. 3.3V operation with 5V tolerant I/O > >The MAX 3000 is also a power hog which is the main reason I am searching >for alternatives. > >I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my >impressions based from their web site. I would appreciate comments. > >CoolRunner: > >1. Although they have these parts on their web site, they seem to be >deemphasised. This suggested to me that maybe this line is on the way >out. > >2. I like the 3.3V supply with the 5V tolerance. > >3. Power is lower than Altera, prices are higher. > >CoolRunner 2: > >1. Xilinx wants to sell these parts. >2. They use 1.8V supplies which is just about the only supply I don't >already need in my design. >3. They are not 5V tolerant which may or may not be important (but often >is) >4. They cost more than Altera Max 3000 or CoolRunner. > >Are the tools as easy as Altera? What's a good In-Circuit-Programmer? >Are there gotchas? > >What other players or parts should I consider? > >1. I want schematic entry, reasonably small size in QFP, low power and >low cost. > > > >Article: 63380
"Jeff Peterson" <jbp@cmu.edu> wrote in message news:369b6e8b.0311190715.4d66f38f@posting.google.com... > We are building a new radio telescope called PAST > (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) > which we will install at the South Pole or in Western China. > > To make this work, will need to sample (6 to 8 bit precision) dozens > of analog voltages at 400 Msample/sec and feed these data streams into > PCs. One PC per sampler. > > The flash ADCs we need are available (Maxim), but we are finding it > difficult to get the data into the PC. > > One simple way would be to use SCSI ultra640, but so far I have not > found any 640 adapters on the market. Is any 640 adapter available? > anything coming soon? > > or we could go right into a PCI-X bus. has anyone out there > done this at 400 Mb/s? is this hard to do? FPGA core liscense > for this seems expensive ($9K), with no guarentee of 400 mByte rates. > > is there a better way? > > thanks > > -Jeff Peterson Why dont you get an AGP Graphics processor, and try to connect your ADCs to the GPU Memory Bus. Run a PCI card for graphics on the PC. The GPUs are programmable , so you might even be able to do some processing inside... Since you only need 400 MSamples/S, you could live with the Maxims. If you want to get some real speed, then maybe something like the Atmel TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be of interest. Going up to Giga Samples per second, would make your problem worse though :-) http://www.atmel.com/dyn/products/datasheets.asp?family_id=611 -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 63381
On Thu, 20 Nov 2003 15:45:00 +0100 Martin Kellermann <martin.kellermann@nospam.xilinx.com> wrote: > Just instantiate a normal buffer (buf) and route the output of this > signal to the clock-input of the FF. That'll work. How can I do this in vhdl? thanks -- Mastupristi? Posted from X-Privat Free NNTP server - www.x-privat.orgArticle: 63382
"Al Clark" <dsp@danvillesignal.com> wrote in message news:Xns94386F2DBE553aclarkdanvillesignal@66.133.130.30... > We have been using Max EPM3032 and EPM3064 devices for several of our > designs. > > The features I like with these devices is as follows: > > 1. Very Cheap - $1.30 for 3032 devices in small quantities > 2. Easy tools with 74 style schematic capture entry. > 3. 3.3V operation with 5V tolerant I/O > > The MAX 3000 is also a power hog which is the main reason I am searching > for alternatives. > > What other players or parts should I consider? > > 1. I want schematic entry, reasonably small size in QFP, low power and > low cost. > You might want to check out the Atmel ATF1500 series. They are pincompatible with the Altera parts. Can convert easily the Altera files, and if you have size limitations, they will fit more into each device as well. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. > > -- > Al Clark > Danville Signal Processing, Inc. > -------------------------------------------------------------------- > Purveyors of Fine DSP Hardware and other Cool Stuff > Available at http://www.danvillesignal.comArticle: 63383
Well, Praveen, that's why I used this as an interview question... :-) Think of a shift register. Min clock period is the sum of clock-to-Q + routing + set-up time. Now assume that the downstream flip-flop is clocked earlier than the upstream one. You have lost that time from your clock period. That's lower performance! Take pencil and paper and draw the timing diagram... Peter Alfke ============================ praveen wrote: > > Hi peter, > > first of all thanks for your reply . But in your reply one of the > sentences was not clear here it goes. > > "Running the clock against the data flow sacrifices performance by > increasing the set-up time". > > what was not clear to me was you say that it sacrifices perfomance. > Could you please elaborate on what parameters it is based. > > rgds, > praveen > > > Peter Alfke <peter@xilinx.com> wrote in message news:<3FBBA6A5.D509B341@xilinx.com>... > > praveen wrote: > > > > > i have no of D flip flops cascaded now there are two ways clock can be routed. > > > > > > 1) in the direction of the data flow. > > > 2) opposite to the direction of the data flow. > > > > > > which of the above is good?? > > > > Good question, Praveen. Since 1988, every young engineer that I > > interviewed for employment here at Xilinx ( i.e. a couple of hundred) > > had to come up with an answer to that question. > > > > If you have a choice ( in an FPGA you should use global clocks, so you > > have no measurable delay difference anyhow) there is a trade-off: > > > > Running the clock against the data flow sacrifices performance by > > increasing the set-up time, but it is the safeest method, and therefore recommended. > > > > Running the clock in the direction of the data flow reduces set-up time > > and thus alllows a higher clock rate, but changes the input requirements > > in the direction of a positive (or more positive) hold time. If > > overdone, this can create a race condition, and "failure at any clock > > speed". > > Therefore not recommended. > > > > Peter Alfke, Xilinx ApplicationsArticle: 63384
Hi Vaughn, Thanks for the information. I tried DSE, and I am geeting and error saying "Error: DSE does not support the ACEX1K family!". > 1. Turn off "optimize i/o cell register placement for timing". That > option enables some aggressive optimizations for registered IO timing. > These optimizations can hurt internal clock frequencies (fmax). If > you are meeting your IO (Tsu & Tco) timing, but missing a clock timing > constraint, turning this option off may help. Yes, Iam meeting the IO (Tsu & Tco) timing. I turned of the "optimize i/o cell register placement for timing", but it did not make any difference. > 4. It sounds like you are using Quartus for synthesis. Make sure you > have "default logic synthesis style" = speed selected (this is the > default). It's under Settings->Default Logic Options Did you mean optimization technique? The optimization technique is set for speed. > 5. Make sure you've set all your timing constraints. I have set all my timing constraints. I could synthesize my code for Acex 1K100 using Leonardo without any timing issues. I used MAx +2 to complie the EDIF file generated by Leonardo. By using quartus, is there anyway that I could get the same speed that I got from LS and max +2? Thanks for your time. Thanks, Kumaran vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0311192112.253d35a@posting.google.com>... > Hi Manfred, > > Here are a few things you can try to meet timing: > > 1. Turn off "optimize i/o cell register placement for timing". That > option enables some aggressive optimizations for registered IO timing. > These optimizations can hurt internal clock frequencies (fmax). If > you are meeting your IO (Tsu & Tco) timing, but missing a clock timing > constraint, turning this option off may help. > > 2. Changing the fitter seed can let you search for a better fit. > Usually things only improve a few % if you search over several seeds, > but on some designs the gains can be larger. > > 3. You can automatically search for a better fit with the Design > Space Explorer (DSE) script that ships with Quartus. It will > automatically sweep the fitter seed for you, and turn on some hidden > try-harder options for placement, and save the best fit. For newer > familes like Stratix & Cyclone, it will also experiment with different > forms of physical synthesis and register packing, but those > optimizations are not available for the ACEX 1K family. > > To use DSE type: > > quartus_sh -t [quartus_install_dir]/bin/tcl_scripts/dse.tcl > > It pops up a simple, self-explanatory GUI. > > 4. It sounds like you are using Quartus for synthesis. Make sure you > have "default logic synthesis style" = speed selected (this is the > default). It's under Settings->Default Logic Options. > > 5. Make sure you've set all your timing constraints. > > 6. Send us the design, and we can check if there is some poor > optimization going on in either synthesis or the fitter. > > Hope this helps. > > Vaughn > Altera > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBB0854.A9C37455@yahoo.com>... > > If you are going to play with the seed, you need to try several settings > > before you can say it won't work. > > > > I once worked on a real b--ch of a design and my coworker set up a > > script that would run multiple passes overnight. That was the only way > > we ever got the thing working. he also had to write AWK scripts to > > parse the timing results since this was MaxPlus2 and the thing pretty > > well sucked for timing analysis. I believe Quartus is much better now. > > But it left a bad taste in my mouth for Altera software. I'll get over > > it some day... > > > > > > Kumaran wrote: > > > > > > Hi Manfred, > > > Thanks for your response. I am using the dedicated clock pin 79. I had > > > a look at other threads for optimizing the speed. Some one mentioned > > > that by increasing the seed in the fitter setting might increase the > > > speed, but, they also mentioned that there will only be a slight > > > improvement, and I saw a slight increase in the speed(not good > > > enough). Any other suggestions? Thanks for your time. > > > > > > Thanks, > > > Kumaran > > > > > > "Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>... > > > > It looks like you didn't use the internal Clock-Network. > > > > Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have > > > > the same delays of clock signal to each gate. > > > > Manfred > > > > > > > > > > > > "Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag > > > > news:40f2d3e9.0311171247.ab73d04@posting.google.com... > > > > > Hi all, > > > > > I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my > > > > > development using Leonardo Spectrum synthesizer(2002) and Max +2. My > > > > > license for leonardo expired, and I decided to use Quartus II(v3.0). > > > > > When I compile using Quartus, Iam getting a negative slack time for > > > > > one of my clock. when I compiled the same FPGA code using LS and Max > > > > > +2, I did not have any timing issues . In the compiler settings, I > > > > > have enabled the "optimize i/o cell register placement for timing" > > > > > option. I also tried different synthesis tool in quartus (FPGA > > > > > express, LS,..) but I could not get the timing right. Can anyone help > > > > > me? > > > > > > > > > > Thanks, > > > > > > > > > > Kumaran > > > > --Article: 63385
MM <mbmsv@yahoo.com> wrote in message news:bpg3er$1neeon$1@ID-204311.news.uni-berlin.de... > > The bigger downside here is that since the state machines took longer > > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > > ) my manager has warned me to find another job ( fat chance ) as he > > has handed in a review requesting a 20% pay cut ... but my real > > question is about the tools so I may do better next time > > I think you do need to find another job with a better manager! An error in > scheduling made by an engineer doesn't deserve a pay cut. If anyone deserves > a pay cut, it's a manager who didn't know a basic management rule: take an > engineer's estimate, multiply it by 2 and then use the next available unit > :) If he knew the rule he would celebrate the work finished way faster than > expected! Especially bearing this in mind... "it worked , after handing over the design to the test department they loaded a board and signed off on the design within a week. My fellow engineers were rather impressed since they knew how complex the control was" This would seem to demonstrate that careful up front design saved time in test and verification. I'd point that out to your 'manager' and his boss before telling him where to shove his job (after you've found something better). Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 63386
Manfred M=FCcke wrote: > BTW: Why do you restrict FIFO depths to powers of two? That would allow= =20 > trading memory usage versus implementation speed (like with altsyncram)= =2E Probably because FIFO storage is based on a ram, and ram comes in increments of one address bit. As Subroto said, the extra space from altsyncram MAXIMUM_DEPTH to the top could not be used as RAM in any case. -- Mike TreselerArticle: 63387
Tim, you have to get over the idea of still getting something from your old chip investment. Xilinx FPGAs have become 100 times (!) cheaper, have added functionality and better software support since the days when you bought the XC4013s. ( Anybody who tries to hang on to a 10-year old computer faces a similar situation, albeit to a lesser extent). That's the price of progress. Your biggest stumbling block is the 5-V compatibility, which stops you from using really modern (and cost-effective and sophisticated ) devices. Sooner or later you will curse the @#^%$*! 5-V standard. Why not do it now! Peter Alfke ============================ Tim Forcer wrote: > > We have some well-established teaching laboratory kit, using > Xilinx XC4013E (optionally XC4020E for project work), with > download by JTAG and a clone of Xilinx Parallel Cable III > (DLC5). > > As has been discussed here before, despite some statements on > Xilinx Website, the latest (full-spec) Xilinx software includes > an iMPACT downloader which doesn't support Parallel Cable III. > Alternatively, latest Webpack 6 includes an iMPACT which > supports the download, but not any flavour of XC4000 (although > all the library and similar files seem to be present). > > Options appear to be: > > 1) A kludge whereby we instal only iMPACT from Wepack 6, to get > the downloading but with no integration into Project Navigator / > Design Manager (so we lose revision control's updating of where > to get the .bit file from). (This is what we're doing at the > moment - not brilliant, but it does work.) > > 2) Someone spends time messing around to produce a collection of > batch files which provide equivalent P&R function to Project > Navigator. > > Suggestions welcome - including suggestions for alternative > hardware. We need to retain 5V-compatible I/O, since all our > kit uses 5V levels for I/O, and much of the work involves > interfacing with other bits of kit. We've also spent quite a > bit of money on the XC4k ICs - total of 25 pin grid array chips, > which were hideously expensive - and we'd like to get a decent > return on this investment. > > (In case it is considered relevant: workstations are networked > PCs with Windows XP Pro, rest of development environment is > ModelSim and Synplify. Students work in pairs, 12 pairs at a > time in a class.) > > -- > Tim Forcer tmf@ecs.soton.ac.uk > The University of Southampton, UK > > The University is not responsible for my opinionsArticle: 63388
Jim Granville wrote: > It is a good idea, but the SW tool side could need work to help it take > off.. :) I agree. This "block ram as state machine" needs a synthesis module generator so that it can be inferred from code. Otherwise, I have to leave the comfortable confines of a VHDL clocked process and I have two types of source code to maintain. -- Mike TreselerArticle: 63389
Hi, The latest version of XST in ISE 6.1 have an option to synthesize a state machine using BRAM as a resource instead of LUTs. It's called FSM_STYLE Göran Mike Treseler wrote: > Jim Granville wrote: > >> It is a good idea, but the SW tool side could need work to help it take >> off.. :) > > > I agree. > > This "block ram as state machine" needs > a synthesis module generator > so that it can be inferred from code. > > Otherwise, I have to leave the comfortable > confines of a VHDL clocked process and I > have two types of source code to maintain. > > > -- Mike Treseler >Article: 63390
> You need chipset specific code to enable access to the dimm after > boot, because it must start disabled to prevent windows from using the > memory. Easier! Just add /MAXMEM to Windows's BOOT.INI, and it will skip some of the BIOS reported memory. So, for the second sight, the think looks easier. > Anyway, an experiment of that type is likely to use an real time OS > anyway, neither windows nor plain vanilla linux. Maybe OS9 or VxWorks. Surely. -- Maxim Shatskih, Windows DDK MVP StorageCraft Corporation maxim@storagecraft.com http://www.storagecraft.comArticle: 63391
Maxim S. Shatskih wrote: >> You need chipset specific code to enable access to the dimm after >> boot, because it must start disabled to prevent windows from using >> the memory. > > Easier! Just add /MAXMEM to Windows's BOOT.INI, and it will skip some > of the BIOS reported memory. > So, for the second sight, the think looks easier. The trick is knowing which physical memory slots are affected by the BOOT.INI statement. An alternative is simply to grab physical memory address space for a device driver during the boot sequence and lock Windows out of it, DataCore uses that approach for it's cache in SANsymphony. -- Nik SimpsonArticle: 63392
Tim, The ISE Classics software <http://www.xilinx.com/ise_classics/index.html> supports the XC4000E devices. I'm not sure it includes iMPACT, but it does include JTAG Programmer software for downloading. Even though ISE 6.1i does not support design of XC4000E devices, it does allow you to program them with iMPACT. Steve Tim Forcer wrote: >We have some well-established teaching laboratory kit, using >Xilinx XC4013E (optionally XC4020E for project work), with >download by JTAG and a clone of Xilinx Parallel Cable III >(DLC5). > >As has been discussed here before, despite some statements on >Xilinx Website, the latest (full-spec) Xilinx software includes >an iMPACT downloader which doesn't support Parallel Cable III. >Alternatively, latest Webpack 6 includes an iMPACT which >supports the download, but not any flavour of XC4000 (although >all the library and similar files seem to be present). > >Options appear to be: > >1) A kludge whereby we instal only iMPACT from Wepack 6, to get >the downloading but with no integration into Project Navigator / >Design Manager (so we lose revision control's updating of where >to get the .bit file from). (This is what we're doing at the >moment - not brilliant, but it does work.) > >2) Someone spends time messing around to produce a collection of >batch files which provide equivalent P&R function to Project >Navigator. > >Suggestions welcome - including suggestions for alternative >hardware. We need to retain 5V-compatible I/O, since all our >kit uses 5V levels for I/O, and much of the work involves >interfacing with other bits of kit. We've also spent quite a >bit of money on the XC4k ICs - total of 25 pin grid array chips, >which were hideously expensive - and we'd like to get a decent >return on this investment. > >(In case it is considered relevant: workstations are networked >PCs with Windows XP Pro, rest of development environment is >ModelSim and Synplify. Students work in pairs, 12 pairs at a >time in a class.) > > >Article: 63393
On a sunny day (Thu, 20 Nov 2003 00:06:40 -0500) it happened "MM" <mbmsv@yahoo.com> wrote in <bphi42$1nue87$1@ID-204311.news.uni-berlin.de>: >> yes, repacking might allow a 64/66 PCI to accept the data. i worry >> that we will spend lots of time and money, but the margin will be >> insufficient for it to actually work. i have heard that some PCI >> cores are not too efficient. > >Spend money and time on what? With regards to PCI, I am pretty sure it will >work. You can ask PCI crowd on the PCI mailing list >(http://www.pcisig.com/developers/technical_support/pci_forum), they will >tell you for sure.And it doesn't have to be a core, you could use an >industry proven silicon, e.g. from PLX. I would be more worried about >processing all this data in your PC. I don't think any PC can do FFT's while >keeping up with such a data flow. Let's say you want to do 1024 point FFT. >At 400 MSPS it will take only 2.56 us to accumulate a new block of data. >The latest and greatest ADI ADSP-TS201S can do a 1024-point complex FFT time >in 16.8 microseconds. I doubt any of the Intel chips can do it faster. >AFAIK, TI DSP's aren't faster either. So, in my opinion you will either need >an array of fast DSP's or some sort of FPGA based processing. Trying to do >this kind of processing in host doesn't sound feasible to me. > > >/Mikhail > > A little while ago in sci.crypt there was some talk about the first optical processor. Basically this is an LED array with multipliers that can do 125 million complex 128 point FFT or 500000 DFT 16 K size per second. http://www.lenslet.com/newsItem.asp?showArchive=&newsId=184 www.lenslet.com The thing itself is a normal DSP with the optical array (you can buy that separately too). Normal logic, if you interfaced a FPGA you could go faster perhaps, those gallium arsenide LEDS switch at 20 GHz... No idea what it costs, perhaps less then you think. Download the datasheet .pdf, maybe it is of use... JPArticle: 63394
"Tero Rissa" <no_spam_for_me@thanks.invalid> wrote in message news:bpi8c4$6ls$1@harrier.doc.ic.ac.uk... > For similar situation, I had a script that translates assembly instructions > directly to .coe and .mif files and edits the ram initialization in the .edf. > In the case of a single block ram, the edit of .edf is quite trivial. If > you need more than one block, the words will be distributed between the > rams, which complicates the script a bit, but is also quite doable. > > On the other hand, regenerating the .edf is just one click in CoreGen. Sure, but the functional simulator in Foundation doesn't read the coe, mif, or edf file. I'm hoping to find the best possible way to allow the students to change their program and have those changes show up in both simulation and hardware. JPArticle: 63395
Mastupristi <cialdi_NO_SP@AM_firenze.net> wrote in message news:<20031120133639.00005b39.cialdi_NO_SP@AM_firenze.net>... > I use Xilinx ise web pack 6.1 sp 2. > > In my project I have a signal that is used as clock in only one flip > flop. > I have a constrain that place this signal on a generic iob. > > in the map process I obtain the following error: > Using target part "2s50eft256-6". > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol > "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be > LOCed to GCLKIOB site. > > How can I force this signal to be placed in a non-GCLK pin? > > thanks Check out the Xilinx Constraints Guide in the 6.1i SW Manuals for all sorts of attributes and directives you can use on your code. Specifically, http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0076_29.html describes the CLOCK_BUFFER constraint (you want "none") for synthesis.Article: 63396
The same holds true for CoolRunner XPLA3 devices (pin compatible with Altera devices (and they can be powered from fruit). Ulf Samuelsson wrote: >"Jeff Peterson" <jbp@cmu.edu> wrote in message >news:369b6e8b.0311190715.4d66f38f@posting.google.com... > > >>We are building a new radio telescope called PAST >>(http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) >>which we will install at the South Pole or in Western China. >> >>To make this work, will need to sample (6 to 8 bit precision) dozens >>of analog voltages at 400 Msample/sec and feed these data streams into >>PCs. One PC per sampler. >> >>The flash ADCs we need are available (Maxim), but we are finding it >>difficult to get the data into the PC. >> >>One simple way would be to use SCSI ultra640, but so far I have not >>found any 640 adapters on the market. Is any 640 adapter available? >>anything coming soon? >> >>or we could go right into a PCI-X bus. has anyone out there >>done this at 400 Mb/s? is this hard to do? FPGA core liscense >>for this seems expensive ($9K), with no guarentee of 400 mByte rates. >> >>is there a better way? >> >>thanks >> >>-Jeff Peterson >> >> > > >Why dont you get an AGP Graphics processor, and try to connect your ADCs to >the GPU Memory Bus. >Run a PCI card for graphics on the PC. > >The GPUs are programmable , so you might even be able to do some processing >inside... > >Since you only need 400 MSamples/S, you could live with the Maxims. > >If you want to get some real speed, then maybe something like the Atmel >TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be >of interest. >Going up to Giga Samples per second, would make your problem worse though >:-) > >http://www.atmel.com/dyn/products/datasheets.asp?family_id=611 > > >Article: 63397
"Mastupristi" <cialdi_NO_SP@AM_firenze.net> schreef in bericht news:20031120133639.00005b39.cialdi_NO_SP@AM_firenze.net... > I use Xilinx ise web pack 6.1 sp 2. > > In my project I have a signal that is used as clock in only one flip > flop. > I have a constrain that place this signal on a generic iob. > > in the map process I obtain the following error: > Using target part "2s50eft256-6". > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol > "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be > LOCed to GCLKIOB site. > > How can I force this signal to be placed in a non-GCLK pin? > > thanks > > -- > Mastupristi? > > Posted from X-Privat Free NNTP server - www.x-privat.org The easiest way is probably to set the number of clock buffers in the proces properties in the synthesis options - Xilinx specific options. This is the number of clock buffers available to the synthesis process. If you set this to '0' then no clock buffers are available for the synthesiser and none are allocated. The clock buffers that you need in the rest of the design must be created with library primitives. I hope this helps, MarkArticle: 63398
> > Jim Granville wrote: > > > >> It is a good idea, but the SW tool side could need work to help it take > >> off.. :) > > "Goran Bilski" <goran@xilinx.com> wrote in message news:3FBD0BBD.9000306@xilinx.com... > Hi, > > The latest version of XST in ISE 6.1 have an option to synthesize a > state machine using BRAM as a resource instead of LUTs. > It's called FSM_STYLE You mean FSM_STYLE lets you choose between (guessing here) One-Hot, Binary, Gray Code, (whatever), or BRAM based ? Another solution to (complex) state engines appeared in the CR2 web seminar, for which Xilinx use the bland term (IIRC) 'Program Memory Integration' in the PicoBlaze. What this _actually_ does is rather more complex, and powerful. The Assembler creates a VHD file for simulation, which is run with the PicoBlaze core, to verify the design. Std soft core operation so far.... Turns out you can recompile both files, as you NOW have a VHD description of the whole system (Core + ASM.VHD) description, and the tools can optimise away redundant logic, and create a smaller/faster logic solution, that started life looking like a 'Tiny_uC and SW in small ROM', but is now whatever the tools optimise to. Not just a soft uC, but a squishy one :) -jgArticle: 63399
Hi all,
I have a small clarification. I am using Quartus 2 Tool for
Synthesis and Place and route of a PCI System. I want to know if we
can set some options for set up time for PCI Clock Seperately.
Thanks
Naveen
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