Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hal Murray wrote: > > >You can use Virtex or Spartan-II to interface with 5V PCI bus > >and retain full compliance per the specification. You can use > >any of our devices, even Spartan3 and Virtex2Pro, with the 5V > >PCI bus, but you need some level translators. This is certainly > >a functional solution (I've tested it personally) but it is not > >compliant with the letter of the specifications. > > Do you have any suggested parts for the level translators? I know > about the IDT QuickSwitchs. TI and other logic makers offer similar products. > >The specifications are pretty clear that you are allowed only > >one component, and that is your "PCI component" and all bus > >signals must attach directly to that one component. > > I don't really care about the rules just to check off the > boxes. I'm willing to cheat if I can convince myself (and > some friends?) that the total system will work solidly. > > There are two parts to that. One is in limited cases, say one > fewer card on the bus. The other is in any configuration legal > under the specs. As you must realize, the issue of how you connect to the PCI bus is one of signal integrity. To use a switch device to limit the voltages to the FPGA would make significant differences in the signals on the bus. I expect the routing lengths would be violated even if you could work around the rest. There are reasons for the specs and violating them will produce a design that may work in some, but not work with all systems. > How far did you bend the rules? How much testing/Spicing did > you do? > > Do modern FPGAs have a low enough pin capacitance so that the > added capacitance of something like a QuickSwitch fits the old > rules? Or are they fast enough to go through an honest repeater > type chip so there is only one bus load? I seem to recall that there is one signal pathway that has very little slack time and even without buffers FPGAs (perhaps ones of a couple years ago) have a hard time meeting the timing. Add a buffer in one direction or perhaps both and I expect all your slack is gone and then some. The added capacitance of a switch part will be *two* extra pins since the entire path through the switch to the FPGA will be the true path (unlike the case with a buffer). I expect this will also be a real problem in getting close to meeting the specs. > Mostly, I'm just curious. If/when I get enough time, I'd like > to build a hobby priced board that I can plug into something like > PCI. For now, that's old 33 MHz 5V PCI. Spartan-II seems like > the best bet. But the clocking in newer chips is attractive. > If there is a solid way to connect them to old PCI, I'd add that > to my list of chips to consider. Have you considered the Altera ACEX parts? They are fully 5 volt tolerant and claim to be PCI compliant, IIRC. > Maybe if I wait a bit longer low cost systems will be readily > available that have real 3V PCI slots. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63001
> How far did you bend the rules? How much testing/Spicing did > you do? > > Do modern FPGAs have a low enough pin capacitance so that the > added capacitance of something like a QuickSwitch fits the old > rules? With an Altera Cyclone part the pin capacitance plus that added by a quickswitch is just within the PCI 10pF/pin spec (Rev2.3) as long as you keep away from the Vref/IO pins. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 63002
Hello Jim, For the most part, I agree with your legal analysis regarding cloning cores. The primary issues have to do with whether or not an architecture is protected by patent and if not, how you market or use the resulting clone so as not to infringe existing copyrights, trademarks, trade dress or confidentiality/license agreements. But in my view, this is not the main issue with cloning an existing architecture. The main issue has to do with how you are going to debug it once you get it into an FPGA wherein it is completely embedded with no address or data lines coming out. Accordingly, I'd like to take this opportunity to simply state that I've posted developmental versions of both my 8051 and 6805 microcontroller cores for free downloading at www.quickcores.com. The 8051 is in original Verilog RTL format and includes on-chip JTAG real-time monitoring and debug logic, including 144-channel trace buffer. I've successfully synthesized them using Synplify and Quartus II web edition. If anyone would like to start a thread about how the JTAG real-time monitor works, I'd be happy to engage. Regards, Jerry D. Harthcock QuickCores p.s., I also have the 9-bit RISC which I'd be happy to post if anyone is interested. Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3FAFFAE7.2939@designtools.co.nz>... > Symon wrote: > > > > Hi Goran, > > So, playing devli's advocate, Xilinx wouldn't mind if the clean room > > Microblaze was targeted at their competitors' devices? Or do you think that > > no one would do this because Microblaze only efficiently fits the Xilinx > > devices? Or the competitors have their own solutions for their parts? > > I wonder.... > > Xilinx's protection does not come from attack on the clean room clone, > but rather from the protection of the Microblaze name, and tool flows. > So, anyone would be free to create an opcode compatible core, > if they wished, but not to use the brand, nor the Xilinx tool flows. > > Older uC cores are easier to copy (any patents lapsed), and their tools > are widely available. Things like 80C51, 6502, Z8, and even 8085.... > ( someone must have done a 8048 core ? :) > > -jgArticle: 63003
When i use the syntax:
attribute TNM of flop: signal is "test";
The TNM is attached to the output *net* of flop. I want to attach the TNM to
the *flipflop* itself (like I do on the schematics by attatching TNM on the
symbol) I also tried portmapping like this:
component FD
generic
(
TNM:STRING:="test"
);
port
(
D : in std_logic;
C : in std_logic;
Q : out std_logic
);
end component;
...and use this for my flop, but this TNM disappeared totally. Am I doing
something wrong?
Does anyone know how to do this properly?
Thx
Article: 63004Hello, I made a simulation by the means of a vwf-file. If I want to see the simulation results of signals which are neither inputs nor output what do I have to do? Is there a difference between registered signals and combinatorical signals? Thanks a lot. Best regards A.VazquezArticle: 63005
"Erez Birenzwig" <erez_birenzwig@hotmail.com> skrev i melding news:9eUrb.2$%o4.221@news.xtra.co.nz... > Hi, > > I'm trying to write some code for a 64 bit counter for a VirtexII. > > The problem I'm facing is that it has to run at least at 200MHz, and > therefore > a simple "a = a + 1" doesn't work (Xilinx rate the 64b counter to 114MHz). > > I've tried a split approach with four smaller counters and a selector > depending on the carry out of the previous stages but it only got me to > about > 180MHz. > > Did anyone ever had a similar problem and solved it ? > Unfortunately I'm not familiar with a pipelined implementation, I'll be > happy > to learn one. Just a thought: Run a 63 bit at clk/2 (100Mhz). reclock the 63 bit result at 200Mhz with a clock enable on the second 200MHz clock in the 100MHz domain. Use a logic accessible 100Mhz clock as bit0. Should work, shouldn't it?Article: 63006
Hi Jeroen, Please send me an email at my business address (jkempa -at- altera -dot- com) and I'll send you some C-source code that implements a simple set of IDE utilities for the CF card slot on our dev boards, using the IDE interface ports that are in the "standard_32" reference design. Jesse Kempa Altera Corp. "Jeroen" <dev@null.com> wrote in message news:<3fb220b6$0$58712$e4fe514c@news.xs4all.nl>... > Hi, > > I'm using a Altera Nios Cyclone dev.board (and the ref-32 design) and I want > to use the CF slot for a testapplication. I'm looking for some C code to > access the CF, so that I won't have to write it myself. Just code to issue > IDE commands and get the data from the CF. No filesystem etc. Does someone > know where I can find such code? > > JeroenArticle: 63007
Hi, Subroto Datta has already answered this to me, not so long ago. (Date: 2003-10-09) Search google groups for 'Quartus II simulation question' Very clear answer. Hope it helps, Christos Quartus II simulation question "Vazquez" <andres.vazquez@gmx.de> wrote in message news:eee19a7a.0311120747.55f699fb@posting.google.com... > Hello, > > I made a simulation by the means of a vwf-file. > > If I want to see the simulation results of signals which are neither > inputs nor output what do I have to do? > > Is there a difference between registered signals and combinatorical > signals? > > Thanks a lot. > > Best regards > > A.VazquezArticle: 63008
Why are we re-inventing complicated solutions to a simple problem? A perfectly synchronous counter solution has been described, using a 2-(or3-)bit front end driving the enable for the rest of the bits. If you want a fast counter (not incrementer!) then there is nothing to be improved or fixed. It's the best solution! Peter AlfkeArticle: 63009
Andres, let me explain: There is no app note, but it is really quite simple. Any Virtex BlockRAM can be loaded with data contained in the configuration bitstream. If you then never write again, you have a BlockROM. Obviously, a 4K x 4 ROM can detect anything on its 12 address lines, and describe it as a 4-bit output. This is all well-known. The trick that makes this solution so efficient is the use of the other port of the same BlockROM. The two ports are completely independent. There is no read port or write port. That's just a typical use when implementing FIFOs. You can use both ports to write, or - as in this case - you use both ports to read. Since you use the same priority encoding for both sets of 12 inputs, you can use the common ROM storage, and thus handle 24 inputs, giving you two sets of 4 outputs. It's the dual-ported nature of the ROM, and using the same encoding for both sets of 12 address inputs, that makes this so efficient. The rest of the logic, combining the two sets of 4-bit outputs, and handling the additional 8 inputs ( for a 32-bit encoder), will be conventional. I like using BlockRAMs for unconventional applications, especially since that relieves the interconnect structure, and - if you have more BlockRAMs than you need - its actually free (not just efficient) :-) Peter Alfke, Xilinx ApplicationsArticle: 63010
Hi, I am fairly new to Xilinx! I am looking to implement a System generator (SG) design with a Microblaze IP! How would one do this as I am a wear Xilinx does not provide intrinsic support for the PPC405 (V-II Pro) or Microblaze in SG? To do this, should one pull the design into EDK/XPS and implement the embedded design from there? What technique should I use to pull the design into EDK, if it's the case that I have to build MPD, PAO and BBD definitions along with VHDL definitions (does this take much time?) for the SG design would I not be better building my designs in Core Generator rather than SG? Regards SiArticle: 63011
I need to write a parser for Motion JPEG2000 data streams. I had hoped that there would be some code out there already, but google shows nothing. MPEG4 would also be a reasonable starting point, as atoms and boxes are fairly similar. Anybody know of anything out there? Thanks PeteArticle: 63012
OK, now it works, problem with webpack is it so often gives wrong messages, now it gave a correct on (I was using a pin differently) and I did not believe a word it said anymore.. So, the 1.4 V pp input video on a CTT pin with 3.3V supply. A r2r ladder on the comparator reference. A 8 step successive approximation, that looks at 0 / 1 from the input (video lower or higher then reference) gives 8 bit video. Because I only use 1.5 of 3.3V it is now 7 bits.. this can be changed. First thing was my DVD player, and is in color, even with 50 MHz clock. But VERY noisy, really bad... plenty of detail RF parts. But this noise, I think maybe the reference or comparator switch level is affected by everything else happening in the FPGA? I test with a second r2r ladder as DA to the output. Anyways, will try some more later, see if this can be made noise free? External comparator perhaps? Will see. I have biased the CTT at 1.5 V and AC coupled the video in. JPArticle: 63013
In article <borkg7$p06$1@cesium.transmeta.com>, H. Peter Anvin <hpa@zytor.com> wrote: >Some vendors have 9/18-bit blockRAMs, some don't. I'm trying to be as >generic as possible. It also makes it easier to port tools like >gas/binutils/gcc. Both Brand A and Brand X have midsize (8-16 bit wide + parity, with >128 addresses in that range) memories, and any other viable FPGA will as well. Thus it is safe to have parameterized cache and register file with instantiates the correct size memories, as part of your design, and still remain vendor neutral. You WANT to use these devices for both register file and memory. The thing that Brand A is missing are the SRL16/LUT as RAM features which give very small memories (16-64x1b), while Brand X all the BlockRAMs (midsized memories) are the same size while Brand A's memories come in different sizes. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 63014
In article <3FB16CEB.C46327DE@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >I am convinced that a generic version would inevitably be inferior in >performance and/or price, compared to the dedicated one. I know that Ken >and Göran used many Xilinx-specific features when they designed >PicoBlaze and MicroBlaze. And I assume that the Altera guys were >operating in a comparable way when they designed Nios. >The generic ones will be the "worst of both worlds", unless you really >believe in clairvoyant synthesis. I think generic will be inferior, but not THAT inferior, given the register files and caches can and should be done in the "everyone has" BlockRAMs. But in order to make it generic, these structures will probably need target-specific parameters and options (dual ported or not, size range) which are instantiated. Also, the other big disadvantage in the generic version is going to be a lack of placement. Placement is good for 10-30% performanec increases. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 63015
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:1068660401.172275@evisp-news-01.ops.asmr-01.energis-idc.net... [...] > So, the 1.4 V pp input video on a CTT pin with 3.3V supply. > A r2r ladder on the comparator reference. > A 8 step successive approximation, that looks at 0 / 1 from the input (video > lower or higher then reference) gives 8 bit video. Cool. [...] > But this noise, I think maybe the reference or comparator switch level is > affected by everything else happening in the FPGA? Random suggestions follow - you've probably thought about most of these already, but I'll offer them anyway :-) Do you *know* where the ground reference is that's used for the output pads that drive your R2R ladder? have you taken care to use output pads all in the same bank for that? Could you consider adding a second R2R and digitizing the video GROUND, also AC coupled in? Then subtract VideoGnd from VideoHot, add a suitable offset (presumably you're getting the offset by sampling the back porch somewhere?). This *might* help if both R2R DACs are driven from buffers that share a common ground, i.e. are very nearby on the chip. I've seen 7-bit SNR with very simply constructed R2R DACs on the output of FPGAs before now, but that was at quite low frequencies so the FPGA itself would have been much quieter. I say this because 7-bit should be plenty to get reasonably quiet-looking video. Finally, are you sampling a composite NTSC or PAL video signal? If so, what's happening about aliasing of the colour subcarrier? Wouldn't it be a good idea to sample at an exact multiple of Fsc? Let us know how you progress - it sounds fun. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63016
Good day gents,
I am wondering if VHDL (or Verilog) code exists =
in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric =
duty cycle.
Below some code can be found which generates a by-2 multiplied frequency =
- however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
-- Frequency Doubler using DFF
-- code in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo =3D 2*fi
end F2;
architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;
begin
process (clk) begin
if (clk 'event and clk =3D '1') then
q <=3D notq;
end if;
end process;
notq <=3D not q ;
clk <=3D (notq xnor fi) ;
fo <=3D clk;
end behav;
Article: 63017
You can't make a symmetric-duty-cycle frequency doubler in digital logic =
unless you have a precisely controlled delay element.
-Kevin
"Gazelle" <wmu@pandora.be> wrote in message =
news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code =
exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric =
duty cycle.
Below some code can be found which generates a by-2 multiplied =
frequency - however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
-- Frequency Doubler using DFF
-- code in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo =3D 2*fi
end F2;
architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;
begin
process (clk) begin
if (clk 'event and clk =3D '1') then
q <=3D notq;
end if;
end process;
notq <=3D not q ;
clk <=3D (notq xnor fi) ;
fo <=3D clk;
end behav;
Article: 63018
Hi Peter,
Yeah, the home built processor is great fun. I did a Xilinx VirtexII one
when the parts first appeared and learnt a lot about the carry chain, those
FMUX thingies, and the mighty 'mult_and'! It also teaches you a lot about
the dual port block rams and multipliers. I called it nanoblaze, kind of
halfway between Micro and Pico, because it used about 250 LUTs, 16 bits, 16
GP regs in a LUT RAM file, stack and program in a block ram, multiply
instruction with the hard multiplier. If you target a particular
architecture you can get suprisingly good performance, I got ~90MIPS in a
VirtexII-slowestgrade, non-pipelined, i.e. 1 clock per most instructions
including conditional relative jumps. Even single cycle interrupts!
Once again, as you can tell(!!), I found it great fun, and an excellent
way to learn about the fabric of the FPGA. Also, can teach you a lot about
floorplanning and performance optimisation. I also used it to learn PERL to
write the assembler, which was probably the best thing to come out of the
whole project! BUT... I'd almost certainly NOT use it in a commercial
product, too much documentation involved and soon every FPGA will have a
hard processor anyway.
Good luck, Syms.
"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bosgmt$n0i$1@cesium.transmeta.com...
> Followup to: <3FB15BB3.5B87@designtools.co.nz>
> By author: jim.granville@designtools.co.nz
> In newsgroup: comp.arch.fpga
> >
> > H. Peter Anvin wrote:
> > >
> > > I have no way to know how this is turning out. My current goal is to
> > > make sure it implements in < 1000 LEs on Cyclone, without using
> > > blockRAM for the register file.
> >
> > Isn't some form of BlockRAM a defacto standard on all
> > 'consider for new design' FPGAs - so not using that would
> > restrict your options ?
> >
>
> Some form thereof, yes, but I tend to run out of blockram a lot faster
> than running out of LUTs. Note that it's not that I'm saying you
> couldn't use it, I'm saying I want to be at < 1000 LE without using
> blockram. About 300-400 of that would be replacable with a blockram.
>
> -hpa
>
>
> --
> <hpa@transmeta.com> at work, <hpa@zytor.com> in private!
> If you send me mail in HTML format I will assume it's spam.
> "Unix gives you enough rope to shoot yourself in the foot."
> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 63019Hi: I noticed Coolrunner XPLA3 isn't on the "Products and Services" page at www.xilinx.com. I like these chips because of their 3.3V levels and 5V input tolerance, since I do a lot of TTL level interfacing with scientific instrumentation. Will the XPLA3 series be around for a few more years? Thanks. -- ____________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.govArticle: 63020
If you don't care about the 2f duty cycle, and are also willing to live with the affect of uncontrolled incoming duty cycle at f, causing alternating period length at 2f, then you can use the circuit described in TechXclusives "Six Easy Pieces". But if you need better defined timing, you need a DLL- or PLL-like structure, there is no way around that. Peter Alfke, Xilinx Applications ================ > Gazelle wrote: > > Good day gents, > I am wondering if VHDL (or Verilog) code > exists in order to make a frequency doubler in a normal > CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric > duty cycle. > Below some code can be found which generates a by-2 multiplied > frequency - however the duty cycle > is very assymmetrical ... > > Many thanks for your input ! > > Regards, > > Michel > > > -- Frequency Doubler using DFF > -- code in VHDL > library ieee; > use ieee.std_logic_1164.all; > > entity F2 is > port (fi : in std_logic; -- Input signal fi > fo : out std_logic); -- fo = 2*fi > end F2; > > > architecture behav of F2 is > signal clk : std_logic; > signal q : std_logic; > signal notq : std_logic; > > > begin > process (clk) begin > if (clk 'event and clk = '1') then > q <= notq; > end if; > end process; > > notq <= not q ; > clk <= (notq xnor fi) ; > fo <= clk; > > end behav;Article: 63021
Hi Praveen, Are you asking what power, given room temperature operation, would send the junction temperature to over 85 degrees Celsius ? Brendan praveen wrote: > John Blaine <john.blaine@xilinx.com> wrote in message news:<3F9FA363.7930A312@xilinx.com>... > > Praveen, > > > > It is difficult to estimate how much impact this will have on the power > > estimate. > > So let me take you through a few points: > > > > Using a post PAR estimate will allow XPower to have an accurate estimate > > of > > capacitance load on the internal routes so no problem here. If you are > > using post MAP > > where no SDF is generated then this is a large source of inaccuracy and > > is not > > recommended. > > > > Now lets look at the timing simulations tend to result in glitches. This > > switching translates > > into higher activity rates in XPower-> higher power. > > > > I would expect these to be fairly low load signals. Also if you have a > > fully synchronous > > design this effect will be limited. > > > > Your clocks will be set correctly (high power consuming nets). > > If you have met timing (verifed through timing analyser) then other > > heavy loaded signals like > > clock enables, should be set correctly. > > > > So in summary, if your design is post PAR, fully synchronous and has met > > timing, you should > > be OK an get an accurate power estimate. > > > > John > > > > praveen wrote: > > > > > hi all, > > > > > > i am calculating the power consumption using xilinx xpower. For > > > generating the VCD file i am not loading the SDF(Standard Delay > > > Format) during VSIM. Will it affect the power calculation. > > > > > > thanks in advance. > > > > -- > > hi john, > > as u said our design is fully synchronous and our entire design is > working on only one clock edge, and more over ther are no latches > inferred in our design , so chances of glitches are minimal. > > so not loading the SDF file will not make much differnce in th power > estimate i guess. > > one more thing i wanted to ask u regarding the power consumption, we r > using XILINX virtex 2p (XC2VP50 -6 FF1517) . what is the power that is > tolerable without providing heat sinks. > > praveenArticle: 63022
The assumed frequency is 1MHz, this is documented in SVF app notes and the iMPACT user guide. If you wish to get absolute time generated in the RUNTEST records you can use the associated preference (Edit->Preferences) Petter Gustad wrote: > In SVF files generated by impact there will be delay statements on the > form: > > // Loading device with a 'ferase' instruction. > ... > RUNTEST 15000000 TCK; > > What is the minimum delay as a result of this statement, i.e. what is > the assumed TCK frequency for impact generated SVF files? > > TIA > Petter >Article: 63023
Chris Carlen wrote: > Hi: > > I noticed Coolrunner XPLA3 isn't on the "Products and Services" page at > www.xilinx.com. > > I like these chips because of their 3.3V levels and 5V input tolerance, > since I do a lot of TTL level interfacing with scientific instrumentation. > > Will the XPLA3 series be around for a few more years? > > Thanks. > > > Please ask directly Xilinx to know the future of Coolrunner XPLA3. Coolrunner is not on the first page, because Xilinx want to seel new techno :-). But all spec about XPLA3, canbe found on xilinx webpage. Laurent www.amontec.com ------------ And now a word from our sponsor --------------------- For a secure high performance FTP using SSL/TLS encryption upgrade to SurgeFTP ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ----Article: 63024
>If you don't care about the 2f duty cycle, and are also willing to live >with the affect of uncontrolled incoming duty cycle at f, causing >alternating period length at 2f, then you can use the circuit described >in TechXclusives "Six Easy Pieces". Assuming the clock is always running and at least in the ballpark of 50-50 duty cycle... Can I fixup the duty cycle with a cap, inverter, and big feedback/bias resistor? If I'm willing to go off-chip and back in, will that work for the 2F clock? [Yes, DLLs/PLLs are good.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z