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"filippo" <filippdavid@yahoo.com> wrote in message news:18add487.0402071604.6589ebbe@posting.google.com... > I made a lot of changes: > - split IO_control in two modules : an io buffer (iobuf) and the > contoller (IO_Async) > - now it's totally asynchronous > - no more extra reg > - tried to split the big always in many little ones > > but now it doesn't work neither with modelsim, post place & route sim > results aren't nice. > The problem seems to be somewhere between iobuf and IO_Async because > when i try to write an address in ADDR it never arrives ? > The funny thing is that both modules work fine alone.. > <snip> > > // ciclo scrittura ADDR > > always @(posedge ALE) > > ADDR <= ibuf; This should be negedge instead of posedge - look at the timing diagrams. Or you can synthesize a latch that is transparent when ALE=1. > //ciclo scrittura rst > > always @(negedge NWR) > > if (ADDR == 8'b0000_0000)rst <= (ibuf[0]); > > else rst <= rst; All "always @(negedge NWR)" statements should use posedge instead. The data is not valid yet on the falling edge. > -------------------------------------------------------------------------- ----- > module iobuff(da,obuf,ibuf,dir); > > input dir; > > inout [7:0] da; > > input [7:0] obuf; > > output [7:0] ibuf; > > > > assign da = (dir) ? 8'bzzzz_zzzz : obuf; > > assign ibuf = (dir) ? da : 8'bzzzz_zzzz; > What is dir connected to? Also, I think you don't need a tristate bus for ibuf. -- GeorgiArticle: 65876
"Steve" <steve41@totalise.co.uk> wrote in message news:4d3ee211.0402090355.49f7aa40@posting.google.com... > So Xilinx /do/ fix their prices. Surely this is against competition laws?? If Xilinx colluded with other FPGA manufacturers to have a fixed price where each competitor agrees not to undercut the other, they would be guilty of price fixing -- this is not the case. When you go to the store to buy Tostitos (a different form of chips) you often see the price is pre-marked on the bag - surely this is a form of price fixing! In reality, this is setting a suggested price; some stores have a different price sticker on top of the pre-printed amount. Semiconductor manufacturers provide their distributors and sales people with price books that give parts and grades for what is available. There is no harm in this. Better prices can be had, but only if you TALK with the people involved, either the Xilinx sales folks or the distributor's sales people.Article: 65877
Rene Tschaggelar wrote: > > Ok. My points. It may work the way you described where there are > plenty of big companies doing big projects. Over here, many big > companies are a mere shaddow of themselves after the new economy > took over and they were rationalized to death or near death. > Many new small businesses took over the lead in applying technology. > I'm lucky that my distributor, selling Altera parts (amongst others), > takes the time to provide me with, compared with my sales volume, > excessive support. > Yes, we may talk about who the project is for. Ask your distributor how they will be compensated for the sales that go into the product you are designing. If they are lucky, you have been able to identify both the company you are doing this for as well as the product name. I was told that this information is "registered" with the manufacturer and they get credit for the sales no matter which distributor actually makes the sale. But if the product can not be tracked this way, they get nothing. There is also some incentive on your part (or your customer's) to provide this tracking info. If they quote you a better than list price to get the design win, this better price will only be good through that distributor since they get a price cut from the manufacturer. But other distis who are not on the registered design win will not get the better price and will likely have to charge a bit more. At least this is how it was described to me. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65878
Steve wrote: > > Rick Collins <spamgoeshere4@yahoo.com> wrote in message news:<402559B3.AFBBB736@yahoo.com>... > > Rene Tschaggelar wrote: > > > > The cost is at the FPGA representative, distributing the stuff. > > > They get the questions asked. > > > > No, the distis only have as much markup as the maker allows. I have > > been though the quotation cycle and nothing gets done without Xilinx > > authorizing it. > > So Xilinx /do/ fix their prices. Surely this is against competition laws?? I think I misspoke (or is it mistyped?). I should have said, the distis only have as much *markdown* as the makers allow. This is just a matter of the manufacturer giving a discount on a qualified design win. The disti is not going to sell the parts at a loss. So to get a better price the manufacturer has to agree to a lower price to the disti for this customer. I don't think that is illegal. Heck, they do this for the government all the time. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65879
"Pszemol" <Pszemol@PolBox.com> wrote in message news:c07n2k.2j4.0@poczta.onet.pl... > Hi there, > I use Quartus II v3.0 to work on my Altera designs and I have a problem. > > Recently I reorganized my hardrive and moved some folder locations... > My old projects open fine from new locations and all components are > found correctly when I double-click in the schematics window. > When I try to locate the component in the messages window (by double > clicking on the error line) the program cannot locate my files, telling > me that file does not exists. This file truly does not exists because > it is looked for in the *old* locations, somehow preserved in the project > file... > > Is there a way to fix the project files without redo all my projects? > I do not want the program to look in the old locations on my non-existing > e: drive. I moved everything to bigger c: drive but it does not work! > I have changed the location for my "User Libraries" in Settings, but > it did not help... Any other ideas? Hi, Try to go to: Project > Add/remove files in Project and there must be the files you need to change locations. hope it helps ChristosArticle: 65880
"Steve" <steve41@totalise.co.uk> wrote in message news:4d3ee211.0402070644.6fbcc3bd@posting.google.com... > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhvfmjde2i.fsf@ruckus.brouhaha.com>... > > Austin wrote: > > > Quite frankly, I am amazed at how folks think about this. You have > > > obviously never thought about that computer on your desk, and how it can > > > be sold for $499! Or even your car, just go price the parts > > > individually some time. > > > > Thomas Womack <twomack@chiark.greenend.org.uk> writes: > > > I've often priced the parts for building a computer, and they add up > > > to something within 15% of the price of buying the computer from Dell. > > > > You may have priced the subassemblies such as the motherboard, CD-ROM > > drive, etc. Try pricing the actual components (chips, passives, etc.) in > > small quantity. You'll be lucky if you can get a total BOM cost less > > than five times Dell's price. > > The total BOM cost in small quantities is irrelevant because you can > buy motherboards from as little as £40 (~$60) in the shops. The issue > is that if you buy Xilinx parts in large quantities then you're > alright, if you don't buy in large quantities then you have to put up > with high unit prices so those that want to buy high volume chips in > small quantities don't benefit from the economies of scale for these > parts. "The motherboard price is irrelevant because you can buy computers for as little as $299." The point WAS that buying the individual parts cost significantly more. The motherboards DO have huge production runs that push the cost of the bare board below $10 - a value I had considered absurdly low when I worked on projects with 25-125/mo production levels. With 1k-10k per month production levels now, we're seeing prices around $10 bare-board prices for our motherboard-sized assemblies. The motherboard manufacturers get large discounts because of volumes. The technical support goes to very few engineers for a short time to produce the massive quantity. The "Cost of Sales" is a very big factor in any industry and isn't much different for selling to a small company versus selling to a conglomerate for similar products (at very different volumes). The market works because small companies still make money (if they're properly managed by people who understand what it takes to build and sell products profitably). If small companies are mismanaged, they will fail. If large companies are mismanaged, they will go bunkrupt without management intervention. Weeding out the people with unrealistic ideas of what the market should do for them so they can make the profit they need (on a product that isn't worth what it *should* cost for the appropriate margins) will help to elevate the overall quality of products offered. Again, see Economics.Article: 65881
Greetings, Geir.
"Geir Botterli" <geirb@fokk.org> wrote in message
news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com...
> "John_H" <johnhandwork@mail.com> wrote in message
> <dcyUb.24$uo1.18709@news-west.eli.net> :
> >Use a single clock for the FPGA.
> >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth
(or
> >4*n-th) edge.
>
> I'm afraid I don't get how I should use clock enables to achieve this.
...
> Could you give an example on how to do this with clock enables?
If you have a 20 MHz clock but you want a 4 MHz counter and a 1 MHz counter,
you need to generate enables that are active every 5th and every 20th master
clocks. The counters themselves effectively "run" at 20 MHz in this case
but the enables slow that all down. You then need to look at how to apply
multi-cycle constraints to tell the place & route tools that all registers
fed by "div5" only need a 4MHz cycle time and the "div20" fed registers need
1 MHz timing constraints. Only the divide signals need to run at 20 MHz.
reg [2:0] div5cnt;
reg [1:0] div20cnt;
reg div5,div20;
always @(posedge Clk20)
if( div5cnt == 3'h4 )
begin
div5cnt <= 3'h0
div5 <= 1'b1;
div20cnt <= div20cnt + 2'b1;
div20 <= (div20cnt == 2'h3);
end
else
div5cnt <= div5cnt + 3'b1;
div5 <= 1'b0;
// div20cnt stays the same
div20 <= 1'b0;
end
always @(posedge Clk20)
if( div5 ) Counter4MHz <= Counter4MHz + 1;
always @(posedge Clk20)
if( div20 ) Counter1MHz <= Counter1MHz + 1;
Article: 65882King wrote: > I tried to open the example of xapp529.pdf in EDK 3.2.2 but found the > following error. > Reading MHS file C:\xapp529\system.mhs... > ERROR: system.mhs:120 Version 1.00.a of IP type xil_idct not found > ERROR: system.mhs:126 Instance xil_idct_1 of type xil_idct is excluded > from design The first error tells you that it couldn't find the peripheral. The second tells you that because of this, it will simply remove all instances of that peripheral from the design. Is "xil_idct" a custom core? Assuming it is, try to see whether you can see it in the Add/Edit cores tool in XPS. If not, then your peripheral path might be wrong. Look in the Embedded System Tools guide, in the Platform Specification Format -> Load Path. The '-lp' option gives the library path, but you still need to give the Library Name. From personal experience, this seems to be "my_periphs" by default for user cores. I haven't found how to change this, although I figure there must be a way. You can also put your peripherals into a "pcores" sub-directory in the main project directory and it should find it. I also seem to remember that some previous versions of EDK used "my_ip" (or something like) instead of "pcores", you might want to check that. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 65883
hey, I'm using the Xilinx CoreGenerator for the first time because i need a FIR filter and saw the DA FIR in the IPCore library and found it really usefull in this design. The only problem is dat i don't find how to generate a COE file? So i don't know how to turn a floating point coefficients (which i found through firdes or matlab) into a COE file? thanx in advance, kind regards, YttriumArticle: 65884
Jakub Dudek wrote: > Any review/feedback on those classes would be appreciated http://groups.google.com/groups?q=training+study+group%3Acomp.lang.vhdl -- Mike TreselerArticle: 65885
"g.k." <replay@newsgroup> wrote in message news:<40278e06$1@e-post.inode.at>...
> As there are no responces I'm wondering if there is anyone who has
> used the plugs-library and/or c++ on the nios softcore?
Sorry GK, I didn't catch your first post. Was on vacation far away
from internet access :)
I cannot be of too much help as I am not a c++ programmer, but I have
seen one customer (quite a while ago) who used C++ to create an
application with Plugs & Nios. It was a simple application to
send/receive data with a custom TCP application on a PC -- so I know
its possible.
The one thing I remember that was special was includes were inside an
"extern "C" { <includes here> } statement... like this:
extern "C" {
#include "excalibur.h"
#include "plugs.h"
#include "plugs_example_designs.h"
}
I don't believe there were any other special things required for the
project to compile.
I believe this is because the library files (plugs & Ethernet mac
driver) are compiled C files with no C++ about them... as I said
though I'm a c++ bonehead.
Jesse Kempa
Altera Corp.
jkempa at altera dot com
Article: 65886On the bottom of page 7 of the Virtex II DC and Switching Characteristics datasheet, a table shows that register-to-register performance of a 4:1 mux can reach 563 MHz. I'm just curious exactly how this was measured. Thanks, AdamArticle: 65887
Austin Lesea <austin@xilinx.com> wrote in message news:<c08aer$bnt1@cliff.xsj.xilinx.com>... > Steve wrote: > > Austin Lesea <austin@xilinx.com> wrote in message news:<c00e21$77m1@cliff.xsj.xilinx.com>... > > > >>Steve, > >> > >>Quite frankly, I am amazed at how folks think about this. You have > >>obviously never thought about that computer on your desk, and how it can > >>be sold for $499! > > > > > > > > I don't know about the US PC prices, but in the UK you can make your > > own PC for not that much more than you buy a new ready-built PC from a > > shop. Compare that to Xilinx where small quantities are a few hundred > > percent more expensive than in large quantities. > > > > Oh really? Really. If you bought all the components from a relatively cheap place like: http://www.scan.co.uk/ I'd bet you could make the same spec PC yourself for a similar price to what you'd pay for a built one from the UK's leading PC retailer: http://www.pcworld.co.uk/ > You can layout the motherboard, buy all of the components, fab the > motherboard, get all the eproms programmed, etc etc etc. Why would I want to lay the motherboard out, buy all of the single components etc etc blah blah when I can buy them from a shop?? The problem with Xilinx products is that unless you buy in large quantities you can't get them at a reasonable unit price. > Sure. What irrelevant "analogy" are you going to come out with next; FGPAs in small quantities are excellent value for money because try making your own out of individual transistors??... -- SteveArticle: 65888
Xilinx Docs -> Constraint Guide -> AREA_GROUP http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm Tungsten-W wrote: > Hi, there: > > I am doing a design which only covers 10% of the slices...but after P&R, it > spreaded all over the FPGA. > How may I constrain it into, say, one corner... > > How may I "nail down the logic into a known location"(Somebody told me this > trick)? > > BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't > be used... > > KelvinArticle: 65889
msm30@yahoo.com (William Wallace) wrote in message news:<7e4865b7.0402090716.baca77b@posting.google.com>... > steve41@totalise.co.uk (Steve) wrote in message news:<4d3ee211.0402070631.4ee1b54@posting.google.com>... > > Rene Tschaggelar <none@none.net> wrote in message news:<402405f0$0$714$5402220f@news.sunrise.ch>... > > Xilinx have a revenue of $1.2bn according to this: > > > > http://finance.yahoo.com/q/is?s=xlnx > > > > Are you seriously trying to say that the cost of an FPGA > > representative being asked questions has anything other than a > > negligible effect on the prices of FPGAs? > > In-state factory FAEs, Disty FAEs. Sales teams that must be incentivized > to drum up demand for new parts. Then customers who go out and convert > their FPGA to CGAs as soon as production ramps up. > > FPGAs are not like CPUs. They are often prototype platforms. > Low volume, abandoned by the customer as soon as the design is > stable and can be converted to a CGA or ASIC. Read the statements that the Xilinx suits say about ASICs vs FPGAs, they say that ASICs are frequently being *replaced* by FPGAs. > FPGAs are inexpensive in my view, In large quantities, not in small quantities. > and the software tools are > amazing. It's a good time to be an engineer. Do you work for a large company that buys FPGAs in large quantities by any chance? > But if you know a way to bring the equivalent of a Xilinx offering > for 25% of the price, join the marketplace, please. My point is that unless you buy in large quantities then small or start-up companies can't put Xilinx parts in their products because they're too expensive. -- SteveArticle: 65890
For the xc2v1000-5, the equation tcko + tnet + tif5x + tdxck = 493 + tnet + 826 (worst case) + 322 = tnet + 1641 ps This allows 135 ps for routing to meet the 563 MHz which - although small - may be very reasonable for (nearly) adjacent slices in the -5 speed grade. Also, the "worst case" number for tif5x may not be needed for a simple 4:1 mux. If you try to compile your own registered 4:1 mux, you should be able to see these numbers broken down to the timing elements like I've shown above in the Timing Analyzer, at least when the appropriate "View" options are selected. I got the numbers from the "speedprint" utility that's command-line accessible on our Solaris platform. "Adam" <unreal@rpi.edu> wrote in message news:qIQVb.50404$n62.1146@twister.nyroc.rr.com... > On the bottom of page 7 of the Virtex II DC and Switching Characteristics > datasheet, a table shows that register-to-register performance of a 4:1 mux > can reach 563 MHz. I'm just curious exactly how this was measured. > > Thanks, > > Adam > > >Article: 65891
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<40276573$0$9043$fa0fcedb@lovejoy.zen.co.uk>... > It's an oligopoly, it's in both their interests to keep low volume > prices up. > If you're a small company trying to get a novel product out it > can be a very big issue, FPGA pricing is likely to dominate > your overall product cost, making the product viable or not. Well summed up! -- SteveArticle: 65892
"Ville Voipio" <vvoipio@kosh.hut.fi> wrote in message news:i3kr7x4y48q.fsf@kosh.hut.fi... > > We have two CPLDs on a board (Altera EPM7256A and Xilinx > XCR3064XL) and would like to program them with a single tool. there is JAM for linux version at sourceforge compiling JAM is pretty easy, modifying for new hardware also patching: we had big big big problems programming Xilinx devices with JAM player anyway we tried the output files from iMpact just didnt work, not directly not via SVF2JAM I got some patch to fix some issues in JAM player, and I think wrote an utility to fix something in either SVF or JAM so got some thing to work. this info may be outdated I have not checked it with latest iMpact version maybe the compatibilty is better now antti xilinx.openchip.orgArticle: 65893
Apologies, I didn't read your post very carefully have you looked at this? http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf Chris Ebeling wrote: > Xilinx Docs -> Constraint Guide -> AREA_GROUP > http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm > > Tungsten-W wrote: > > > Hi, there: > > > > I am doing a design which only covers 10% of the slices...but after P&R, it > > spreaded all over the FPGA. > > How may I constrain it into, say, one corner... > > > > How may I "nail down the logic into a known location"(Somebody told me this > > trick)? > > > > BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't > > be used... > > > > KelvinArticle: 65894
praveen wrote: > I wanted the relationship between the number of iteration vs LUT table > entry. > Because i wanted to estimate the arc tan to a accuracy of 1 > microradians. > In my simulation i found that even if the iteration is around 25 > iteration i could not achieve the 1 microradian accuracy. Somewhere I have a databook from many years ago with a ROM look-up table for sine. This was when ROMs were much smaller than today, and pretty much the way it worked was to have one that was the high bits of the sine, and another that did linear interpolation. What domain and range do you expect for your arctan? For smaller values it shouldn't be too hard, but for larger values it gets much harder. What form is the input in, and what form do you expect the output to be? -- glenArticle: 65895
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:c08f4a$otj$1@sunnews.cern.ch... > Try to go to: > Project > Add/remove files in Project > and there must be the files you need to change locations. > > hope it helps Interestingly enough, it was enough to open this window and the problem is fixed... Somehow it relisted everything but I had to enter this window with the list of files. Thanks.Article: 65896
Subroto, Is there any chance a 64bit version of Quartus will be released? I got my 15+ min. builds down to 5+ by upgrading to the fastest available cpu, but I was thinking this process might benefit from the new 64 bit AMD and upcoming Intel procs. Thanks, Ken "Subroto Datta" <sdatta@altera.com> wrote in message news:jIsUb.19024$ZW5.17022@newssvr16.news.prodigy.com... > Ted, > If you can do send me the two archives of the design. The one which > compiles in the 7-8 minute range and the other one which has the addiitonal > logic added, and causes increased compilation time. We would like to analyze > the design. > > Thanks > - Subroto Datta > Altera Corp. > > "ted" <edaudio2000@yahoo.co.uk> wrote in message > news:c54bf83f.0402050212.74024e17@posting.google.com... > > I am compiling a design for the Acex EP1k50 using Quartus II version > > 3. The FPGA device is about 20% full, but I am finding compilation > > times are taking longer and longer (Currently 14 minutes) > > > > They also seem to be increasing disproportionatley to the amount of > > extra functions added. For example, compilation was taking 7-8 minutes > > last week. Since then I have only added very few functions, but > > compile time has been creeping up on a daily basis to the current 14 > > minutes. > > > > I have tried playing with the compiler settings under mode and fitting > > (as in "save more files for fast compilation") with little effect > > > > One odd thing I noticed is that if I remove a few source modules, > > compilation time stays at the full 14 minutes. > > > > It feels as though the compiler is getting bloated somehow, possibly > > by accumulating irrelevant data in some files somewhere. > > > > Is there anything I can do to alleviate this? > > > > I don't think the problem has much to do with the design itself, which > > is fully synchronous. Compilations for similar projects in the past > > have only taken 3-4 minutes. > > > > Any ideas anybody? > > > > ted > >Article: 65897
If you build something in small volume, everything is expensive: design effort, pc-boards, most components, testing, marketing, advertising, selling, servicing etc. You must have a really good product to absorb all these high costs. That's life. Peter Alfke ================================ Steve wrote: > My point is that unless you buy in large quantities then small or > start-up companies can't put Xilinx parts in their products because > they're too expensive. > > -- > SteveArticle: 65898
rickman wrote: > Rene Tschaggelar wrote: > >>Ok. My points. It may work the way you described where there are >>plenty of big companies doing big projects. Over here, many big >>companies are a mere shaddow of themselves after the new economy >>took over and they were rationalized to death or near death. >>Many new small businesses took over the lead in applying technology. >>I'm lucky that my distributor, selling Altera parts (amongst others), >>takes the time to provide me with, compared with my sales volume, >>excessive support. >>Yes, we may talk about who the project is for. > > > Ask your distributor how they will be compensated for the sales that go > into the product you are designing. If they are lucky, you have been > able to identify both the company you are doing this for as well as the > product name. I was told that this information is "registered" with the > manufacturer and they get credit for the sales no matter which > distributor actually makes the sale. But if the product can not be > tracked this way, they get nothing. > > There is also some incentive on your part (or your customer's) to > provide this tracking info. If they quote you a better than list price > to get the design win, this better price will only be good through that > distributor since they get a price cut from the manufacturer. But other > distis who are not on the registered design win will not get the better > price and will likely have to charge a bit more. > > At least this is how it was described to me. > I have some understanding for it. On the other hand I'm not complaining about prices. 20 years ago we made fast electronics with ECL. A few gates on a big board. Took a lot of power and it had to be tweaked for nanoseconds. The whole job then took us 6 months for the two of us. I can do the same now with just one small CPLD chip. With a doublesided layout. Say in 3 weeks. We recently had some faster wishes. Spend 100k for an ASIC. It didn't work out finally. The current CPLDs and FPGAs are excellent value. ReneArticle: 65899
Thanks to all that replied; I hope to contribute back to this group some day :) -Geir
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