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praveen wrote: > Hello, > I wanted the relationship between the number of iteration vs LUT table > entry. > Because i wanted to estimate the arc tan to a accuracy of 1 > microradians. > In my simulation i found that even if the iteration is around 25 > iteration i could not achieve the 1 microradian accuracy. > > My LUT i have represented using 32 bit and the two number whos atan is > to be obtained is also 32 bit(all fixed point). > > Please suggest a solution > with regards > praveen Go to my web site, http://users.erols.com/, look at my article "Quadratic Interpolation in Forth", and even it the article itself gives you no ideas, there's a link at the top that may. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 65901
http://www.mathworks.com/access/helpdesk/help/toolbox/filterdesign/coewrite.shtml If you can't use coewrite from Matlab, then use this format... ; ; XILINX CORE Generator(tm) Distributed Arithmetic FIR filter ; coefficient (.COE) File ; Generated by MATLAB(tm) and the Filter Design Toolbox. ; ; Generated on: 15-Mar-2002 13:47:15 ; Radix = 10; Coefficient_Width = 16; CoefData = -41, -851, -366, 308, 651, 22, -873, -658, 749, 1504, 21, -2367, -2012, 3014, 9900, .... "Yttrium" <Yttrium@pandora.be> wrote in message news:<DTPVb.4731$16.313447@phobos.telenet-ops.be>... > hey, > > I'm using the Xilinx CoreGenerator for the first time because i need a FIR > filter and saw the DA FIR in the IPCore library and found it really usefull > in this design. The only problem is dat i don't find how to generate a COE > file? > So i don't know how to turn a floating point coefficients (which i found > through firdes or matlab) into a COE file? > > thanx in advance, > > kind regards, > > YttriumArticle: 65902
Greetings DSP Guru's
Does anyone have experience with the Xilinx MAC FIR V3.0
I am interested in implementing a polyphase decimator.
The Xilinx data sheet is lacking in the timing department for the
polyphase decimator.
A simple simulation test seems to fail
Input a impulse -> output should equal the FIR coeffs.
The decimation is 4 and this is where the impulse is (@ sample 4)
The MAC FIR core works under this test without decimation.
Any insight would be appreciated.
Rgds
B.Onorato
Article: 65903On a sunny day (Mon, 09 Feb 2004 13:21:48 -0800) it happened Peter Alfke <peter@xilinx.com> wrote in <4027F9ED.F7C82422@xilinx.com>: >If you build something in small volume, everything is expensive: design >effort, pc-boards, most components, testing, marketing, advertising, >selling, servicing etc. You must have a really good product to absorb >all these high costs. That's life. >Peter Alfke Hey, of cause things are expensive. Now log in to www.microchip.com Find a PIC, you can enter a quantity and order right there. Whats your problem? Perfect for small business. WYSIWYGArticle: 65904
> > Jesse, > Thanks for that. We would expect NIOS II to be more 'tuned' > for Stratix II... > > Here's a question, (for when you can comment :) > Will NIOS II have a variant that fits/runs on MAX II devices ? > > -jg Hi Jim, I'd love to address that right now but can't -- stay tuned for the MAX II & Nios II launches. They will answer that question. - JesseArticle: 65905
I am kind of new to FPGA design and I have to understand a circuit given as a set of hierarchical .vhd files (top level and two-three lower levels), but it would be kind of nice to see it layed out on a piece of paper... Is there a tool to generate schematics from vhd files to visualize vhd?Article: 65906
Thank you Chris. I have read the xapp290... However I have defined AREA_GROUP on each modules of my design, now I need to restrain the P&R of a particular module to be within a corner of the module's AREA_GROUP instead... Best Regards, Kelvin "Chris Ebeling" <christopher.ebeling@xilinx.com> wrote in message news:4027E24B.10145AF8@xilinx.com... > Apologies, > I didn't read your post very carefully have you looked at this? > http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf > > Chris Ebeling wrote: > > > Xilinx Docs -> Constraint Guide -> AREA_GROUP > > http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm > > > > Tungsten-W wrote: > > > > > Hi, there: > > > > > > I am doing a design which only covers 10% of the slices...but after P&R, it > > > spreaded all over the FPGA. > > > How may I constrain it into, say, one corner... > > > > > > How may I "nail down the logic into a known location"(Somebody told me this > > > trick)? > > > > > > BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't > > > be used... > > > > > > Kelvin >Article: 65907
I would have assumed that given a real variable, LAPP, to divide it by two would simply be; LAPP / 2 But I get as an error, "no feasible entries for /". How would one divide through a real number?? - KingsleyArticle: 65908
I think that you're mistaking VHDL as some form of programming language. VHDL is a hardware description language, and as such it has no real knowledge of a divide. The only thing that a divide would be used for would be as an expression to form a constant. If you're trying to divide some non-constant value by two, then you have to ask yourself where this non-constant value is coming from, what kind of operation would need to be performed on it to divide it by two, and where you want the result to end up. Then you must design the logic to go between the input and the output of the divide operation (or alternatively use some prebuilt libray which already has such a design). I think that you should read an introductory book on VHDL, it should help you understand where you're going wrong with your approach. "kwaj" <k.otengNOSPAM@student.unsw.edu.auNOSPAM> wrote in message news:c09bq7$r6t$1@tomahawk.unsw.edu.au... > I would have assumed that given a real variable, LAPP, to divide it by two > would simply be; > > LAPP / 2 > > But I get as an error, "no feasible entries for /". How would one divide > through a real number?? > > - Kingsley > > > >Article: 65909
Hi Kenneth, > Is there any chance a 64bit version of Quartus will be released? We'll release a 64-bit version of Quartus when one is needed in order to address more memory. Windows XP maxes out at 3 GB (with a command-line flag), and Linux maxes out at ~3.7 GB. In all our testing of Stratix II, I don't think I've seen any compile (even on a 2S180) that required more than 2 GB of memory, and most compiles require much less than this -- and we get some very stressful, pathological designs from our internal test/product engineering groups. Also, as memory needs keep increasing due to larger and larger chips, we strive to beat down on the memory requirements of Quartus. In addition, architectural changes in Stratix II result in reduced memory consumption compared to the same design compiled in Stratix. So there is still plenty of room left before we _have_ to go 64-bit -- and we will be ready when the market needs a 64-bit version of Quartus. > I got my 15+ min. builds down to 5+ by upgrading to the fastest available > cpu, but I was thinking this process might benefit from the new 64 bit AMD > and upcoming Intel procs. Contrary to popular belief, the "bitness" of a processor does not (necessarily) equate with speed. The primary advantage of switching to 64-bit computing is the increase in (easily) addressable memory that you get with 64-bit pointers. You are limited in 32-bit machines to 4 GB of addressable memory (minus the up to 2 GB of address space the OS reserves). There are tricks to get this up higher, but aren't fun to program to. From a processing speed perspective, switching to 64-bit code may help and may hinder things. It can help in those cases where you would have had to break up something that wanted a > 32-bit representation across multiple integers. But most things fit fine in 32 bits, and promoting those variables to 64 bits just pollutes your data cache, effectively reducing the amount of cache memory available to the processor. And 64-bit code can be larger (because of larger pointers, instruction extensions, larger data values, etc.) thus chewing up valuable instruction/trace cache room. Luckily, recompiling C code to 64-bits does not change your integers to 64-bits -- just your pointers -- but this still has some impact on data and instruction cache consumption. I am glossing over many pros and cons of 32/64-bit code, but you get the idea. Intel plans to ramp the Prescott (90 nm version of P4) core up to 4 Ghz+, and AMD will be making Opteron/Athlon64 for years to come. As they up the speed, you will get more performance on your 32-bit applications. And you can bet future versions of the processors will support fast 32-bit processing, since it will take a LONG time before many programs make the switch to 64-bit. If you are interested in some early benchmarks comparing 32-bit and 64-bit x86 performance using a beta of Windows XP 64-bit, see http://www.anandtech.com/. Another bit of performance data: http://www.speg.org/. Do a search on results from "AMD Athlon" and click through to find results that were on the same machine, one running 32-bit windows, the other 64-bit SuSE Linux w/64-bit gcc compilation. On the few machines I looked at, the SPEC level was ~5% better on 32-bit. If you look at the "VPR" component of the SPECint test, this is an academic FPGA place and route tool, and it too yields something ~7-8% less speed on 64-bit x86. Of course, there could be immaturity of compilers, different OS efficiencies, etc. in here, but 64-bit will be no silver bullet when it comes to performance. Regards, Paul Leventis Altera Corp.Article: 65910
On Tue, 10 Feb 2004 15:03:11 +1300, "Bevan Weiss" <kaizen__@NOSPAMhotmail.com> wrote: >"kwaj" <k.otengNOSPAM@student.unsw.edu.auNOSPAM> wrote in message >news:c09bq7$r6t$1@tomahawk.unsw.edu.au... >> I would have assumed that given a real variable, LAPP, to divide it by two >> would simply be; >> >> LAPP / 2 >> >> But I get as an error, "no feasible entries for /". How would one divide >> through a real number?? >> >> - Kingsley try LAPP / 2.0 '2.0' is a real, and '2' is an integer (and the compiler hasn't been told to divide a real by an integer). This is unlikely to be synthesisable (depending on context) as Bevan suggested. Regards, Allan.Article: 65911
> The one thing I remember that was special was includes were inside an
> "extern "C" { <includes here> } statement... like this:
And for those C++ "boneheads" wondering what this does: It is equivalent to
putting an extern "C" modifier in front of all the function declarations in
the contained header file. Why is this needed? Because C++ uses
"name-mangling" to turn the user-friendly names you see in your code into
nearly unreadable function names that incorporate function name, type
information of the arguments, and likely some other stuff. The reason it
does this is that you can have overloaded functions that have same name and
different argument types, but the compiler wants to generate object code
that any old linker can properly link (I think). There are probably other
reasons (like, where else would it store the type info?) that I can't think
of.
Bottom line, by saying extern "C" you're telling the compiler that the
function will not have multiple variants and thus the compiler should use
the straight-forward name, which is just the function name with a _ in front
(assuming __cdecl calling convention) rather than the mangled name. This is
needed because the library you are linking to (or C files) were compiled by
a C-compliant compiler that did not mangle the names.
Besides linking to C code, this can be handy when cutting down on the size
of the debug information in your executable.
And just in case you're a C/C++ coder and were confusing this with calling
conventions (as I was until recently), C & C++ have the same default calling
convention (__cdecl). That is, there is no difference in the way they pass
function parameters and return values on the stack/registers -- they both
pass parameters on the stack with the caller responsible for stack clean-up.
Paul Leventis
Altera Corp.
Article: 65912Hi folks, I'm trying to get the modular partial reconfig flow going (as per XAPP 290). Details below - if anyone has any suggestions I'm all ears! I'm doing this all with ISE 6.1.02i (trying under both Linux and Windows XP, same behaviour/problems). As a first test, I successfully modularised my design, and implemented it using the modular flow described in the ISE documentation (Chapter 4 of the Development System Reference Guide). This all worked as expected. Next, I inserted the partial reconfig bus_macro between my two modules, and created a set of placement constraints that ngdbuild would be happy with. My toplevel design complies with all of the guidelines and rules I can find in the various bits of documentation about the partial reconfig flow (my hard-copy of XAPP290 is very well worn!). I can perform top level initial budgeting without errors or warnings (except the expected "assuming such-and-such is a module"). Doing active module implementation - I can MAP and PAR the individual modules, and export the PIMs. PAR reports failure due to some signals being unrouted. This concerned me, however I see that the same happens in the example distributed with XAPP290... I can perform final assembly on the pims and my toplevel, and it MAPs and PARs succesfully (all signals routed in final assembly implementation). There is one strange message in this final PAR during guide file processing: WARNING:Guide:147 - Design contains an unroutable situation due to existing islands. This may be caused by having an invalid NCD as input. Verify that the input NCD's were implemented correctly. However eventually PAR completes without errors or more warnings. Now here's the really wierd bit - if I try to load the placed and routed toplevel NCD file into either fpga_editor, or even bitgen, it causes that program to crash. Doing it on Linux I get a segfault, and on windows I get the standard "error in this application". So, somehow, the tools have build such a broken NCD file that it crashes the other tools. The "progressive" NCDs produced during the various lead-up phases seem OK - I can load them into FPGA editor etc. A couple of questions: (1) should the active module implementation phase "fail" with unrouted signals? I thought the purpose of the bus_macro was to lock all of them down, but seeing this behaviour in XAPP290 makes me wonder. (2) Has anyone ever seen bitgen or fpga_editor choke on an NCD produced by the implementation tools? (3) Is there some other step I need to take to get this going? If anyone has any ideas, please let me know. Thanks, JohnArticle: 65913
If you can, use Synplify for synthesis. Get the HDL Analist option. Otherwise, just use the bundles that come from the manufacturer. "Invisible One" <Invisible_1@sympatico.ca> wrote in message news:<hfuUb.8985$bp1.563899@news20.bellglobal.com>... > I am doing my thesis in artificial intelligence, and wish to create a "proof > of concept". It has been a long time since I have been working with FPGAs > directly and wish to know the following: > > 1 - What software and hardware tools are available that operate well under > Windows (compilation, etc...)? > 2 - Has anyone had any experience with programming AI's on FPGAa? Are there > tools available for FPGA development? > 3 - Are there any programmable logic devices out there that have a ADC built > in? > 4 - Are there any "tricks" that I would be able to use in order to generate > uniform, gaussian or Cauchy noise with a minimal of external hardware? > > Thank you in advance, I have posed many questions for a single posting! > > John.Article: 65914
Thank you all for the information. I will look into it immediately. If you have anything else to say, I will be surely monitoring this thread. John. "Invisible One" <Invisible_1@sympatico.ca> wrote in message news:hfuUb.8985$bp1.563899@news20.bellglobal.com... > I am doing my thesis in artificial intelligence, and wish to create a "proof > of concept". It has been a long time since I have been working with FPGAs > directly and wish to know the following: > > 1 - What software and hardware tools are available that operate well under > Windows (compilation, etc...)? > 2 - Has anyone had any experience with programming AI's on FPGAa? Are there > tools available for FPGA development? > 3 - Are there any programmable logic devices out there that have a ADC built > in? > 4 - Are there any "tricks" that I would be able to use in order to generate > uniform, gaussian or Cauchy noise with a minimal of external hardware? > > Thank you in advance, I have posed many questions for a single posting! > > John. > >Article: 65915
Jan Panteltje wrote: > > On a sunny day (Mon, 09 Feb 2004 13:21:48 -0800) it happened Peter Alfke > <peter@xilinx.com> wrote in <4027F9ED.F7C82422@xilinx.com>: > > >If you build something in small volume, everything is expensive: design > >effort, pc-boards, most components, testing, marketing, advertising, > >selling, servicing etc. You must have a really good product to absorb > >all these high costs. That's life. > >Peter Alfke > Hey, of cause things are expensive. > Now log in to www.microchip.com > Find a PIC, you can enter a quantity and order right there. > Whats your problem? > Perfect for small business. And you will pay some 3 or 4 times what you would pay if you were buying 1000's. I know, I have looked. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65916
hi,
i designed decoder in vhdl and i am going to map that on vertex-II
xilinx FPGA. Can any body have the idea how to calculate the power
consumption in that design.
thanking u all.
Article: 65917Hi, I've implemented an sdram controller on an fpga (to micron 128 MB memory) and tested it with a sequence of write and subsequent read bursts. In around 1 in 5 attempts, the correct read data appears on the dq[31..0] data bus, otherwise the memory read just returns 0xFFFFFFF. Could someone please give pointers to why might this be? Thanks, AnttiArticle: 65918
Many thanx for that great insight! Regards g.k.Article: 65919
Does anybody know where I can purchase a Pilchard or TKDM board? I'd
like to use one in a research project at UC Berkeley.
http://www.tik.ee.ethz.ch/~plessl/publications/fpt03/fpt03.ppt
http://www.cse.cuhk.edu.hk/~phwl/papers/pilchard_fccm01.pdf
- a
--
"Keep your thoughts positive because your thoughts become your words.
Keep your words positive because your words become your behaviors.
Keep your behaviors positive because your behaviors become your habits.
Keep your habits positive because your habits become your values.
Keep your values positive because your values become your destiny."
- Gandhi Ji
Article: 65920if you look on the Xilinx web-site they have power calculation tools, you need to know the resources used and the clock frequency, as far as I can remember. Ben "sunil" <inaganti_suni@yahoo.com> wrote in message news:9f28d282.0402092133.2190279@posting.google.com... > hi, > i designed decoder in vhdl and i am going to map that on vertex-II > xilinx FPGA. Can any body have the idea how to calculate the power > consumption in that design. > thanking u all.Article: 65921
Yttrium wrote: > hey, > > I'm using the Xilinx CoreGenerator for the first time because i need a FIR > filter and saw the DA FIR in the IPCore library and found it really usefull > in this design. The only problem is dat i don't find how to generate a COE > file? > So i don't know how to turn a floating point coefficients (which i found > through firdes or matlab) into a COE file? > > thanx in advance, > > kind regards, > > Yttrium The Active-HDL simulator has the similar built-in FIR core generator which accepts the floating point coefficients. Regards, A.Ser.Article: 65922
John Williams wrote: > A couple of questions: > (1) should the active module implementation phase "fail" with unrouted > signals? I thought the purpose of the bus_macro was to lock all of them > down, but seeing this behaviour in XAPP290 makes me wonder. This is normal. When you implement a single module with the routing restricted to module boundaries by the "MODE = RECONFIG"-constraint, you can't route signals that belong to other modules or to the toplevel. E.g., if you have bus macro communication from lets say the left module to the right, and try to implement the left module, you can't route the signals coming out of the bus macro on the right side, hence these are reported as unrouted. Same applies to open signals (like not connected busmacro pins) and top-level-logic signals, if any. So at least that is nothing to worry about. You can open the corresponding .NCD in FPGA Editor and let it list the unrouted nets. You'll find that all these signals are either not connected, or belong to another module in some way. > (2) Has anyone ever seen bitgen or fpga_editor choke on an NCD produced > by the implementation tools? Yes, this happens to me regularly... the entire design flow runs through without any error messages or unusual warnings, but in the end I get an .NCD that can neither be opened in FPGA Editor nor be converted to a bitfile. The main problem is that I cannot reproduce this behaviour, so I haven't opened a webcase for this yet. I think that even though the Xilinx support guys are without a doubt very competent, it's best if you can give them a simple as possible test design to reproduce the problem reliably. That way, they can get into it more easily. > (3) Is there some other step I need to take to get this going? Yes: Pray to the gods of Virtex, and a human sacrifice every now and then has been known to help was well... :) I've been working on partial reconfiguration for some months now, and run into new problems on a daily basis. I've seen so many "FATAL_ERROR" and "INTERNAL ERROR"-messages, that I could probably keep all of Xilinx support busy for a decade. The biggest problem is that there is no pattern behind this. Sometimes it works, most of the time it doesn't. If I find a combination of modules and cores inside the modules that works, it stops working as the moon shifts phases or I change the tiniest of things. Let's just face it: Partial reconfiguration is a market niche, purely academical, and the support in the tools just plain sucks. It works for simple designs with few modules, but as soon as it gets a little interesting the tools simply can't cope. It gets a tiny little bit better from ISE to ISE, but unfortunately new bugs are introduced as well. Just found one in ISE6.1 that sometimes causes top level logic to be placed incorrectly und makes par fail in the final assembly stage. No workaround available, no general rules as to what you can do to avoid it. Will probably be fixed in one of the first service packs for ISE6.2, which isn't even released yet. Bugger... But enough rambling and let's get back to your problem: The error message you get occured to me once. Basically it suggests that some components of a module have been placed outside of module boundaries somehow. I think this happened to me when I changed the area constraints of my modules causing the bus macros to be completely inside one of the modules. If that's not the problem in your case, I suggest you check the .NCD-files for each of the modules in PACE or Floorplanner and see if any components may have been misplaced. Other than that, it might help to just start over. If you do exactly the same thing twice with the same settings, results will vary considerably. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 65923
"Paul Leventis (at home)" <paul.leventis@utoronto.ca> wrote in message news:e%WVb.28093$R6H.7213@twister01.bloor.is.net.cable.rogers.com... > Hi Kenneth, > > > Is there any chance a 64bit version of Quartus will be released? > > We'll release a 64-bit version of Quartus when one is needed in order to > address more memory. Windows XP maxes out at 3 GB (with a command-line > flag), and Linux maxes out at ~3.7 GB. In all our testing of Stratix II, I > don't think I've seen any compile (even on a 2S180) that required more than > 2 GB of memory, and most compiles require much less than this -- and we get > some very stressful, pathological designs from our internal test/product > engineering groups. Also, as memory needs keep increasing due to larger and > larger chips, we strive to beat down on the memory requirements of Quartus. > In addition, architectural changes in Stratix II result in reduced memory > consumption compared to the same design compiled in Stratix. > > So there is still plenty of room left before we _have_ to go 64-bit -- and > we will be ready when the market needs a 64-bit version of Quartus. > > > I got my 15+ min. builds down to 5+ by upgrading to the fastest available > > cpu, but I was thinking this process might benefit from the new 64 bit AMD > > and upcoming Intel procs. > > Contrary to popular belief, the "bitness" of a processor does not > (necessarily) equate with speed. The primary advantage of switching to > 64-bit computing is the increase in (easily) addressable memory that you get > with 64-bit pointers. You are limited in 32-bit machines to 4 GB of > addressable memory (minus the up to 2 GB of address space the OS reserves). > There are tricks to get this up higher, but aren't fun to program to. > > From a processing speed perspective, switching to 64-bit code may help and > may hinder things. It can help in those cases where you would have had to > break up something that wanted a > 32-bit representation across multiple > integers. But most things fit fine in 32 bits, and promoting those > variables to 64 bits just pollutes your data cache, effectively reducing the > amount of cache memory available to the processor. And 64-bit code can be > larger (because of larger pointers, instruction extensions, larger data > values, etc.) thus chewing up valuable instruction/trace cache room. > Luckily, recompiling C code to 64-bits does not change your integers to > 64-bits -- just your pointers -- but this still has some impact on data and > instruction cache consumption. I am glossing over many pros and cons of > 32/64-bit code, but you get the idea. > > Intel plans to ramp the Prescott (90 nm version of P4) core up to 4 Ghz+, > and AMD will be making Opteron/Athlon64 for years to come. As they up the > speed, you will get more performance on your 32-bit applications. And you > can bet future versions of the processors will support fast 32-bit > processing, since it will take a LONG time before many programs make the > switch to 64-bit. > > If you are interested in some early benchmarks comparing 32-bit and 64-bit > x86 performance using a beta of Windows XP 64-bit, see > http://www.anandtech.com/. > > Another bit of performance data: http://www.speg.org/. Do a search on > results from "AMD Athlon" and click through to find results that were on the > same machine, one running 32-bit windows, the other 64-bit SuSE Linux > w/64-bit gcc compilation. On the few machines I looked at, the SPEC level > was ~5% better on 32-bit. If you look at the "VPR" component of the SPECint > test, this is an academic FPGA place and route tool, and it too yields > something ~7-8% less speed on 64-bit x86. Of course, there could be > immaturity of compilers, different OS efficiencies, etc. in here, but 64-bit > will be no silver bullet when it comes to performance. > > Regards, > > Paul Leventis > Altera Corp. > There are a few benifits of the AMD-64 architecture beyond the 64-bit width (in general I agree with most of what you've written here - it's a good explanation). In particular, the larger number of registers is a help in many types of application. Also, for some types of application, convenient 64-bit data items can lead to other benifits - for example, povray runs slightly faster in 64-bit mode than 32-bit mode on an Athlon-64, but more importantly it runs more accurately, giving finer detail. I don't know whether this could apply to tools like Quartus (povray deals with approximations to reality rather than absolute logic), but perhaps it might have benifits for simulation. Of course, for a real break-through in compilation speeds the key would be effective multi-threading, but I understand that that's a bit difficult for current algorithms.Article: 65924
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: : try : LAPP / 2.0 : '2.0' is a real, and '2' is an integer (and the compiler hasn't been : told to divide a real by an integer). What about substracting -1 from the exponent? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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