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Ray Andraka <ray@andraka.com> wrote in message news:<406A644A.67629932@andraka.com>... > You didn't mention your image size or pixel rate. Those are a factor in > determining the best approach. > > YunghaoCheng wrote: > > > Hi folks!! > > Now ,I am designing a real-time visual tracking system based on FPGAs. > > > > The images are captured by the CCD camera, and we do edge detection > > by using (Sobel-mask) 2D convolver. > > We also use two consecutive image > > frames I(k) and I(k-1) to subtracted pixel by pixel ,in order to > > find out the moving object. > > > > A "Moving Edge" is include by doing a logic AND operation between the > > subtracted image and the edge image(obtained by Sobel-mask)of the > > current frame. > > > > After finding out the "Moving Edge" we must to extract the object's > > shape > > by using Active Contour Model(or snake). > > > > Now I have implemented the "Moving Edge" detection function on > > a Xilinx FPGA.The next step is to design the "Snake-Based Outline > > Extraction" > > function block. I've found a lot of reference papers on the Google > > about the > > "active contour model" and finally I want to choose two methods--> One > > is Greedy algorithm based snake-model and the other one is Gradient > > Vector Flow (GVF)based algorithm. > > I wonder which one is more suitable for FPGA based architecture > > design? > > Could anyone can give me some recommendations or you have any other > > good ideas > > to design the object outline extraction function on FPGA..?? > > > > Thanks a lot!! > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 Yes .. The image size is 320x240 and in order to meet a nearly real-time constraint, each image frame (320x240) processing time must be less than 34 ms.Article: 68276
I remember those bucket brigade delay lines all too well. Just getting
them to work with a reasonable SNR was a feat in itself, because of the
offset currents, drifting bias etc. Been doing stuff with today's
"small" FPGAs that significantly outperforms in every respect stuff I
was doing in the '80s using a whole chassis full of boards. Ain't
progress wonderful?
Jonathan Bromley wrote:
> On Tue, 30 Mar 2004 16:43:17 -0500, Ray Andraka <ray@andraka.com>
> wrote:
>
> [...]
> >(signal processing was all analog before somewhere around 1960, and
> >predominantly analog all the way up to around 1980).
>
> Happy memories of building FIR filters with the Reticon TAD32
> tapped analog delay line, with its frightening mess of bizarre
> supply voltages and unpredictable output offset currents...
> I was doing that kind of stuff around 1982/83, because there
> was no other *cheap* way of doing a 10MHz FIR.
>
> And doing DSP on the digitised output of linear CCD cameras
> using an 8-bit microprocessor clocked at about 4MHz, to get
> sub-pixel interpolated edge positions.
>
> Things have moved on.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573 Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68277
Hi guys,
I am having a strange problem.
I have my schematic file, made up of lots of nice LUTs, gates, etc. My
inputs are represented by an I/O marker followed by either an IBUF,
OBUF, or BUFG for input, output and clock signals.
The synthetiser works perfectly.
The translator works perfectly.
The mapper gets rid of all my logic.
Here is the relevant section on the report:
Section 5 - Removed Logic
-------------------------
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "XLXN_421" is unused and has been removed.
Unused block "XLXN_421" (PAD) removed.
The signal "XLXN_422" is unused and has been removed.
Unused block "XLXN_422" (PAD) removed.
The signal "XLXN_423" is unused and has been removed.
Unused block "XLXN_423" (PAD) removed.
The signal "XLXN_424_IBUFG" is unused and has been removed.
Unused block "XLXN_424_IBUFG" (CKBUF) removed.
The signal "XLXN_424" is unused and has been removed.
Unused block "XLXN_424" (PAD) removed.
The signal "XLXN_427" is unused and has been removed.
Unused block "XLXN_427" (PAD) removed.
The signal "XLXN_402" is unused and has been removed.
Unused block "B2_2_FF" (FF) removed.
The signal "XLXN_408" is unused and has been removed.
Unused block "B2_1_FF" (FF) removed.
The signal "XLXN_416" is unused and has been removed.
Unused block "XLXI_53" (BUF) removed.
The signal "XLXN_419" is unused and has been removed.
Unused block "XLXI_61" (CKBUF) removed.
The signal "XLXN_353" is unused and has been removed.
Unused block "XLXI_60" (BUF) removed.
The signal "XLXN_361" is unused and has been removed.
Unused block "XLXI_55" (BUF) removed.
The signal "XLXN_357" is unused and has been removed.
Unused block "XLXI_54" (BUF) removed.
The signal "XLXN_371" is unused and has been removed.
Unused block "B1_1_FF" (FF) removed.
The signal "XLXN_377" is unused and has been removed.
Unused block "B1_2_FF" (FF) removed.
I know I should have named my instances!! :-P
Anyway, it all starts with my input pads being removed because they
are unused. Anyone got any idea what am I doing wrong?
Thanks!!
Article: 68278
OK, so webcam type stuff. These have a low pixel rate and image size compared to other
video. Bit serial arithmetic works great for this. I think the gradient vector flow
might be a little easier to do.
YunghaoCheng wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<406A644A.67629932@andraka.com>...
> > You didn't mention your image size or pixel rate. Those are a factor in
> > determining the best approach.
> >
> > YunghaoCheng wrote:
> >
> > > Hi folks!!
> > > Now ,I am designing a real-time visual tracking system based on FPGAs.
> > >
> > > The images are captured by the CCD camera, and we do edge detection
> > > by using (Sobel-mask) 2D convolver.
> > > We also use two consecutive image
> > > frames I(k) and I(k-1) to subtracted pixel by pixel ,in order to
> > > find out the moving object.
> > >
> > > A "Moving Edge" is include by doing a logic AND operation between the
> > > subtracted image and the edge image(obtained by Sobel-mask)of the
> > > current frame.
> > >
> > > After finding out the "Moving Edge" we must to extract the object's
> > > shape
> > > by using Active Contour Model(or snake).
> > >
> > > Now I have implemented the "Moving Edge" detection function on
> > > a Xilinx FPGA.The next step is to design the "Snake-Based Outline
> > > Extraction"
> > > function block. I've found a lot of reference papers on the Google
> > > about the
> > > "active contour model" and finally I want to choose two methods--> One
> > > is Greedy algorithm based snake-model and the other one is Gradient
> > > Vector Flow (GVF)based algorithm.
> > > I wonder which one is more suitable for FPGA based architecture
> > > design?
> > > Could anyone can give me some recommendations or you have any other
> > > good ideas
> > > to design the object outline extraction function on FPGA..??
> > >
> > > Thanks a lot!!
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> Yes ..
>
> The image size is 320x240 and in order to meet a nearly real-time constraint,
> each image frame (320x240) processing time must be less than 34 ms.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68279We are in desperate need of a half dozen XCF16 or XCF08 serial proms(48 pin package). Engineering samples are fine. Please email me direct with pricing info. Thanks.Article: 68280
Use one of those RS232 level translators and do it right. They are little more
than special inverters. Some have a charge pump built in so that they operate
off a 5v supply. Costs are pretty low. Check Maxim.
Martin T--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68281
That is correct. -6 is faster than a -4. A -6 will replace a -4 in all
cases, not true the other way around though. Best bet on using the -4 is
to recompile with the -4 as the target. The PAR tools since 4.1 have only
worked at place and route hard enough to meet the timing target. Even if
the design is capable of more, PAR calls it a day when it meets timing.
Martin Thompson wrote:
> Rene Tschaggelar <none@none.net> writes:
>
> <snip>
> > I'd assume a -4 can replace a -6 in all cases at all
> > temperatures.
> >
>
> Isn't that the other way around - a -6 will replace a -4 in all cases?
> -6s are faster than -4s aren't they?
>
> Cheers,
> Martin
>
> --
> martin.j.thompson@trw.com
> TRW Conekt, Solihull, UK
> http://www.trw.com/conekt
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68282Jonathan, That was very helpful, Thanks much ! -rajeev- ------------------- Jonathan Bromley <jonathan.bromley@doulos.com> wrote in message news:<n10l60pa39pdca836cre380k43op1hv4gq@4ax.com>... > On 30 Mar 2004 15:22:53 -0800, rrr@ieee.org (Rajeev) wrote: > > >Hello, > > > >I'm plugging away climbing the Altera DSP Builder > >learning curve. Right now I'm struggling with a > >problem that's beyond my level of VHDL knowhow -- > >I'd sure appreciate some tips. > > Probably better to post on comp.lang.vhdl, but I'll bite anyhow. <...>Article: 68283
MNQ wrote: > HI All > > I am desperately in search of some Xilinx CPLDs Part number > XC2C256-7TQFP144I. I need a quantity of 25. Can anyone suggest where I can > purchase them from. > > Thanks for any help. > > Naveed > > Just online order on http://www.nuhorizons.com They have 75 pces in stock ! Larry, www.amontec.com ------------ And now a word from our sponsor ---------------------- For a quality mail server, try SurgeMail, easy to install, fast, efficient and reliable. Run a million users on a standard PC running NT or Unix without running out of power, use the best! ---- See http://netwinsite.com/sponsor/sponsor_surgemail.htm ----Article: 68284
I am sorry I cannot help you with the Xapp134 SDRAM controller, but you might consider checking the new version of the SDRAM controller from XESS ( you can get it free from www.xess.com ). I haven't tried it myself, but it seems like a really neet and fast controller. It is also reasonably well documented, although not as good as the Xapp134 may I add. Best of luck with your project, George MercuryArticle: 68285
On Mon, 29 Mar 2004 12:55:15 -0800, Gary wrote: > I'm having a problem with a XC3S200 device, and Xilinx tech support has > been stumped to this point. The device is set up for hot-swap mode > (HWSAPEN=2.5V). > > I have a signal which is pulled low externally to the part. Everything > looks fine until about the last 3mS of the configuration when it appears > that the IO pullup resistor is connected to the pin. This signal is an > output that is then driven low upon the completion of configuration. I > just checked, and saw the same behavior on the XC3S50ES device that we > used on the previous version of our board only the pullup value seems to > be lower on those devices which is why it didn't cause problems for us > then. We are configuring at about 500KHz. > > Any ideas? > Thanks, > Gary Gary, I have just been in the throws of a similar problem - by any chance are you using slave parallel mode ? I found that at 212072 bytes into the load the pull-ups came on and stayed on, in addition to this the pull-ups were not so weak; I came up with a figure of 1.5K this caused our processor to go in a major huff. I've only just discovered this, so not had it confirmed by Xilinx, but it sounds pretty similar to your problem. I think if our processor had been able to load more data the pull-ups would have come back off but it was spinning away with the HOLD pin high :-(. I seem to have gotten around it by lowering the pull down on the HOLD pin but what a fright it gave me, and fortunately the processor can drive against these stronger pull-ups to complete the configuration. I'd be interested to know what value of pull-up resistor your chip has ? Cheers JohnArticle: 68286
Marija wrote: > Hi Jean, > > I know that the frequency > synthesis shows is only estimated. > The real problem is that I have > a .xcf file in which I have > defined clk freq constraint, and > after PAR everything looks OK. ISE > even reports that timing > constraints are met. Later, when I > run gate level simulation, using > frequency which is close to the > maximal, I do not get good > results. > > BR, > Marija > Something similar just happened to me, and I believe I have fixed it (I'm currently into the second day of error-free post-PAR timing simulation). First of all, are you simulating using the SDF back-annotations in your simulations? If so, your simulator should tell you exactly where (if) any timing errors are happening. In my case, when I first did the timing simulation, I was getting multiple violations on the input flip-flops to my module (I have combinational logic in between my inputs and the first synchronous elements) despite having met all timing constraints in PAR. The problem seems to have been that ISE assumed my signals were coming from pads instead of another synchronous module, and I assume this changed its timing analysis. By including the "wrapper" synchronous elements and logic in my synthesis (which were already in my simulation), ISE seems to have correctly routed to respect my timing. At the very least, Modelsim hasn't given me any timing violations (cross fingers, knock wood ;). Hope this helps, -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68287
Let me explain some basics: Metastability is not a digital phenomenon, it is analog. Metastable recovery time depends on the gain-bandwidth product of the feedback loop in the master latch ( in a flip-flop) Metastable outputs never settle to the "wrong" value, since either value is as good as the other (That's why it went metastable). The problem is not the final output value, the problem is the hesitance in arriving at it, and the non-deterministic timing of the output change. Metastability occurs in daily life: at a 4-way intersection, in any situation where conflicting inputs must be resolved and the arguments for both sides are perfectly balanced. "Take the right road or the left road" and while arguing about the advantages, you end up in the ditch.... Let Condelezza testify or not... Peter Alfke =========================== > From: Austin Lesea <austin@xilinx.com> > Organization: Xilinx,Inc > Newsgroups: comp.arch.fpga > Date: Wed, 31 Mar 2004 07:25:02 -0800 > Subject: Re: Metastablility > > Hal, > > I ran a whole series of spice simulations, and compared them to the > results from Peter's experiments. > > It is true that spice makes something that "looks" like metastability > happen, but different versions of spice give radically different > results, so I suspect that the simulator is not simulating the actual > metastable process, but is an artifact of the simulator itself. > > Austin > > Hal Murray wrote: >>> Is it possible to simulate Metastability? Not in the functional >>> simulation. But in Gate level Netlist simulation. >> >> >> What are you trying to do? >> >> I doubt if you can do anything interesting at the gate level >> if your gates are boxes with binary inputs/outputs and delays. >> >> Metastability is rare enough that you can't usefully simulate >> it in a statistical sense. You might adjust the starting >> conditions to tickle the timing window. >> >> You can do interesting simulations at the transistor level with Spice. >> That might help you estimate or understand recovery times and >> things like that. >>Article: 68288
Muthu wrote: > Hi, > > Is it possible to simulate Metastability? Not in the functional > simulation. But in Gate level Netlist simulation. > > Regards, > Muthu Yes, it is possible, at least in a way. If the simulator detects a setup or hold time violation of an FF, then the output of your simulation model may be 'X' until the next clock (if the signal is stable then). If you switch off the "x-propagtion" of your simulator, everything is as expected. BR, ChrisArticle: 68289
99.9% of all set-up time violation do NOT result in metastability. The flip-flop output is just either a 1 or a 0, but the propagation delay is normal. If the set-up time violation hits the bull's eye (femtoseconds wide), then you get these strange and unpredictable metastable delays. If you treat every set-up time violation as metastability, you are overly cautious. If you want to, that's your choice. When you change the D input inside the set-up time window you play Russian Roulette, but with very few bullets in the chamber... Peter Alfke > From: Chris <cgs-news56@cg983schneider.com> > Organization: 1&1 Internet AG > Newsgroups: comp.arch.fpga > Date: Wed, 31 Mar 2004 20:37:53 +0200 > Subject: Re: Metastablility > > Muthu wrote: >> Hi, >> >> Is it possible to simulate Metastability? Not in the functional >> simulation. But in Gate level Netlist simulation. >> >> Regards, >> Muthu > > Yes, it is possible, at least in a way. If the simulator detects a setup > or hold time violation of an FF, then the output of your simulation > model may be 'X' until the next clock (if the signal is stable then). If > you switch off the "x-propagtion" of your simulator, everything is as > expected. > > BR, ChrisArticle: 68290
Peter Alfke wrote: > 99.9% of all set-up time violation do NOT result in metastability. The > flip-flop output is just either a 1 or a 0, but the propagation delay is > normal. > If the set-up time violation hits the bull's eye (femtoseconds wide), then > you get these strange and unpredictable metastable delays. > > If you treat every set-up time violation as metastability, you are overly > cautious. If you want to, that's your choice. When you change the D input > inside the set-up time window you play Russian Roulette, but with very few > bullets in the chamber... > Peter Alfke That's right. I know that. I agree that my sugguested simulation is not very near to reality. But if you just want to see if a design is able to handle the additional delay it is pretty useful. BR, ChrisArticle: 68291
Whats a normal execution time for a testbench? Is simulation the only verificationmethod used for fpga designs or do people use function test too? GlennArticle: 68292
Hello, I know Pinpoint Solutions has expertise in video processing IP for ASICs and FPGAs. You could E-mail them to see if they have what you need. http://www.asic-design.com/ Bob Synplicity FAE - Colorado. coreDEVIL wrote: > I need sync separator IP which works like Gennum GS4982. > > Can I get any information about that? > > Or is there any web site that introduces existing IPs? > > > > Thank you for your answer. >Article: 68293
Just an small extra to Brian's post, there a Xilinx app 'SPEEDPRINT'. You can run it from a command prompt and tell it temperature and supply voltage to get new sets of timing info. So, why not use the on-die temperature diode (DXN/DXP) to servo your design's clocking frequency on the fly? I reckon you could do it using a temperature chip, a BUFGMUX and a couple of DCMs? ;-) good luck, Syms.Article: 68294
Rudolf Usselmann <russelmann@hotmail.com> wrote in message news:<c4bnh2$6br$1@nobel.pacific.net.sg>... > Rudolf Usselmann wrote: > > > > So I have a design that uses two clocks. Neither one is > > available on my development PCB. Lets throw in some numbers > > to make it a bit simpler: I need 60 and 75 MHz, my development > > board only has a 100MHz oscillator. > > > > Hmm, sounds like a simple problem to solve. Pull up Arch. > > Gen., configure two DCMs, one fo 60 the other for 75 MHz. > > edit the files to pull out the IBUFG to serve both of the > > DCMs, done, right ?! wrong ! > > > > Now the fight with the tools begins. First Synplify, had to > > learn I had to put the clock in to separate groups so it > > will constrain them independently. So far so good. > > > > No I want for ISE to treat them separate as well. But it > > just refuses. It will accept the input clock as 100MHz, > > and one of the other once (either 60 or 75) as an independent > > clock, but the other one it will make dependent on the input > > clock, and come up with cycle times of 22++ nS. > > > > Now I did do a trial synthesis and P&R without the DCMs > > and know that theoretically there should be no problems > > whatsoever to meet the required timing. But ISE starts of > > the timing report with some 10 ns as the first entry: > > Slack: -9.417ns (requirement - (data path - clock path > > skew + uncertainty)) > > > > How do I tell ISE to treat ALL clocks separate, even though > > some of them are used in the same module ? > > > > Thanks, > > rudi > > > I'm following up to my own message, I made some additional > discoveries: > > 1) It appears the architecture wizard is instantiating > BUFGs and IBUFG. Both of them are modeled as a simple > buffer, with out the "synthesis black box" directive, > which makes the syntheis took remove them. Adding "synthesis > black_box" to both modules in the xilinx libraries, leaves > them. > > 2) If I use different clock inputs for both DCMs all my > problems seem to go away. How can I use a single clock > input for both DCMs ??? Rudi, The Architecture Wizard should generate a component with a CLKIN_IBUFG_OUT output port (if the 100 MHz clock is coming from a pad). Send that signal from the dcm60 into the CLKIN_IN port of the dcm75. Also, for your dcm75, in the Architecture Wizard, specify that the clk is coming from an internal source. This will prevent an IBUFG from being inserted in the dcm75 file. This worked for me. Code snippet below: Inst_dcm60: dcm60 PORT MAP( CLKIN_IN => clk100, LOCKED_OUT => open, CLKFX_OUT => clk60, CLKIN_IBUFG_OUT => clk100_ibufg_out, CLK0_OUT => open ); Inst_dcm75: dcm75 PORT MAP( CLKIN_IN => clk100_ibufg_out, LOCKED_OUT => open, CLKFX_OUT => clk75, CLK0_OUT => open ); If you need the rest of the code, I can send it to you. Regards, BenArticle: 68295
Ray Andraka <ray@andraka.com> writes: > Use one of those RS232 level translators and do it right. They are > little more than special inverters. Some have a charge pump built in > so that they operate off a 5v supply. Costs are pretty low. Check > Maxim. TI makes direct replacements for most of the common Maxim EIA-232 level translators at substantially lower prices. Digikey stocks both the Maxim and TI parts.Article: 68296
Hi, I am trying to create a large bus(32 bits wide), with many slaves recieving and sending data. Should I look for tristates on my V2pro or giant MUX or any other suggestion anyone has? Thanks MattArticle: 68297
muthusnv@yahoo.co.in (Muthu) wrote in message news:<4f8e807b.0403302302.5ded8632@posting.google.com>... > Hi, > > Is it possible to simulate Metastability? Not in the functional > simulation. But in Gate level Netlist simulation. > > Regards, > Muthu Many decades ago, an elder EE would recant his lab story to show the youngens about metastability (who of course didna believe such fairy tales). He had a bench setup with an old 4000 series FF (I mean RCA 70's cosmos family). The latch would be driven by a D/A converter to some middle value and let go, see how long it would take to settle one way or the other. Point was to get it automatically to stay indeterminite for the longest possible time. Can't remember how long that was, probably in ms range (maybe even secs) but it definitely showed a FF being less than perfect. At the time we were working with NMOS so alot of idiot type circuit design was floating around (multiple Vt drops, neg bootstrapping etc) that would have produced pretty nasty chips had not CMOS come along. If you want to do that experiment today, you could work on a DRAM controller and pull the refresh cycle out till the data is not quite sensed right. Its the same deal inside, a perfectly balanced latch with din (decaying) and 1/2 din ref on other side. regards johnjakson_usa_comArticle: 68298
I reported this to my local FAE last Friday. He confirmed the problem and opened a Webcase. Apparently the code in XAPP134 was written "a long time ago" for Synplicity (?) and never updated. The current version of Synplicity will not synthesize the code either. No word on when it might get fixed, if ever. Steven wrote: > Hi, Newsgrouper, > > I began to implement a SDRAM controller a few weeks ago. Of course I > started with Xilinx Xapp134 sample code. > > Now I have problem to get the code synthesized. Xilinx ISE XST returns > following error messages: > > *Synthesizing Unit <sdrm>. > *Related source file is > H:/proj/XilinxRef/xapp134/XinlinxDemo/sdrm.vhd. > > *FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This > application has discovered an exceptional condition from which it > cannot recover. Process will terminate. To resolve this error, > please consult the Answers Database and other online resources at > http://support.xilinx.com. If you need further assistance, please open > a Webcase by clicking on the "WebCase" link at > http://support.xilinx.com > > *ERROR: XST failed > *Process "Synthesize" did not complete. > > I have no problem to get Verilog code running, but I am in Germany, I > have to use VHDL. :) > > Any one has experience with this :) > > Thanks > > StevenArticle: 68299
Hi, I was poking around in FPGA Editor, and I found a switch I hadn't noticed before. There's an Virtex2Pro-specific option to disable the PowerPC cores and "recover" the FPGA fabric that they overlay. Yay! No more PPC cores getting in the way of my floorplan and RPMs. Question: is there a command line option (on Map or PAR) for this so that I don't have to use FPGA Editor? Cheers, Allan.
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