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"sg" <sunil.k.gupta@intel.com> wrote in message news:<c4tc2u$blc$1@news01.intel.com>... > Hi All - > > I am trying to use bi-directional I/O pin in VHDL (inout). When I run it > through the Xilinx ISE, in the Pad report it converts the inout pin as > output. Is there any sample example/code which I can try to make sure I am > not writing something incorrect. Thanks. > > - Sunil Are you sure you use the pin for internal logic ?Article: 68576
On Thu, 8 Apr 2004 06:52:13 -0700, khamkar77 <khamkar77@yahoo.co.in> wrote: > Kindly post in plain text in future. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68577
Hi, there: I saw some boards with a EPM7128SLC84...which I found can only implement a simple 8-bit multiplier... For example, http://www.fpga.com.cn/solution/jx002b.htm ... Is there any market for such tiny FPGA chips? What are they? KelvinArticle: 68578
Thanks for all the answers given. Following the advices, I am now also looking into Xess's controller. The sample codes works under ISE 5.1, so it may be a compatible problem. Thank you all ! Steven. nachikap@yahoo.com (Nachiket Kapre) wrote in message news:<eadce17c.0404040032.6ad528e5@posting.google.com>... > Brian Philofsky <brian.philofsky@no_xilinx_spam.com> wrote in message news:<c4l1sh$dt65@xco-news.xilinx.com>... > > > > I wouldn't call XAPP 134 stupid but I would call it a rather simple > > implementation of a SDRAM controller which does make it easier to use > > and understand (one of the purposes of a reference design). > > my apologies. the idea that i wanted to convey was that the controller > was too simplistic in its assumption that row activations are > necessary for every row access. when you look at altera's sdram > controller core, "activation" as a separate command suddenly makes the > xilinx controller look foolish. its probably not that hard for even a > novice to figure out that "activations" shouldn't piggyback each > read/write commands. of course the novice now has to start remembering > which rows did he keep active in which banks...etc. but, you take a > look at the xess code to see how to keep the interface simple .. only > read/write and yet automate a lot of the sdram operations internally, > yet intelligently. so the bottomline is xilinx should really try and > tweak the code to allow easy extensibility of their vhdl. > > > That > > application note has been out for some time now and maybe 4 or 5 years > > ago, I made the modifications to that code for a project I was working > > on to allow for open page accesses of the SDRAM and while it does > > improve throughput for sequential, non-burst reads/writes it was not as > > trivial to modify as you suggest and does make timing somewhat harder to > > meet for faster implementations. You do need to store last access > > address as you suggest but I also had to build a fast comparator (at the > > time, I had to build it structurally), make several modifications (more > > complex state transition logic) to the state-machine, I had to keep > > track of whether a refresh was issued since the last read/write to the > > RAM, I had to dynamically modify the data buffering in the SRLs to > > adjust to the proper wait states depending on whether a precharge is > > needed or not, as well as a few other details that probably escape me > > right now. The data paths did get longer with my implementation of open > > page accesses so timing was harder to hit but I did meet my targets > > after some coaxing with the code. > > i was almost tempted to modify the code myself. but then i stumbled > across the xess controller which i guess probably wan't available 4-5 > years ago. and i think i am reasonably happy with it. > > > > > Any ways, the great thing about a reference design with open code like > > this is if you do not like what you see, modify it to what works best > > for you. For applications that make somewhat random access to the > > memory, or where latency is not the utmost concern, I found that > > controller to work very well but of coarse every design has its own > > requirements and one generic implementation will not fit all of them. > > true. but, i am skeptical about how easy the xilix code is to allow > modification. again when you look at xess' code it is far better > commented and the signals/state encoding makes more sense than the > xilinx coding style in xapp134. and i agree with your concern for > meeting timing and there might be some tricks required to get it > working. > > nachiket.Article: 68579
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.GSO.4.58-035.0404080202540.6639@unix3.andrew.cmu.edu... > When trying to create a mux with a case statement XST requires the output > be a reg. Why is this and would making it a reg(latch) make the mux > slower? > > Matt When trying to create a mux with a case statement VERILOG requires the use of reg elements. These do not have to end up as registers and will not slow the design. Assemble the case statement inside an always block with all the inputs in the sensitivity list. The resulting "reg" values assigned in the case statement are effectively wires. - John_HArticle: 68580
If you want reasonable speed, then use 470 Ohm (10 mA @ 5V) or even at 3.3 V. Higher resistors give long risetime. If that is acceptable, you can use something like 5.6 k. Peter Alfke > From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> > Newsgroups: comp.arch.fpga > Date: Thu, 8 Apr 2004 16:03:15 +0300 > Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND > > I think, yes. You'll pull the line up by resistor (several kilos?). CPLD > will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0 > otherwise. The same can be applied to pull-down resistor and '1', 'Z' > drivers. Line will be zero when nothing drives it. If CPLD outputs support > 'Z' state then I see no problem. > > > "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message > news:40748144$0$15193$a729d347@news.telepac.pt... >> Thanks for the help valentin. >> >> I want to use the Xilinx XC9536. >> If I use a pull-down resitor, I can do a Wired-OR with several pins, > right? >> >> Bruno >> >> >> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na >> mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de... >>> >>> The one I can think of: >>> >>> if OR_REDUCE(drivers) = '1' then >>> w <= DRIVE(1) >>> else >>> w <= DRIVE(0); >>> >>> >>> >>> >>> Externally, you would pull-up a line by resistor to Vcc and implement >>> transistor internally in FPGA: >>> >>> O <= '0' when A = '0' else 'Z'; >>> >>> cheers. >>> >>> >> >> > >Article: 68581
I meant to write: ... or even 330 Ohm at 3.3 V... Peter =========== > From: Peter Alfke <peter@xilinx.com> > Organization: Xilinx,Inc > Newsgroups: comp.arch.fpga > Date: Thu, 08 Apr 2004 08:34:20 -0700 > Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND > > If you want reasonable speed, then use 470 Ohm (10 mA @ 5V) or even at 3.3 > V. Higher resistors give long risetime. If that is acceptable, you can use > something like 5.6 k. > Peter Alfke > >> From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> >> Newsgroups: comp.arch.fpga >> Date: Thu, 8 Apr 2004 16:03:15 +0300 >> Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND >> >> I think, yes. You'll pull the line up by resistor (several kilos?). CPLD >> will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0 >> otherwise. The same can be applied to pull-down resistor and '1', 'Z' >> drivers. Line will be zero when nothing drives it. If CPLD outputs support >> 'Z' state then I see no problem. >> >> >> "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message >> news:40748144$0$15193$a729d347@news.telepac.pt... >>> Thanks for the help valentin. >>> >>> I want to use the Xilinx XC9536. >>> If I use a pull-down resitor, I can do a Wired-OR with several pins, >> right? >>> >>> Bruno >>> >>> >>> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na >>> mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de... >>>> >>>> The one I can think of: >>>> >>>> if OR_REDUCE(drivers) = '1' then >>>> w <= DRIVE(1) >>>> else >>>> w <= DRIVE(0); >>>> >>>> >>>> >>>> >>>> Externally, you would pull-up a line by resistor to Vcc and implement >>>> transistor internally in FPGA: >>>> >>>> O <= '0' when A = '0' else 'Z'; >>>> >>>> cheers. >>>> >>>> >>> >>> >> >> >Article: 68582
Hi - On Thu, 8 Apr 2004 02:05:30 -0400 (EDT), Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote: >When trying to create a mux with a case statement XST requires the output >be a reg. Why is this and would making it a reg(latch) make the mux >slower? Declaring something "reg" does *not* necessarily mean that it will be syntheized or simulated as a register or latch. The 1364-2001 spec says: "Assignments to a reg are made by procedural assignments (see 6.2 and 9.2). Since the reg holds a value between assignments, it can be used to model hardware registers. Edge-sensitive (i.e., flip-flops) and level sensitive (i.e., RS and transparent latches) storage elements can be modeled. A reg needs not represent a hardware storage element since it can also be used to represent combinatorial logic." Instead of "reg," think "sticky." (But type "reg"!) Bob Perlman Cambrian Design Works >Matt > >On Thu, 8 Apr 2004, rickman wrote: > >> john jakson wrote: >> > >> > "John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>... >> > > Usually your best chance of getting it is with a CASE statement. No >> > > guarantees though as synthesisers are notoriously unpredictable. >> > > >> > > You can also try structuring your VHDL to suggest a element layout. >> > > >> > > Instantiating macros in your HDL will give you a more exact structure. >> > > >> > > -- >> > > John Adair >> > > Enterpoint Ltd. >> > > http://www.enterpoint.co.uk >> > > >> > > This message is the personal opinion of the sender and not that necessarily >> > > that of Enterpoint Ltd.. Readers should make their own evaluation of the >> > > facts. No responsibility for error or inaccuracy is accepted. >> > > >> > > >> > > "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message >> > > news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu... >> > > > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using >> > > > several 2:1 muxs'. >> > > > Is there a suggested coding style to get xst to infer the larger muxes or >> > > > how would i hardcode them to make larger muxes? >> > > > >> > > > Thanks >> > > > >> > > > Matt >> > >> > look in the XST templates. >> > >> > In Verilog >> > >> > x <= >> > (sel==0)? a0 : >> > (sel==1)? a1 : >> > (sel==2)? a2 : >> > (sel==3)? a3 : >> > an >> > >> > and so on works for me. I've gone to 8 no problem. But occasional use >> > of hardcoding a MUXxyz can help to build the top stage if you need to >> > combine say a 2->1 with an earlier 4->1 and so on. There are quite a >> > few app nots in the xapp dir. >> >> >> I have not tried coding this in XST, but I am pretty sure it does not >> result in an 8:1 mux. The syntax you show is a priority selector. That >> means that it indicates an order of precedence. Even though it makes no >> difference since the selectors in each case are mutually exclusive, it >> is unlikely that this will be optimized to a proper mux. >> >> The recommended coding style would be a case statement, which by >> definition has mutually exclusive selections of a single control >> variable. >> >> A better coding method for bus muxes would be to pre-decode the >> selectors so that each of the 8 mux inputs has a separate enable. Then >> an 8 input mux can be done in just two levels of LUTs. The first level >> can encode the AND gates and one OR gate for combining two inputs. The >> second level is an four input OR gate for the final output. >> >> -- >> >> Rick "rickman" Collins >> >> rick.collins@XYarius.com >> Ignore the reply address. To email me use the above address with the XY >> removed. >> >> Arius - A Signal Processing Solutions Company >> Specializing in DSP and FPGA design URL http://www.arius.com >> 4 King Ave 301-682-7772 Voice >> Frederick, MD 21701-3110 301-682-7666 FAX >>Article: 68583
"Kelvin" <kelvin8157@hotmail.com> wrote in message news:<c53nnm$nf0$1@reader01.singnet.com.sg>... > I saw some boards with a EPM7128SLC84...which I found can only implement a > simple 8-bit multiplier... > For example, http://www.fpga.com.cn/solution/jx002b.htm ... > > Is there any market for such tiny FPGA chips? What are they? The salient feature in non-volatility not capacity. Some logic has to work immediately at powerup. Maybe some glue to boot a cpu or to control the loading of fpgas. -- Mike TreselerArticle: 68584
Thanks for the replies Amit and Yang. I solved the problem myself though - it was in my VHDL code. I wasn't taking into account that bit 30 and 31 of Bus2IP_Addr were being dropped. Now it is working as expected. Thanks, JoeArticle: 68585
"Kelvin" <kelvin8157@hotmail.com> wrote in message news:<c53nnm$nf0$1@reader01.singnet.com.sg>... > Hi, there: > > I saw some boards with a EPM7128SLC84...which I found can only implement a > simple 8-bit multiplier... > For example, http://www.fpga.com.cn/solution/jx002b.htm ... > > Is there any market for such tiny FPGA chips? What are they? Well, #1 is that it's a CPLD. #2 is that a 128-macrocell CPLD was certainly sufficient for me to use as the controller for a audio digital delay. I2S in, I2S out, SRAM controller, digital input level meter, the works. Not every design needs that multi-million-gate thousand-ball thousand-dollar FPGA, ya know. Betcha that brands A, L and X sell more of the small/midsize CPLDs than they do of the super-big/super-fast devices. -a-Article: 68586
Ray, OK, I'll grant that in special cases there are other possible structures. #2 sounds a little weird, like self-modifying code. Don't forget #5: one can set the contents of a blockRAM so that the address lines can be used for mux control and data. -Kevin "Ray Andraka" <ray@andraka.com> wrote in message news:40749F09.28C2F9E9@andraka.com... > Well, there are a few ways I can think of: > > 1) Use TBUFs to wire-OR LUT outputs together > 2) Use the OR cascade in virtexII in the same way, preferable because it is > faster and more plentiful > 3) If you can accept a 16 clock set-up time, you can use the SRL16 as a > programmable LUT. The programmer uses 2.5 slices, and loads up the SRL16 (or a > word wide bank of them) with the appropriate pattern to connect the selected > input to the output ( patterns are for a mux with enable are > X"0000",X"AAAA",X"CCCC",X"F0F0",X"FF00"). This is useful for minimum > propagation time 4:1 muxes for applications where the selection is relatively > static, or is otherwise allowed time to complete. Yes, I have used it. > 4) if your sources to the mux have available terms or come from flip-flops, you > can substitute a 4 input OR for each MUX bit by having your select logic gate > off all but one of the inputs at any given time. If the inputs are from > flip-flops, you can use the sync reset on the flip-flops for the gate function > without having to add logic in front of the flip-flop other than the decoder on > the reset. > > > > > Kevin Neilson wrote: > > > "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message > > news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu... > > > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using > > > several 2:1 muxs'. > > > Is there a suggested coding style to get xst to infer the larger muxes or > > > how would i hardcode them to make larger muxes? > > > > > > Thanks > > > > > > Matt > > > > I don't understand how you would make a 4:1 mux in a Xilinx without making > > it out of smaller muxes. The LUTs only have 4 inputs, so you can't make a > > 4:1 mux out of a single LUT. You need two LUTs plus another F5 mux. > > -Kevin > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 68587
I agreed. I was in Altera web seminar. I asked "Stratix is only comparable to Virtex-II, not -Pro" and did not get answer. I do not have comments on the performance comparison materials. But my designs required 190 16x16 multipiliers in each of three FPGAs in a row. Stratix had no way to do it. Stratix-II, too later. I really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70% over 4.x ..... were jokes. I was seeing -1000% 6.2 over 6.1. -qlyus Austin Lesea <austin@xilinx.com> wrote in message news:<c51n66$d5r1@cliff.xsj.xilinx.com>... > Sander, > > I apologize if I have offended. Just wanted to be sure to balance the > scales. > > AustinArticle: 68588
Austin Lesea <austin@xilinx.com> wrote: > Sander, > > I apologize if I have offended. Just wanted to be sure to balance the > scales. no offence, I just think pure marketing - and even more so aggressive marketing asking people to question various things doesn't IMHO really belong here. This isn't to pick on Xilinx or you. > > Austin > -- Sander +++ Out of cheese error +++Article: 68589
Sander, Thanks, I just can't stand it when others post "PM" so I feel obligated to balance it out. I do try to place some really useful and practical bits in the post, however. Austin Sander Vesik wrote: > Austin Lesea <austin@xilinx.com> wrote: > >>Sander, >> >>I apologize if I have offended. Just wanted to be sure to balance the >>scales. > > > no offence, I just think pure marketing - and even more so aggressive > marketing asking people to question various things doesn't IMHO really > belong here. This isn't to pick on Xilinx or you. > > >>Austin >> > >Article: 68590
qlyus, If you get such a degraded performance result, you should open a case. That is an indication that something is not right. Either your style is using the wrong features, or the software is. We certainly like to know. Any individual design can easily vary 2:1 in performance on either toolset, so just as one error does not define a rate, one result does not define performance. Just curious, what do you use 190 multipliers for, and what is the market for that? Austin qlyus wrote: > I agreed. I was in Altera web seminar. I asked "Stratix is only > comparable to Virtex-II, not -Pro" and did not get answer. > > I do not have comments on the performance comparison materials. But > my designs required 190 16x16 multipiliers in each of three FPGAs in a > row. Stratix had no way to do it. Stratix-II, too later. > > I really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70% > over 4.x ..... were jokes. I was seeing -1000% 6.2 over 6.1. > > -qlyus > > > Austin Lesea <austin@xilinx.com> wrote in message news:<c51n66$d5r1@cliff.xsj.xilinx.com>... > >>Sander, >> >>I apologize if I have offended. Just wanted to be sure to balance the >>scales. >> >>AustinArticle: 68591
Hi,
My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456
The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis tool.
The Drop down menu had only one option "None".
I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.
1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages
ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.
ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.
The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp".
I guess the last _xst is for XST specific. Do I just rename the file? or
how do I move ahead with the tutorial using Synplicity for my synthesis.
Any clues on how to proceed would be appreciated.
Thanks
brijesh
Article: 68592Was going through the Documentation. Buried deep within I found this "Currently, Platform Generator only supports XST (Xilinx Synthesis Technology)." Guess Iam stuck. Unless there is a tutorial that does not use the Platform Generator. Is there a way to change the Synthesis tool option once the project is generated using the Platform Generator. Or more basic question does EDK support Synplicity at all? Thanks brijesh Brijesh wrote: > Hi, > > My set up is > EDK 6.1 > ISE 6.1 (no XST) > Synplicity > Memic VitexII Pro Dev board P4 FG 456 > > The tutorial expects you to use Xilinx synthesis tool XST. During > initial XPS wizard didnt give me an option to choose the synthesis tool. > The Drop down menu had only one option "None". > > I went ahead with the steps and managed to export the project to ISE > project Navigator. Had to manually add the system.vhd and other files. > Then I had the following problems. > > 1) The bus format in the UCF files had to be changed from <> to (). > 2) Got stuck with this error messages > > ERROR:NgdBuild:704 - The BRAM instance > 'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0' > could not be found in the netlist. Please verify the instance name in > the BMM file and the netlist. > > ERROR:NgdBuild:604 - logical block 'system_dcm' with type > 'system_dcm_wrapper' could not be resolved. A pin name misspelling can > cause this, a missing edif or ngc file, or the misspelling of a type > name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'. > > The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp". > I guess the last _xst is for XST specific. Do I just rename the file? or > how do I move ahead with the tutorial using Synplicity for my synthesis. > > Any clues on how to proceed would be appreciated. > Thanks > brijeshArticle: 68593
Is the 50 mhz EP1C3T100C7 Cyclone have enough resources (LE) to synthesize the nios? For example, this board doesnt have any memory, what kind of limits will that put on the nios processor?Article: 68594
> Is the 50 mhz EP1C3T100C7 Cyclone have enough resources (LE) to synthesize > the nios? For example, this board doesnt have any memory, what kind of > limits will that put on the nios processor? You will probably not have very much fun without external memory. (AD!) A nice and affordable board with Cyclone 1C6 and 1MB fast 32-bit memory: http://www.jopdesign.com/cyclone/index.jsp A ready configured version of NIOS for this board can be found at: http://www.jopdesign.com/nios.jsp MartinArticle: 68595
Kevin, I presume you meant to say #3, not #2 'sounds a little weird. #2 is very
straight forward, and not much different than #1 or #4. #3 is more like a poor
man's reconfiguration of only the LUTs involved. I suppose you can call it self
modifying, but it only modifies specific LUTs with one of 5 specific sets of
bits. The fact is, it gets you a 4:1 mux in one level of LUTs, and it is
spacewise efficient for word-wide data paths.
Kevin Neilson wrote:
> Ray,
> OK, I'll grant that in special cases there are other possible structures.
> #2 sounds a little weird, like self-modifying code. Don't forget #5: one
> can set the contents of a blockRAM so that the address lines can be used for
> mux control and data.
> -Kevin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:40749F09.28C2F9E9@andraka.com...
> > Well, there are a few ways I can think of:
> >
> > 1) Use TBUFs to wire-OR LUT outputs together
> > 2) Use the OR cascade in virtexII in the same way, preferable because it
> is
> > faster and more plentiful
> > 3) If you can accept a 16 clock set-up time, you can use the SRL16 as a
> > programmable LUT. The programmer uses 2.5 slices, and loads up the SRL16
> (or a
> > word wide bank of them) with the appropriate pattern to connect the
> selected
> > input to the output ( patterns are for a mux with enable are
> > X"0000",X"AAAA",X"CCCC",X"F0F0",X"FF00"). This is useful for minimum
> > propagation time 4:1 muxes for applications where the selection is
> relatively
> > static, or is otherwise allowed time to complete. Yes, I have used it.
> > 4) if your sources to the mux have available terms or come from
> flip-flops, you
> > can substitute a 4 input OR for each MUX bit by having your select logic
> gate
> > off all but one of the inputs at any given time. If the inputs are from
> > flip-flops, you can use the sync reset on the flip-flops for the gate
> function
> > without having to add logic in front of the flip-flop other than the
> decoder on
> > the reset.
> >
> >--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68596
I sometimes see small gains for 6.2 if the design has one clock domain. For designs with
multiple clock domains however, I have been having considerable difficulty meeting timing on all
the clock domains on designs that met timing without trouble under 5.2, even with the effort
level cranked up on 6.2. Apparently, the software is now focusing on what it figures to be the
clock domain with the tightest timing and failing the others as a result. Time to compile means
nothing if the result is garbage.
qlyus wrote:
> II really think Xilinx's claims ISE 6.2 40% over 6.1 50% over 5.2 70%
> over 4.x ..... were jokes. I was seeing -1000% 6.2 over 6.1.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68597I'm planning an FPGA design that will use the wb_pci core at Opencores, but I've been unable to subscribe to the list there. Does anybody know if their mailer/list manager is broken or somesuch? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 68598
rickman wrote > john jakson wrote: snipping > > > > look in the XST templates. > > > > In Verilog > > > > x <= > > (sel==0)? a0 : > > (sel==1)? a1 : > > (sel==2)? a2 : > > (sel==3)? a3 : > > an > > > > and so on works for me. I've gone to 8 no problem. But occasional use > > of hardcoding a MUXxyz can help to build the top stage if you need to > > combine say a 2->1 with an earlier 4->1 and so on. There are quite a > > few app nots in the xapp dir. > > > I have not tried coding this in XST, but I am pretty sure it does not > result in an 8:1 mux. The syntax you show is a priority selector. That > means that it indicates an order of precedence. Even though it makes no > difference since the selectors in each case are mutually exclusive, it > is unlikely that this will be optimized to a proper mux. > I did miss 1 detail, I use the form in both cont = assignments and the always <= form but only if the output isn't needed elsewhere before the DFF. Technically it is a priority encoding, but since the sel values are unique, the result is always a mux. In the report and layout I see all the muxes I expect to see except when the inputs are coded as constants in which case the mux is smaller. I have actually used alot of 4->1s which is a pair of LUTs locked. The 8->1 mux (actually 7->1 with the extra 0) used for status flag selection uses a pair of 4->1 with the extra MUXFx as it says in the appnotes. The hidden MUXF567 supposedely are much faster than extra LUT 2->1 so an 8->1 is really 4 2->1 LUTs with 3 more MUXF cells so delay may be much faster than binary treee of LUTs. At least all the reports and docs leads me to believe this. I am actually quite impressed with XST so far, I have't really had to instance any primitives except the Blockram to get true dualport R & W. > The recommended coding style would be a case statement, which by > definition has mutually exclusive selections of a single control > variable. > > A better coding method for bus muxes would be to pre-decode the > selectors so that each of the 8 mux inputs has a separate enable. Then > an 8 input mux can be done in just two levels of LUTs. The first level > can encode the AND gates and one OR gate for combining two inputs. The > second level is an four input OR gate for the final output. > Thanks for reminding me of And/Or, there may be occasions where I just might need that trick. So far I have used MUXF5,6s for some sneek paths, then rewrote the whole module to do better job without. regards johnjakson_usa_comArticle: 68599
Anyone out there using the PLB RapidIO LVDS core in the Xilinx EDK? If so, have you been able to transmit a packet (NREAD) successfully? I've been able to successfully complete training mode and the Error and Status CDR shows the "Port OK" but sending an NREAD packet results in the CSR indicating "Output Error - Encountered". Any help would be appreciated. Thanks, Kevin
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