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Another thought: If you're instantiating the MUXCY primitives, you may need to add an XORCY between the MUXCY and the register. Take a look at the slice configuration - the Virtex functional data sheet illustration is more detailed than that found in the Spartan-II's - and you'll see that the MUXCY output from one "stage" of your carry chain feeds the XORCY of the register one half slice above. Also, rather than instantiating 12 MUXCY and XORCY primitives, try using the 13-bit result from 13'h1fff+In where you may need to add some directives to keep a smart synthesizer from reducing your equation to an equivalent 1-bit result. Use the top 12 of the 13 bits for your "deterministic" delay and you're there. It may be cleaner and easier to implement in the end. "A Beaujean" <abeaujean@gillam-fei.be> wrote in message news:8211d046.0404060730.5e01e294@posting.google.com... > I want to be able to use the fastest possible paths within a SpartanII > FPGA to create internal signals which are simple copies of each other > linked in a chain. Delay between each should be in the order of a few > tens to hundreds of picoseconds. > All of the created signals should however be usable by other internal > logic (in fact on D inputs of a chain of flip-flops clocked all the > same) > My first idea was to define a chain of BUF "components", and see what > happens. > As feared, the (Foundation) development tool just merged all the > signals (No BUF generated). > Forcing a KEEP attribute on all the signals just did not help. > I tried with LUT1's. This works but is much too slow for the > application. > Looking at the FPGA Editor gave me the idea of using the MUXCY, > MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a > miracle happened then: the dedicated carry chain was selected, running > thru the expected number of CLB's, and speed was excellent. But to my > great surprise, only one flip-flop out of two hooked onto the outputs > of the MUXCY components was selected as being part of the same cell. > The second FF was placed in a totally different CLB. This is not > exactly what I expected, since the application requires a very close > matching of delays. > Any idea why this happens ? Possible corrections ? Thank you > beforehand.Article: 68501
Hi Sander, Your teacher's picked a good project! Try Googling for vga.pdf from xess.com. (Search for 'vga.pdf', it's the first Google result.) That helps you wire it up. Then this might help you with frequencies... TABLE 1 VGA CORE VIDEO MODES IBM Standard Modes Mode Type Display Alpha. Res. Colors Vert. Horz. Pix Clk 0, 1 A/N 40 x 25 8 x 8 320 x 200 16 70 Hz 31.778 kHz 25.175 MHz 2, 3 A/N 80 x 25 8 x 8 640 x 200 16 70 Hz 31.778 kHz 25.175 MHz 0*, 1* A/N 40 x 25 8 x 14 320 x 350 16 70 Hz 31.778 kHz 25.175 MHz 2*, 3* A/N 80 x 25 8 x 14 640 x 350 16 70 Hz 31.778 kHz 25.175 MHz 0+, 1+ A/N 40 x 25 9 x 16 360 x 400 16 70 Hz 31.778 kHz 28.322 MHz 2+, 3+ A/N 80 x 25 9 x 16 720 x 400 16 70 Hz 31.778 kHz 28.322 MHz 4, 5 APA - - 320 x 200 4 70 Hz 31.778 kHz 25.175 MHz 6 APA - - 640 x 200 2 70 Hz 31.778 kHz 25.175 MHz 7 A/N 80 x 25 9 x 14 720 x 350 Mono 70 Hz 31.778 kHz 28.322 MHz 7+ A/N 80 x 25 9 x 16 720 x 400 Mono 70 Hz 31.778 kHz 28.322 MHz D APA - - 320 x 200 16 70 Hz 31.778 kHz 25.175 MHz E APA - - 640 x 200 16 70 Hz 31.778 kHz 25.175 MHz F APA - - 640 x 350 Mono 70 Hz 31.778 kHz 25.175 MHz 10 APA - - 640 x 350 16 70 Hz 31.778 kHz 25.175 MHz 11 APA - - 640 x 480 2 60Hz 31.778 kHz 25.175 MHz 12 APA - - 640 x 480 16 60Hz 31.778 kHz 25.175 MHz 13 APA - - 320 x 200 256 70 Hz 31.778 kHz 25.175 MHz Enhanced Modes 18 A/N 132 x 44 8 x 8 1056 x 352 Mono 70 Hz 30.5 kHz 40.00 MHz 19 A/N 132 x 25 8 x 14 1056 x 350 Mono 70 Hz 30.5 kHz 40.00 MHz 1A A/N 132 x 28 8 x 13 1056 x 364 Mono 70 Hz 30.5 kHz 40.00 MHz 22 A/N 132 x 44 8 x 8 1056 x 352 16 70 Hz 30.5 kHz 40.00 MHz 23 A/N 132 x 25 8 x 14 1056 x 350 16 70 Hz 30.5 kHz 40.00 MHz 24 A/N 132 x 28 8 x 13 1056 x 364 16 70 Hz 30.5 kHz 40.00 MHz 25 APA - - 640 x 480 16 72 Hz 38.7 kHz 32.512 MHz 26 A/N 80 x 60 8 x 8 640 x 480 16 60 Hz 31.5 kHz 28.322 MHz 29 APA - - 800 x 600 16 60 Hz 38.0 kHz 40.00 MHz 2A A/N 100 x 40 8 x 15 800 x 600 16 60 Hz 38.0 kHz 40.00 MHz 2D APA - - 640 x 350 256 70 Hz 31.5 kHz 25.175 MHz 2E APA - - 640 x 480 256 60 Hz 31.5 kHz 25.175 MHz 30 APA - - 800 x 600 256 60 Hz 38.0 kHz 40.00 MHz 37 APA - - 1024 x 768 16 60 Hz 49.9 kHz 65.00 MHz NTSC Modes - CCIR 601 Data Rates 3# A/N 80 x 25 9 x 16 640 x 480 16 60 Hz 15.73 kHz 27 MHz 12# APA - - 640 x 480 16 60Hz 15.73 kHz 27 MHz PAL Modes - CCIR 601 Data Rates 3@ A/N 80 x 25 9 x 16 640 x 480 16 50 Hz 15.62 kHz 27 MHz 12@ APA - - 640 x 480 16 50Hz 15.62 kHz 27 MHz good luck with it, Syms. "Sander Odekerken" <sander.odekerken@lycos.nl> wrote in message news:c4v3h8$93g$1@news2.tilbu1.nb.home.nl... > Hi everybody, > > I'm a student and for a project at school we have to make a VGA controller. > Does anyone have a good customizable example or does anyone know where to > download one? What do I have to do if I want to make one of my own. > > The input datawidth = 16 bit & the target device is a Xilinx Spartan IIE > FPGA. > > Thanks in advance, > > Sander Odekerken > >Article: 68502
"Sander Odekerken" <sander.odekerken@lycos.nl> wrote in message news:c4v3h8$93g$1@news2.tilbu1.nb.home.nl... > I'm a student and for a project at school we have to make a VGA controller. > Does anyone have a good customizable example or does anyone know where to > download one? www.engr.sjsu.edu/crabill Click on Lab 4 files. One of the verilog files is a video timing controller (VTC). More details on that at http://www.engr.sjsu.edu/crabill/projects/vtc/ > What do I have to do if I want to make one of my own. I think his codes are self explanatory. You can customize his code by changing the resolution, refresh rate etc. > The input datawidth = 16 bit & the target device is a Xilinx Spartan IIE > FPGA. Incidentaly, the input datawidth for the VTC is 16 bits and I have used this VTC for Xilinx Spartan IIE and it worked. HendraArticle: 68503
This is indeed a mistake in the diagram in Figure 20. The clock feeding the SRL16 should feed from the input clock (connected to CLKIN) and not from the feedback clock (connected to CLKFB). I will make sure that this is updated when we update XAPP462. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC <seyior> wrote in message news:ee83a9a.-1@WebX.sUN8CHnE... > Dear All: > I have tried the reset circuit for external feedback DCM on XAPP462 Figure 20. > > Is it ok to use feedback clock input as the shift register to generate DCM reset? Modelsim's wave tell me that DCM will not output clock when it is at reset. > > A miss for XAPP462 Figure 20? Or I made the misunderstanding. > > http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf > > regards, > seyior >Article: 68504
Followup to: <34c5542c.0404050818.6b93c6bc@posting.google.com> By author: haythamazmi@hotmail.com (H.Azmi) In newsgroup: comp.arch.fpga > > Iam using Sparatn II 200 connected to XC18V02 > I have founded that the programing of the FPGA takes a long time so > that I lost my master reset ... > The question is : Can I use the done signal internally to reset my > design ? > The easiest way to do this is to have a decrementer initialized in the bitstream to all ones; decrement until it's all zero. Now you have an internal reset signal that will be guaranteed asserted for a specific number of cycles after intialization. You can also OR (or AND, if inverted) with an external reset if you don't always reinitialize on reset. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 68505
Dear XILINX: Thanks for the immediate help. I am happy to be a XILNX FPGA designer. Regards, seyiorArticle: 68506
On Mon, 05 Apr 2004 07:53:14 -0700, Jim Lewis <Jim@SynthWorks.com> wrote: >Rajeev, >Make sure to turn on the VHDL-93 switch. > >You can do this in the compile options menu item under >compile in 5.7. Why do you suppose Modelsim defaults to -93 off? Perhaps someone should report this as a bug. Allan.Article: 68507
Hi, Andy, There are many things that will affect the optimal FPGA selection for your design including core performance, DSP capability, high-speed memory interfaces, clocking requirements, etc. not to mention the vendor specific development tools. I have been working on benchmarking Altera versus Xilinx and there are varieties of design and tool flow issues that will affect your result. When you benchmark, you will need to control the tool effort level (fast or exhaustive), software settings, timing constraints and clocks analyzed. These settings can cause results to change by up to 3X based on our benchmarks so understanding these options is fundamental to making a good performance comparison. In addition, you will need to be careful if your design is coded to take advantages of specific features in a FPGA. These issues will be discussed in a net seminar hosted by Altera on April 8th regarding effective FPGA performance benchmarking methodology and comparison of leading FPGA architectures. If you are interested, the registration link is here: http://www.altera.com/education/net_seminars/current/ns_0408.html John Hu Altera Corp. agwsu@yahoo.com (Andy) wrote in message news:<10c5be06.0404021109.319d5200@posting.google.com>... > Hi everybody, Could you people help me choose between Altera's Stratix > and Xilinx Vertex II...also as how to analyze the datasheet to > conclude the pros and cons of both the architectures? > thanks > -andyArticle: 68508
Hi, there: Is there anyway to merge the NGC cores from 3rd party vendors into my final NGC file? I found -read_cores YES only read in the NGC file for analysis... Best Regards, KelvinArticle: 68509
Altera only mentions the ByteBlaster II for programming Cyclone devices. Presumably the ByteBlasterMV doesn't have the right voltage thresholds, strictly speaking, but I was wondering if it could be used in a pinch. I made my own from the published schematic (it works fine with Flex10K devices), and would rather avoid having to buy the II, or make my own clone of it. LeonArticle: 68510
Or if someone was knowledgeable about what's inside a ByteBlaster II, that would be helpful. Because at $150, I don't want to imagine what the margin on these is. The ByteBlaster/MV are models of simplicity, I hope Altera keeps the spirit.Article: 68511
Hi,
I have a problem with accessing a procedure in a special manner:
Some background information:
I want to use a testbench in which I write the valid input data
(16bit) for my VHDL module under test into a ringbuffer. That is my
VHDL module gives out data (16 cleaned bit) after some pipelining
stages.
These output data should be compared with the data I have written into
my ringbuffer (The data in the ringbuffer are unstuffed, that is after
six consecutive ones the following zero is unstuffed. This unstuffing
function is of course also implemented in the VHDL module under test
itself.).
By the means of this object-oriented check I want to verify my module.
Here is my problem:
------------------------------------------------------------
architecture testb of xy is
signal t_Enable_in : std_logic;
signal t_Clk : std_logic;
signal t_Reset : std_logic;
signal t_In_data : std_logic_vector(15 downto 0);
constant history_size : integer := 1024;
signal t_history : std_logic_vector(history_size-1 downto 0);
...
procedure feed(signal d : in std_logic;
signal history : out std_logic_vector(history_size-1
downto 0)) is
variable ptr : integer range 0 to 1023;
variable n : integer range 0 to 6;
begin
if ((n=6) and (d='0')) then
null; --??? Does this exist in VHDL ?
else
history (ptr mod history_size) <= d;
end if;
if d='0' then
n:=0;
else
n:=n+1;
end if;
end feed;
begin
...
-------------------------------------------------------
-------------------------------------------------------
process(t_Reset, t_Clk)
begin
if t_Reset='1' then
t_history <= (others => '0');
elsif rising_edge(t_Clk) then
t_history <= t_history;
if t_Enable_in='1' then
for i in 15 downto 0 loop
feed(d => t_In_data(i),
history => t_history
);
end loop;
end if;
end if;
end process;
-------------------------------------------------------
-------------------------------------------------------
end testb;
I get the following error message (Modelsim5.7e)
# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(134):
The actual for parameter d must denote a static signal name.
# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(146):
VHDL Compiler exiting
How can I change that?
I would appreciate your time and help.
Kind regards
Andres V.
Article: 68512Hi all, no metter how hard I try, I couldn't find an appropriate way to set timing constraints to my project. The thing is, I create .xcf file, add it to the project, run synthesis, run translate, map and par and the effect is that all of my timing constraints are met. When I run the Timing Analysis, the reported clk period is even shorter than the one I need. Ok, I run simulation using ModelSim and .sdf and .vhd files which ISE PAR generated - and get simulation errors caused by too short clk period! How can I be sure that the tool 'understood' my constraints and implemented them as well? Thanks in advance! MarijaArticle: 68513
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using several 2:1 muxs'. Is there a suggested coding style to get xst to infer the larger muxes or how would i hardcode them to make larger muxes? Thanks MattArticle: 68514
This guy has got the schematics on his website. It is labelled Byteblaster MV, but it is the Byteblaster II though (as you can see by the name of the file). The schematics are indeed quite ... simple http://www.fuw.edu.pl/~gkasprow/ I've built the thing, and it seems to work. > Or if someone was knowledgeable about what's inside a ByteBlaster II, that > would be helpful. Because at $150, I don't want to imagine what the margin > on these is. > The ByteBlaster/MV are models of simplicity, I hope Altera keeps the spirit. > >Article: 68515
Usually your best chance of getting it is with a CASE statement. No guarantees though as synthesisers are notoriously unpredictable. You can also try structuring your VHDL to suggest a element layout. Instantiating macros in your HDL will give you a more exact structure. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu... > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using > several 2:1 muxs'. > Is there a suggested coding style to get xst to infer the larger muxes or > how would i hardcode them to make larger muxes? > > Thanks > > MattArticle: 68516
Hi Andres,
the problem is that an individual bit of a vector inside a
for loop is considered to be dynamic. In other words the indexing
is dynamic. This is because for loops are "dynamically elaborated".
Have a look at the section on "longest static prefix" in the
comp.lang.vhdl FAQ.
There are a number of possibilities
1) pass the whole vector into the procedure and test it all in one
go outside the for loop
2) re-write using a generate statement instead, i.e. create 16
parallel
processes, one per bit. The generate index is then constant (not
dynamically
elaborated) so it will be ok.
e.g.
g: for i in 15 downto 0 generate
> process(t_Reset, t_Clk)
> begin
> if t_Reset='1' then
> t_history <= (others => '0');
> elsif rising_edge(t_Clk) then
> t_history <= t_history;
> if t_Enable_in='1' then
> -- for i in 15 downto 0 loop
> feed(d => t_In_data(i),
> history => t_history
> );
>-- end loop;
> end if;
> end if;
> end process;
end generate;
Hope this helps - the comp.lang.vhdl FAQ section at
http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers
is worth reading anyway,
regards
Alan
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
Article: 68517"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:vdp670hd4nld9gof12hc92dgt04pbtu6rv@4ax.com... > On Mon, 05 Apr 2004 07:53:14 -0700, Jim Lewis <Jim@SynthWorks.com> > wrote: > > >Rajeev, > >Make sure to turn on the VHDL-93 switch. > > > >You can do this in the compile options menu item under > >compile in 5.7. > > Why do you suppose Modelsim defaults to -93 off? > Perhaps someone should report this as a bug. > > Allan. In Modelsim 5.8 it defaults to VHDL 2002, so I guess your wish is granted :-) regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68518
On Wed, 07 Apr 2004 12:22:43 +1000, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: [...] >Why do you suppose Modelsim defaults to -93 off? It doesn't any more - since about version 5.8, the default has been VHDL-2001. >Perhaps someone should report this as a bug. Hardly a "bug", when you can fix it by deleting just one comment character in the modelsim.ini file :-) But I have been known to call it a "bloody nuisance". -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68519
Hi, here is what seems odd to me: t_history <= t_history. I think you don't need to do this, i.e. if t_Enable_in is not asserted, this signal will keep the old value. The 'null' command exists in VHDL, but I've never used it in this way. Testbenches usually contain checker procedures to check if the output complies with the expected. You can set the checker procedure to notify you about the test results by: assert (condition_not_fulfilled) report "test passed"; assert (condition_fulfilled) report "test failed"; where condition means comparing the expected output with the data you collected from the output. I hope I offered you at least a hint :) BR, MarijaArticle: 68520
Hello all, I understand that I can assign timing constraints using a .ucf file. I tried defining one (using the wizard) and including it in the project. In synthesis properties it is not possible to point out a .ucf file, and a .xcf file is expected. I left this blank. I selected the option 'write timing constraints file' and run the synthesis process. I see the tool consulting the .ucf file and gives no warnings. I ran Implement design processes and have a information that all of the timing constraints are met. When I run the simulation using ModelSim, .sdf and .vhd file generated by the ISE tool, the results look like the timing constraints are not met (even if I select a frequency much smaller than the tool accepted). Hints? Thanks in advance, MarijaArticle: 68521
Hi Christian, I did change the reesolution to a ps, but the timing constraints is in ns, anyway. Still, it doesn't work :( MarijaArticle: 68522
Hi Marija, maybe you didn't change your simulation resolution to ps? (it is the -t option, or can also be found in a pull down menu in the ModelSim GUI) ChristianArticle: 68523
Rajeev wrote: /snip/ > Incidentally it appears to me that you could fix your problem by > setting enabletr<=3D'1' and using only enabledt, ie >=20 >=20 >>hi data bus driver : lpm bustri >> GENERIC MAP (LPM WIDTH =3D> 30 >> ) >> PORT MAP (data =3D> int dnio, >> enableDT =3D> NOT n0 dir, >> enableTR =3D> '1', >> result =3D> dnio inbus, <<*** this is the problem >> tridata =3D> dnio rec >> ); >=20 >=20 > It sure gets frustrating at times. Hope this helps, Thanks, this has helped indeed. The dnio_inbus is now connected directly = to the pin. An interesting consequence: Quartus pin assignment lists=20 show the same pins twice: once as inputs once as tri-state outputs. There are, however, some open questions remaining. 1./ It helped only in the given case. I have another design, where the=20 enableTR =3D> '1' and the result connection is unused (the output is=20 used as tristate output, no input) and the TRI buffer is replaced by an=20 OR gate. 2./ In both cases the compilation (Cadence) and the behavioral=20 simulation (Cadence NCsim) that uses Altera=B4s own=20 ldv40.5/altera/quartusIIv3.0/lpm/ libraries does its job without any=20 warning or error message. I guess the simulation library should show the = same behavior as the Fitting tool Quartus. Thanks for your help. Janos Ero CERN Div. EPArticle: 68524
I think the best is to use GSR but I don't know how to use it in my design can you give me example ? knowing that Iam using spartan II 200 H. Peter Anvin <hpa@zytor.com> wrote in message news:<c4vh9s$l40$1@cesium.transmeta.com>... > Followup to: <34c5542c.0404050818.6b93c6bc@posting.google.com> > By author: haythamazmi@hotmail.com (H.Azmi) > In newsgroup: comp.arch.fpga > > > > Iam using Sparatn II 200 connected to XC18V02 > > I have founded that the programing of the FPGA takes a long time so > > that I lost my master reset ... > > The question is : Can I use the done signal internally to reset my > > design ? > > > > The easiest way to do this is to have a decrementer initialized in the > bitstream to all ones; decrement until it's all zero. Now you have an > internal reset signal that will be guaranteed asserted for a specific > number of cycles after intialization. You can also OR (or AND, if > inverted) with an external reset if you don't always reinitialize on > reset. > > -hpa
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