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Sander, I apologize if I have offended. Just wanted to be sure to balance the scales. AustinArticle: 68551
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:EiYcc.383059$Or1.126922@news.chello.at... > > Altera only mentions the ByteBlaster II for programming Cyclone > devices. > > Presumably the ByteBlasterMV doesn't have the right voltage > thresholds, > > strictly speaking, but I was wondering if it could be used in a > pinch. I > > made my own from the published schematic (it works fine with Flex10K > > devices), and would rather avoid having to buy the II, or make my > own clone > > of it. > > The ByteBlasteMV works quite well with the Cyclone. I'm using it in > the JTAG mode. Thanks, I'll try it. I suppose it could depend on how the I/O banks are configured. LeonArticle: 68552
You can merge netlists together through ngcbuild (not ngdbuild). Ncgbuild would then merge all the netlist into a single ngc file. This was introduced in 6.2i. I find it kinda quirky that Ngcbuild reads in an NGC and produces an NGC, so you'll need to be careful renaming your output NGC so as not to clash with your input NGC. Kelvin @ SG wrote: > Hi, there: > > Is there anyway to merge the NGC cores from 3rd party vendors into my final > NGC file? > I found -read_cores YES only read in the NGC file for analysis... > > Best Regards, > Kelvin > > > > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 68553
Thanks for the help valentin. I want to use the Xilinx XC9536. If I use a pull-down resitor, I can do a Wired-OR with several pins, right? Bruno "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de... > > The one I can think of: > > if OR_REDUCE(drivers) = '1' then > w <= DRIVE(1) > else > w <= DRIVE(0); > > > > > Externally, you would pull-up a line by resistor to Vcc and implement > transistor internally in FPGA: > > O <= '0' when A = '0' else 'Z'; > > cheers. > >Article: 68554
Well, there are a few ways I can think of:
1) Use TBUFs to wire-OR LUT outputs together
2) Use the OR cascade in virtexII in the same way, preferable because it is
faster and more plentiful
3) If you can accept a 16 clock set-up time, you can use the SRL16 as a
programmable LUT. The programmer uses 2.5 slices, and loads up the SRL16 (or a
word wide bank of them) with the appropriate pattern to connect the selected
input to the output ( patterns are for a mux with enable are
X"0000",X"AAAA",X"CCCC",X"F0F0",X"FF00"). This is useful for minimum
propagation time 4:1 muxes for applications where the selection is relatively
static, or is otherwise allowed time to complete. Yes, I have used it.
4) if your sources to the mux have available terms or come from flip-flops, you
can substitute a 4 input OR for each MUX bit by having your select logic gate
off all but one of the inputs at any given time. If the inputs are from
flip-flops, you can use the sync reset on the flip-flops for the gate function
without having to add logic in front of the flip-flop other than the decoder on
the reset.
Kevin Neilson wrote:
> "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
> news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu...
> > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
> > several 2:1 muxs'.
> > Is there a suggested coding style to get xst to infer the larger muxes or
> > how would i hardcode them to make larger muxes?
> >
> > Thanks
> >
> > Matt
>
> I don't understand how you would make a 4:1 mux in a Xilinx without making
> it out of smaller muxes. The LUTs only have 4 inputs, so you can't make a
> 4:1 mux out of a single LUT. You need two LUTs plus another F5 mux.
> -Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68555yeah, that was the way i did it. but i think it is a good idea to give user the option to merge NGC files...i am glad ise-6.2 has implemented that. Kelvin Fernando <fortiz80@tutopia.com> wrote in message news:2658f0d3.0404070601.30d8cb41@posting.google.com... > > Is there anyway to merge the NGC cores from 3rd party vendors into my final > > NGC file? > > I found -read_cores YES only read in the NGC file for analysis... > > I think you have to instantiate your cores as black boxes for > synthesis, and then integrate them into the design during the > translate stage > > You can run PAR and use the floorplanner to capture your new (bigger) > NGC core. XAPP 422 has all the details. > > That's the way I do it, but it may not be the only solution. > > Fernando OrtizArticle: 68556
ngdbuild should automatically pick up a ucf file if it is included in the project. You can also try adding "-uc ucf_file_name" to the ngdbuild command line. I'd double check the clock frequency on the waveform. You clock generation code may assume a time unit and only use a number as the period. This may not work if the timing simulation uses a different time unit than the one used in the functional simulation. HTH, Jim jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chips "Marija" <gemini@verat.net> wrote in message news:ee83aea.-1@WebX.sUN8CHnE... Hello all, I understand that I can assign timing constraints using a .ucf file. I tried defining one (using the wizard) and including it in the project. In synthesis properties it is not possible to point out a .ucf file, and a .xcf file is expected. I left this blank. I selected the option 'write timing constraints file' and run the synthesis process. I see the tool consulting the .ucf file and gives no warnings. I ran Implement design processes and have a information that all of the timing constraints are met. When I run the simulation using ModelSim, .sdf and .vhd file generated by the ISE tool, the results look like the timing constraints are not met (even if I select a frequency much smaller than the tool accepted). Hints? Thanks in advance, MarijaArticle: 68557
john jakson wrote: > > "John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>... > > Usually your best chance of getting it is with a CASE statement. No > > guarantees though as synthesisers are notoriously unpredictable. > > > > You can also try structuring your VHDL to suggest a element layout. > > > > Instantiating macros in your HDL will give you a more exact structure. > > > > -- > > John Adair > > Enterpoint Ltd. > > http://www.enterpoint.co.uk > > > > This message is the personal opinion of the sender and not that necessarily > > that of Enterpoint Ltd.. Readers should make their own evaluation of the > > facts. No responsibility for error or inaccuracy is accepted. > > > > > > "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message > > news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu... > > > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using > > > several 2:1 muxs'. > > > Is there a suggested coding style to get xst to infer the larger muxes or > > > how would i hardcode them to make larger muxes? > > > > > > Thanks > > > > > > Matt > > look in the XST templates. > > In Verilog > > x <= > (sel==0)? a0 : > (sel==1)? a1 : > (sel==2)? a2 : > (sel==3)? a3 : > an > > and so on works for me. I've gone to 8 no problem. But occasional use > of hardcoding a MUXxyz can help to build the top stage if you need to > combine say a 2->1 with an earlier 4->1 and so on. There are quite a > few app nots in the xapp dir. I have not tried coding this in XST, but I am pretty sure it does not result in an 8:1 mux. The syntax you show is a priority selector. That means that it indicates an order of precedence. Even though it makes no difference since the selectors in each case are mutually exclusive, it is unlikely that this will be optimized to a proper mux. The recommended coding style would be a case statement, which by definition has mutually exclusive selections of a single control variable. A better coding method for bus muxes would be to pre-decode the selectors so that each of the 8 mux inputs has a separate enable. Then an 8 input mux can be done in just two levels of LUTs. The first level can encode the AND gates and one OR gate for combining two inputs. The second level is an four input OR gate for the final output. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68558
When trying to create a mux with a case statement XST requires the output be a reg. Why is this and would making it a reg(latch) make the mux slower? Matt On Thu, 8 Apr 2004, rickman wrote: > john jakson wrote: > > > > "John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>... > > > Usually your best chance of getting it is with a CASE statement. No > > > guarantees though as synthesisers are notoriously unpredictable. > > > > > > You can also try structuring your VHDL to suggest a element layout. > > > > > > Instantiating macros in your HDL will give you a more exact structure. > > > > > > -- > > > John Adair > > > Enterpoint Ltd. > > > http://www.enterpoint.co.uk > > > > > > This message is the personal opinion of the sender and not that necessarily > > > that of Enterpoint Ltd.. Readers should make their own evaluation of the > > > facts. No responsibility for error or inaccuracy is accepted. > > > > > > > > > "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message > > > news:Pine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu... > > > > I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using > > > > several 2:1 muxs'. > > > > Is there a suggested coding style to get xst to infer the larger muxes or > > > > how would i hardcode them to make larger muxes? > > > > > > > > Thanks > > > > > > > > Matt > > > > look in the XST templates. > > > > In Verilog > > > > x <= > > (sel==0)? a0 : > > (sel==1)? a1 : > > (sel==2)? a2 : > > (sel==3)? a3 : > > an > > > > and so on works for me. I've gone to 8 no problem. But occasional use > > of hardcoding a MUXxyz can help to build the top stage if you need to > > combine say a 2->1 with an earlier 4->1 and so on. There are quite a > > few app nots in the xapp dir. > > > I have not tried coding this in XST, but I am pretty sure it does not > result in an 8:1 mux. The syntax you show is a priority selector. That > means that it indicates an order of precedence. Even though it makes no > difference since the selectors in each case are mutually exclusive, it > is unlikely that this will be optimized to a proper mux. > > The recommended coding style would be a case statement, which by > definition has mutually exclusive selections of a single control > variable. > > A better coding method for bus muxes would be to pre-decode the > selectors so that each of the 8 mux inputs has a separate enable. Then > an 8 input mux can be done in just two levels of LUTs. The first level > can encode the AND gates and one OR gate for combining two inputs. The > second level is an four input OR gate for the final output. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 68559
"Christoph Brinkhaus" <c.brinkhaus@t-online.de> wrote in message news:4enu4c.hl.ln@lola.de... > Antti Lukats <antti@case2000.com> wrote: > > Hi Antti! > > > >> Your USB clock needs a 48MHz clock speed. I have a Nios Development Board > >> with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz > >> (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's > >> the best that I can get. > > > > it will receive 100% ok also with 50MHz clock > > I once tested accidently, not sure if the hosts will accept 50MHz transmit > > 48.08 will defenetly work both ways, not matter if it is withing spec range > > or not > > At work we have also worked on USB devices which are connected to a PC. > In this case the tolerance of ceramic resonator can be too much. I am > not sure about the exact figures, if I am not wrong the spec is about > +/-100ppm or slightly more. In some application notes you can find also > statements like "should not work with ceramic resonators but no problems > in practice". So using a 50MHz clock does not sound too much promising > for me. Sure, I just said that the opencores usb1_phy DPLL tolerates 50MHz on the receive side! as I by accident did figure out. nothing more. for any serious projec the specs should be followed of course! anttiArticle: 68560
"Stéphane Acounis" <Dans.le@Reply.to> wrote in message news:pan.2004.04.07.12.53.42.186782@Reply.to... > Hello, > > I have installed the latest Quartus version for Linux, applied the service > pack 1 and still have problem with it: as soon as I want to edit my VHDL > top design file, Quartus crashes with no error message. > I have removed all the accentuated letters but it did not resolved the > problem. > I am running a RedHat 9, I know it is not officialy supported but Altera > did modify the scripts to include the magic LD_ASSUME_KERNEL variable to > make it run. > > I can compile the design, simulate it but not editing it! > > Any clue? Thanks. I don't know specifically, but there's a couple of things you might try. Firstly run strace, e.g. strace quartus and it will show what is being executed by the program when it crashes. Secondly, as you mention accented letters, have you tried setting the system language to "C"? You can do this by editing /etc/sysconfig/i18n to contain LANG=C Good luck! Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68561
hi! does anybody know how to handle this error? it occurred when implementing a design in a 2v1000 -5 with ise 6.2.01i: ************************************************************************ Running related packing... FATAL_ERROR:Ncd:basncsignal.c:283:1.39.8.2 - Could not find a bel for a signal on pin BYOUT of comp i_top_mainpath_i_channelengine_RPF2_INTPOL_BETRAG_i_sctb1_low/BU77/G.S0. Its current programmed state is : F:#RAM:D=0x0000 G_ATTR:DUAL_PORT DIG_MUX:ALTDIG DIF_MUX:ALTDIF SLICEWE0USED:0 F_ATTR:DUAL_PORT BYOUTUSED:0 G:#RAM:D=0x0000 BYINVOUTUSED:0 SLICEWE1USED:0 WF1USED:0 WF2USED:0 WF3USED:0 WF4USED:0 WG1USED:0 WG2USED:0 WG3USED:0 WG4USED:0 BXOUTUSED:0 BXINV:BX CLKINV:CLK SRINV:SR Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com Design Summary -------------- Number of errors : 1 Number of warnings : 19 ERROR: MAP failed Process "Map" did not complete. Mapping Module top_shell . . . MAP command line: map -intstyle ise -p xc2v1000-bg575-5 -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off -o top_shell_map.ncd top_shell.ngd top_shell.pcf Mapping Module top_shell: failed ************************************************************************ checking the answer database from xilinx support was not very helpful. kind regards wolfgangArticle: 68562
> "Eric Paillet" <epaillet@antwerpen.be> wrote in message > news:4073b644$0$1991$ba620e4c@news.skynet.be... > > This guy has got the schematics on his website. It is labelled Byteblaster > > MV, but it is the Byteblaster II though (as you can see by the name of the > > file). The schematics are indeed quite ... simple > > > > http://www.fuw.edu.pl/~gkasprow/ > > > > I've built the thing, and it seems to work. > > Thanks Eric. I downloaded the file and got it converted to ASCII format by > someone with Protel, so I can read it into Pulsonix. It's definitely a lot > different from the MV - uses three '244 chips and a transistor. I'll be > making a PCB for it and putting the design on my web site. If anyone else > wants the ASCII Protel file I can make it available. > > Leon > > Could You please send us a copy of the converted BBII schematics in a readable form (*.Bit, *.PDF, *.gif, ...) or make them available on the net? Think a specialized format is not good for publishing ... -Thanks.- with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 68563
Hi, I have problem using the XAPP662 readframe and writeframe functions. First I read a frame, then I write some byte of the frame and after I read it again to see the change. The problem is that when I try to write the frame, there is only the pad frame that get updated, the data frame is not modified and I don't understant why. Thanks in advance. JonathanArticle: 68564
I was used to Xilinx ISE already now I want to learn Quartus for some work experience... I like the GUI but I don't understand why must Altera deliver the Chip Editor but not license it!!! And why they can't give a permanent license... KelvinArticle: 68565
"Peter Seng" <NOSPAM@seng.de> wrote in message news:c530f4$gp3$1@online.de... > > > "Eric Paillet" <epaillet@antwerpen.be> wrote in message > > news:4073b644$0$1991$ba620e4c@news.skynet.be... > > > This guy has got the schematics on his website. It is labelled > Byteblaster > > > MV, but it is the Byteblaster II though (as you can see by the name of > the > > > file). The schematics are indeed quite ... simple > > > > > > http://www.fuw.edu.pl/~gkasprow/ > > > > > > I've built the thing, and it seems to work. > > > > Thanks Eric. I downloaded the file and got it converted to ASCII format by > > someone with Protel, so I can read it into Pulsonix. It's definitely a lot > > different from the MV - uses three '244 chips and a transistor. I'll be > > making a PCB for it and putting the design on my web site. If anyone else > > wants the ASCII Protel file I can make it available. > > > > Leon > > > > > > Could You please send us a copy of the converted BBII schematics in a > readable form (*.Bit, *.PDF, *.gif, ...) or make them available on the net? > Think a specialized format is not good for publishing ... I output it from Pulsonix as a PS file and converted it to a PDF: http://www.leonheller.com/bb.pdf It really needs the colours changing on the imported schematic to remove the black areas, but you should be able to follow it. I'm not sure if it really is compatible with the BBII, I'll try my BBMV clone on the Cyclone first and see how I get on. LeonArticle: 68566
Le Thu, 08 Apr 2004 08:31:57 +0100, Alan Fitch a écrit : > > I don't know specifically, but there's a couple of things you might > try. > > Firstly run strace, e.g. > > strace quartus > I will try this when I will reinstall it! It only crashes with the text editor not when compiling or simulating. > and it will show what is being executed by the program when it crashes. > > Secondly, as you mention accented letters, have you tried setting the > system language to "C"? You can do this by editing > > /etc/sysconfig/i18n to contain LANG=C > It is already done by the qenv script when Quartus is launched. Beside this, I have replaced all the accented letters and it still crashed. If no one else experiences the same problem, I guess that my setup is wrong and I will have to find out what I have done bad. Thanks for your help. -- Stéphane ACOUNIS "Oh le beau mur, il faut qu'je freine!" Ayrton SegaArticle: 68567
Martin Schoeberl wrote: <snip> > The ByteBlasteMV works quite well with the Cyclone. I'm using it in > the JTAG mode. > > Martin > -- The drawback is that BBMV can't program EPCS devices....Article: 68568
I think, yes. You'll pull the line up by resistor (several kilos?). CPLD will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0 otherwise. The same can be applied to pull-down resistor and '1', 'Z' drivers. Line will be zero when nothing drives it. If CPLD outputs support 'Z' state then I see no problem. "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message news:40748144$0$15193$a729d347@news.telepac.pt... > Thanks for the help valentin. > > I want to use the Xilinx XC9536. > If I use a pull-down resitor, I can do a Wired-OR with several pins, right? > > Bruno > > > "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na > mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de... > > > > The one I can think of: > > > > if OR_REDUCE(drivers) = '1' then > > w <= DRIVE(1) > > else > > w <= DRIVE(0); > > > > > > > > > > Externally, you would pull-up a line by resistor to Vcc and implement > > transistor internally in FPGA: > > > > O <= '0' when A = '0' else 'Z'; > > > > cheers. > > > > > >Article: 68569
use case statement to infer 4:1 mux case sel is when "00"=> -- or use basic gates to form 2:1 mux then use this mux in structural way this will help synthesizer to optimise logic at boolean optimisation levelArticle: 68570
Hi!
from the manual given along with the reference design, it seems you
should use the C_BASEADDR to access user logic. I think your code should
work if you change the CORE_ADDR macro definition to C_BASE_ADDR.
#define CORE_ADDR C_BASE_ADDR
--yang
Joe wrote:
> Hello,
>
> I am trying to add user logic to an EDK project. I have tried attching
> to both the OPB and PLB busses using the ssp0 reference designs. I
> have striped down the user logic portion of the reference designs to
> be like a RAM that I can write to /read from. I can download the
> design to the development board, but the data that I read back is
> garbage.
>
> In the MHS file for the core, I have:
> BEGIN plb_simple_core
> PARAMETER INSTANCE = plb_simple_core_0
> PARAMETER C_BASEADDR = 0xD0000000
> PARAMETER C_HIGHADDR = 0xD000FFFF
> PARAMETER c_mir_baseaddr = 0xD0010100
> PARAMETER c_mir_highaddr = 0xD00101FF
> BUS_INTERFACE SPLB = plb
> PORT plb_clk = sys_clk
> END
>
> And in the C code I have:
> #define CORE_ADDR XPAR_PLB_SIMPLE_CORE_0_BASEADDR
>
> Xuint32 reg_0;
>
> // Write data to core
> XIo_Out32( (CORE_ADDR + 0x0000), 0x00000000); // or some other data
>
> // Read data from core
> reg_0 = XIo_In32((CORE_ADDR + 0x0000));
> xil_printf("Data at address 0 is: %d \r\n", reg_0);
>
> Is this the correct method for reading/writing to the core?
>
> If so any idea where else my error could be?
>
> Thanks,
> Joe
Article: 68571
Why does it require a register? Yes it has to be in a process, but the process can be one sensitive to the
mux inputs rather than to clock. You can also use the switch statement instead, which is a concurrent
equivalent to the case.
Matthew E Rosenthal wrote:
> When trying to create a mux with a case statement XST requires the output
> be a reg. Why is this and would making it a reg(latch) make the mux
> slower?
>
> Matt
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68572Hi Rudi, Apologies for asking you to repeat your question but I can't see it on my news reader. I can however tell you that (as Ben has said) timing constraints applied to the input side of the DCM will result in timing constraints being automatically generated on the outputs.. I can only assume you are generating both these clocks from the same DCM (i.e. you are applying a single clock constraint to a single input clock) and this constraint is then being propogated. If you repeat your question, I will try to help where I can, Best Regards, Steve Merritt BEng (Hons) CEng MIEE XILINX Gold Certified Field Applications Engineer Insight MEMEC ( +44 (1296) 330061 È+44 (7766) 470756 ? smerritt@insight.uk.memec.com Click link below for more information on : XILINX Free Training <http://www.xilinx.com/support/training/europe-home-page.htm> XILINX Design Services <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service s> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm> Or Tel - 08707 356532 for more information "Ben Howe" <bmhowe@yahoo.com> wrote in message news:df26a773.0404010628.4cd19478@posting.google.com... > Rudolf Usselmann <russelmann@hotmail.com> wrote in message news:<c4gbkq$6gv$1@nobel.pacific.net.sg>... > > Hi Ben, > > > > yes I have tried that as well, and yes it does work, > > except the timing between the 60 and 75 MHz clocks > > can not be separated (at least thats what it seems > > to me). > > > > It creates a dependency between the clocks (I think). > > I meet the 60 MHZ timing but the 75MHz timing is off > > by a factor of 2 ! (I meet all timing if I use separate > > clock inputs for the DCMs.) > > > > How do you constrain the outputs of the DCMs in your > > UCF file ? > > Hi Rudi, > > I only constrain the input clock to the DCM and the constraints for > the output clocks are automatically generated. Maybe you should try > specifying a FROM-TO constraint across clock domains. Here is my UCF > file: > > # Constrain the input to the DCMs > NET "clk100" TNM_NET = "clk100"; > TIMESPEC "TS_clk100" = PERIOD "clk100" 10 ns HIGH 50 %; > > # Create a timing constraint to constrain paths that cross clock > domains > NET "clk60" TNM_NET = "clk60"; > NET "clk75" TNM_NET = "clk75"; > TIMESPEC "TS_crosscycle" = FROM "clk60" TO "clk75" 5 ns; > > Regards, > BenArticle: 68573
hi Marija there are two possibility one u may not have apply reset for long enough time ,which will not initialise internal logic properly(this will be case if u r using asyncronous reset) nother possibility is if ur toplevel entity has bidirectional port then dont forget to use pullup/pulldown resistor model in test bench let me know is this help u or notArticle: 68574
Just using the done signal as the reset for the rest of the board could be dangerous. Here is why: The done signal indicates that programming of the SpartanII is complete and correct. If the configuration of the FPGA was not correct (i.e. the CRC that is performed failed) the done bit will not be set. If you are using a PROM and the configuration fails than your whole board will be in reset. So what do you do now? Depending on your situation this may or may not be catastrophic. If you also have a controller/processor on the board which is stopped from operating from this case you cannot recover. That may or may not be OK, again depending on your situation. Board power up and control needs to be thought about and designed up front--this is especially true with SRAM based FPGAs that do nothing on initial powerup and take time to load. Opinions expressed are my own and may or may not reflect any other human or organisation. Use at your own peril. ~ >>> H.Azmi<haythamazmi@hotmail.com> 4/5/2004 12:18:11 PM >>> Iam using Sparatn II 200 connected to XC18V02 I have founded that the programing of the FPGA takes a long time so that I lost my master reset ... The question is : Can I use the done signal internally to reset my design ?
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