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"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<40e3dd69$0$291$cc9e4d1f@news-text.dial.pipex.com>... > "Daragoth" <daragoth@kuririnmail.com> wrote in message > news:317379a8.0406302118.32829ee1@posting.google.com... > > Hi, I have just began working with FPGA devices and have been trying > > to apply them in real-world situations. For my first project I need a > > very small, relatively inexpensive "bare-bones" type FPGA board. But > > I have been having difficulty finding one. I just need one with the > > following features (please tell me if I'm missing anything vital): > > > > -FPGA device with at least 15,000 usable gates (more would be > > preferable). I only need a small number of user IOs, so that > > shouldn't be an issue at all. The device doesn't need to be very fast > > either, as it will be running only at around 4 MHz. > > -clock with only around 4 MHz frequency range... higher isn't a > > problem however. > > -in-circuit reprogrammable non-volatile memory device for storing the > > FPGA's configuration data. > > -The most important thing is that it all fits within a 40 mm x 30 mm x > > 10 mm volume or less. > > > > More features than this obviously isn't a problem, provided it doesn't > > make the board larger than the specified volume. Do boards like this > > exist for purchase, or will I have to build it myself? I am > > inexperienced in the area of designing PCBs so I would prefer to buy > > it already made. Is it even possible to build this device in such a > > small volume? Thanks for your help. > > I was thinking of designing something like that, with an Altera Cyclone > EP1C100 (2,910 LEs) and an EPCS1 configuration device. I don't know how many > gates 2,910 LEs is, but it might be enough for you. > > Leon Hi just my 0.02$ worth of tought If I remember my gate counting skill regarding Altera and LE's 15k Gates are roughly 750LE's. Marketing will make it any number:). But to be serious even a Cyclone EP1C3 in a TQFP package is 16X16mm in size add the small config mem to that and probably some power supplies (3.3V and 1.5V) and the board starts to grow. One possible solution is to use the new MAX2 family, the EPM1270 in TQFP144 is 22x22 mm has 1270 LE's (more than 15k gates) don't need config mem and has also a internal (not so accurate, but spect above 4MHz) clock. Furthermore only needs one power supply (3.3V). On the power side it is also less power hungry and you can probably do with a linear regulator and not use switch mode power (witch is a pest when coming to size, those darn inductors and caps are real board eaters). Cheers FredrikArticle: 70901
hey guys! i trie to simulate a dcm design with modelsim, but the dcm doesn't start. i tried to reset the dcm after applying clkin, it seems, that the dcm is working, but clkfx is only a amount of spikes instead of a 50:50 clock but at the right frequency. clkin is a 60%:40% clock with 33 MHz. anyone out there with the same problem? thx wolfgangArticle: 70902
license_rant_master wrote: > I am an ASIC engineer who frequently 'takes work home' with me. <snip> With a standard cable or DSL connection, VNC works pretty well. I don't think it could violate any license since it only virtualizes the interface, and that part at least, should be fully owned by the user. Overzealous license agreements that try to impose what you do with your hardware should be slapped down by the courts, but the increasing virtualization /globalization blurs the 'site' definition. Interesting stuff. If VNC really does not work for you, there must be a way that your vendor can extend/change the license to one or more node locked seats (tied to a removable NIC, say). Node locked seats should never be restricted by distance from the license server. Rant on dude. We should all have the right to use every legitimate seat 24/7, no matter where we are.Article: 70903
I just read a press release about "power reduced" Spartan 3s. They don't give much in the way of numbers, they just say the quiescent power is reduced by *up to* 66%. The last time I checked the data sheets, there were no power figures. Anyone know what actuals might be attached to this value? Just how much quiescent power do these chips suck down? Numbers on the XC3S400 would be useful. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70904
In article <SGMEc.2916$486.1576@newssvr25.news.prodigy.com>,
license_rant_master <none@nowhere.net> wrote:
>According to the language/legalese of the license-agreement, a license
>'seat' is tied to a physical location called 'site.'
I've heard that this is to prevent on-site consultants from sharing their
personal license (or more likely, the consultant's company's license) with
their customer. Otherwise only ASIC consulting companys would be buying the
$500K licenses.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 70905ssharma@gmail.com (xyz) wrote in message news:<47dcad3e.0406301903.14dcd378@posting.google.com>... > PL-USB-BLASTER is faster than PL-BYTEBLASTER2 (specially in Passive > Serial programming mode) > > ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0406280522.1fe77b20@posting.google.com>... > > Hi newsgroup users, > > > > can someone tell me how to define the programming time of a EP1C12 Cyclone > > when using PL-BYTEBLASTER2 cable in comparison to PL-USB-BLASTER cable? > > > > Thank you for your help. > > > > > > Rgds ThanX. Do you have some concrete numbers concerning programming time?Article: 70906
license_rant_master <none@nowhere.net> writes: > I am an ASIC engineer who frequently 'takes work home' with me. > ... According to the > language/legalese of the license-agreement, a license 'seat' > is tied to a physical location called 'site.' Here's a hint: like a lot of things in life, these restrictions are negotiable if you are a big enough customer.Article: 70907
> 2. What happens during power up and configuration ? Is the PCI diode in > circuit at this time ? From memory the data sheet discusses limiting the input current using a resistor. It then says that during configuration the PCI clamp diode is not in circuit so you need to make sure there are no 5V signals applied before the end of cunfiguration! Pretty limiting, I always use IDT quickswitches to protect the FPGA pins from 5V inputs. They're simple, work well and cheap as chips (french fries). Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 70908
daragoth@kuririnmail.com (Daragoth) wrote in message news:<317379a8.0406302118.32829ee1@posting.google.com>... > Hi, I have just began working with FPGA devices and have been trying > to apply them in real-world situations. For my first project I need a > very small, relatively inexpensive "bare-bones" type FPGA board. But > I have been having difficulty finding one. I just need one with the > following features (please tell me if I'm missing anything vital): > > -FPGA device with at least 15,000 usable gates (more would be > preferable). I only need a small number of user IOs, so that > shouldn't be an issue at all. The device doesn't need to be very fast > either, as it will be running only at around 4 MHz. > -clock with only around 4 MHz frequency range... higher isn't a > problem however. > -in-circuit reprogrammable non-volatile memory device for storing the > FPGA's configuration data. > -The most important thing is that it all fits within a 40 mm x 30 mm x > 10 mm volume or less. > > More features than this obviously isn't a problem, provided it doesn't > make the board larger than the specified volume. Do boards like this > exist for purchase, or will I have to build it myself? I am > inexperienced in the area of designing PCBs so I would prefer to buy > it already made. Is it even possible to build this device in such a > small volume? Thanks for your help. > > > Sincerely, > Darien A. Gothia Sounds suspiciously like credit card sz of which armoid comes to mind. http://armoid.com/store/catalog/product_info.php?products_id=28&osCsid=4f58554bddd3dd7b0e86fd94df0b2808 I have seen a no of weeny size boards but can't recall where, the low cost guys often have little formats xess, burch, etc http://www.fpga-faq.com/FPGA_Boards.shtml regards johnjakson_usa_comArticle: 70909
Kelvin wrote: > Hi, there: > > I remembered there was a constraint that can prevent MAP from > removing floating input pins? What is it? > > Thanks. > Kelvin > > > > The net constraint "S" will block trimming on an undriven or unloaded net. An example of UCF syntax is: NET "net_name" S ; When map is run with the "-u" switch, this constraint is automatically applied throughout the design. BretArticle: 70910
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:cbv012$fhr$1$8302bc10@news.demon.co.uk... > Steven K. Knapp wrote: > > The Xilinx online store has stock will ship boards to practically > > anywhere on this planet. > > Alightly off-topic, but it would be really really helpful if > the online store could move into the 20th century and start > selling FPGAs. No need to stock all speed grades or compete > on price. > > And, as I've said before, if X management don't want to handle > this, subcontract it to Amazon or DigiKey or whoever. Just make > it possible for designers to order prototype quantities without > going through the distributor tarpit - it would help your overall > business. Try www.nuhorizons.com for small quantities. -- GeorgiArticle: 70911
Hi Gottfried, I don't know, you academics poisoning those kids' minds with your crazy plans! ;-) Just kidding, sounds like an interesting project, I wish you the best of luck with the timing tools provided by the FPGA manufacturers! cheers, Syms. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E3C0E0.5040101@ecs.tuwien.ac.at... > I know that synchronous RAMs are preferable, but the asynchronous RAMs > are needed in my design due to the fact that it is a processor design > that is fully asynchronous. > > regards > Gottfried >Article: 70912
"Fully asynchronous", ohmygod! Well, you can always generate a strobe pulse when you want to read or write. We would call that a clock, but if your religion forbids that, you can call it something else..We are agnostic, up to a point :-) Peter Alfke ================================================= > From: "Symon" <symon_brewer@hotmail.com> > Newsgroups: comp.arch.fpga > Date: Thu, 1 Jul 2004 09:39:08 -0700 > Subject: Re: FPGA with fully asynchronous RAM > > Hi Gottfried, > I don't know, you academics poisoning those kids' minds with your crazy > plans! ;-) > Just kidding, sounds like an interesting project, I wish you the best of > luck with the timing tools provided by the FPGA manufacturers! > cheers, Syms. > "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message > news:40E3C0E0.5040101@ecs.tuwien.ac.at... >> I know that synchronous RAMs are preferable, but the asynchronous RAMs >> are needed in my design due to the fact that it is a processor design >> that is fully asynchronous. >> >> regards >> Gottfried >> > >Article: 70913
In article <40E3C0E0.5040101@ecs.tuwien.ac.at>, Fuchs Gottfried <fuchs@ecs.tuwien.ac.at> wrote: >I know that synchronous RAMs are preferable, but the asynchronous RAMs >are needed in my design due to the fact that it is a processor design >that is fully asynchronous. I'm sorry for the pain you are going to suffer making self timing circuits in an FPGA. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 70914
Joseph H Allen wrote: > In article <SGMEc.2916$486.1576@newssvr25.news.prodigy.com>, > license_rant_master <none@nowhere.net> wrote: > > >>According to the language/legalese of the license-agreement, a license >>'seat' is tied to a physical location called 'site.' > > > I've heard that this is to prevent on-site consultants from sharing their > personal license (or more likely, the consultant's company's license) with > their customer. Otherwise only ASIC consulting companys would be buying the > $500K licenses. > or an america and european company could get together and share licenses, with a 7-8-9 hour time difference they wouldn't need the licenses at the same time I think some companies (big ones) can a special license, I know one that share worldwide and I would think they have a pool of licenses -LasseArticle: 70915
license_rant_master wrote: > I am an ASIC engineer who frequently 'takes work home' with me. > Recently, I began using ssh to remotely login to our company's > servers to run some Verilog/VHDL simulations. Launching [SNIP] > For now, I've simply told my supervisor 'project schedule slip.' > And I've given up on doing real work at home (now mostly just > catching on documentation and inline RTL-comments.) I'm glad you did speak up ! I wish more people would - preferably not anonymously ... Here is another free Verilog simulator, you might find it will run the more serious verilog jobs: http://www.pragmatic-c.com/gpl-cver/ Runs on Linux ... Good Luck ! Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 70916
tns1 wrote: > > license_rant_master wrote: > > I am an ASIC engineer who frequently 'takes work home' with me. > <snip> > > With a standard cable or DSL connection, VNC works pretty well. I don't > think it could violate any license since it only virtualizes the > interface, and that part at least, should be fully owned by the user. > Overzealous license agreements that try to impose what you do with your > hardware should be slapped down by the courts, but the increasing > virtualization /globalization blurs the 'site' definition. Interesting > stuff. > > If VNC really does not work for you, there must be a way that your > vendor can extend/change the license to one or more node locked seats > (tied to a removable NIC, say). Node locked seats should never be > restricted by distance from the license server. Rant on dude. We should > all have the right to use every legitimate seat 24/7, no matter where we > are. I can tell that this is going to be one of those long threads that have a loooong life. Software companies charge with two principles in mind. One is the cost of doing busisness. If you buy three licenses for a given location the vendor can expect an average level of support that they will need to provide to that site and others like it. If they allow you to use the same license at other locations, their revenue will not go up, but the level of support required will likely increase. Many vendors allow for this by selling more expensive licenses which are authorized company wide. So you will just need to pay a bit more. The other issue that software vendors consider is the one that users consider, value. Let's face it, like other products, the price is not a function of what it costs to make it unless that cost sets the minumum price. Non-commodity products are sold at a price that reflects the value to the customer. A node locked license has less value than a site license which has less value than a company wide license. Support costs not withstanding, the value here sets the price paid. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70917
"www.amontec.com" <laurent.gauch@DELETE_CAPSamontec.com> wrote in message news:<40E3F58B.5070507@DELETE_CAPSamontec.com>... > My company can do this work very quickly. PCBs - FPGA configuration - > DC/DC. Spartan-II or Spartan-IIE would be great for. > > Do you need onboard DC regulators ? > Which kind connectors? > > Laurent > www.amontec.com Well, the board will be receiving power from another board, so I don't beleive DC regulators will be necessary. I was planning on making connections just using single wires, so whatever type of connectors work best for that would work. What kind of pricing would I be looking at for a custom-made board? Like I said, I am looking for a relatively inexpensive solution. Thanks. Sincerely, Darien A. GothiaArticle: 70918
rickman wrote: > > I just read a press release about "power reduced" Spartan 3s. They > don't give much in the way of numbers, they just say the quiescent power > is reduced by *up to* 66%. The last time I checked the data sheets, > there were no power figures. Anyone know what actuals might be attached > to this value? Just how much quiescent power do these chips suck down? > Numbers on the XC3S400 would be useful. I checked the web site and there are new numbers for the quiescent power. For the XC3S400, Vccint = 35 mA typ, Vcco = 1.5 mA typ and Vccaux = 20 mA typ. Any plans to fill in the max values? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70919
I was observing from the scope that the non-DMA from-device writes were
taking anywhere between 30 and 40 bus clock cycles for the lower dword to
transfer. I would recommend doing something along this line:
host writes to DMA trigger register ==>
device causes DMA transaction ==>
on done device causes interrupt ==>
driver reads doorbell register to check transaction completion size,
etc.
"Mark Schellhorn" <mark@seawaynetworks.com> wrote in message
news:SOAEc.175874$207.1241277@news20.bellglobal.com...
> If anyone can offer help with this (or a pointer to a more suitable forum)
it
> would be greatly appreciated. I am posting here because I know there is
some
> some folks with expertise who frequent this group (and we're using a
Xilinx core
> :)).
>
> We are attempting to perform 64B burst PCI-X DMA write transfers from our
add-in
> card into host memory on a dual Xeon system.
>
> Our linux device driver (kernel 2.24.x/2.26.x) is notified via an
interrupt &
> single dword "doorbell" write that the larger 64B entry is available for
processing.
>
> The order of operation on the PCI-X bus is as follows:
>
> 64B data write --> 4B doorbell write --> interrupt.
>
> Upon receiving the interrupt, the device driver polls the location in
memory
> where the 4B doorbell write is expected to show up. Once he sees the
doorbell
> location written, he reads the 64B data location. PCI ordering should
guarantee
> that the 64B data location is written to system memory before the 4B
doorbell
> write is.
>
> The above writes are performed as Memory Write Block transactions (we have
also
> tried Memory Write transactions), the No Snoop bit is cleared, and the
Relaxed
> Ordering bit is cleared.
>
> We consistently encounter a situation where the device driver correctly
receives
> the interrupt & single dword doorbell write, but the 64B write fails to
appear
> in memory. Instead, the device driver reads a stale 64B block of data
(data from
> the last successful DMA write).
>
> As a debug measure, we had the FPGA on our add-in card perform a readback
> (Memory Read Block) of the 64B entry immediately after writing it. We
obeserved
> that the data read back was stale and matched the stale data that the
device
> driver saw. Eg:
>
> 1) Location 0xABCDEF00 is known to contain stale 64B data
0xAAAA....AAAA.
> 1) FPGA does Memory Write Block 64B 0xBBBB....BBBB at address
0xABCDEF00.
> 2) FPGA does Memory Read Block 64B at address 0xABCDEF00 (Split
esponse).
> 3) Split Completion is returned by bridge with data 0xAAAA....AAAA.
>
> This appears to be a violation of PCI ordering rules. Again, the No Snoop
and
> Relaxed Order bits are cleared for all of these transactions.
>
> The device driver *never* writes to the 64B location, so there should be
no
> possibility of a collision occurring where he writes/flushes stale data
that
> overwrites the incoming DMA write.
>
> This tells me that the location is NOT getting written because, according
to PCI
> ordering rules, the FPGA read *must* push the Memory Write Block into
system
> memory before reading back the location.
>
> We observe this behaviour in dual Xeon systems with both the Intel E7501
chipset
> and the Broadcom Serverworks GC-LE chipset.
>
> We observe this in SMP and single processor configurations.
>
> When bus traffic is light at 133MHz, or whenever the bus is running at
66MHz, we
> do *not* observe this problem. We occasionally observe the problem when
the bus
> is running at 100MHz with heavy traffic. This suggests that we are hitting
a
> narrow timing window at higher bus speeds.
>
> We are suspicious that we might be encountering a cache errata in the
Xeon, and
> are wondering if anyone can confirm this and possibly provide a
workaround?
>
> We've been banging our heads on this for a couple of weeks now.
>
> Mark
Article: 70920In my experience the 'after hours' time I spend on these tools is either because the SW is buggy/poorly documented and I couldn't get the job done during office hours, or I am trying to extend my skills, ultimately reducing my need for support. Heck, the only support available after hours (sometimes during hours too) are these public forums anyway, so what is the vendors cost? Unless of course, the users are finding lots of bugs and pressing for fixes. But hey, this is just one of those unpaid services we users provide. rickman wrote: > tns1 wrote: > >>license_rant_master wrote: >> >>>I am an ASIC engineer who frequently 'takes work home' with me. >> >><snip> >> >>With a standard cable or DSL connection, VNC works pretty well. I don't >>think it could violate any license since it only virtualizes the >>interface, and that part at least, should be fully owned by the user. >>Overzealous license agreements that try to impose what you do with your >>hardware should be slapped down by the courts, but the increasing >>virtualization /globalization blurs the 'site' definition. Interesting >>stuff. >> >>If VNC really does not work for you, there must be a way that your >>vendor can extend/change the license to one or more node locked seats >>(tied to a removable NIC, say). Node locked seats should never be >>restricted by distance from the license server. Rant on dude. We should >>all have the right to use every legitimate seat 24/7, no matter where we >>are. > > > I can tell that this is going to be one of those long threads that have > a loooong life. > > Software companies charge with two principles in mind. One is the cost > of doing busisness. If you buy three licenses for a given location the > vendor can expect an average level of support that they will need to > provide to that site and others like it. If they allow you to use the > same license at other locations, their revenue will not go up, but the > level of support required will likely increase. Many vendors allow for > this by selling more expensive licenses which are authorized company > wide. So you will just need to pay a bit more. > > The other issue that software vendors consider is the one that users > consider, value. Let's face it, like other products, the price is not a > function of what it costs to make it unless that cost sets the minumum > price. Non-commodity products are sold at a price that reflects the > value to the customer. A node locked license has less value than a site > license which has less value than a company wide license. Support costs > not withstanding, the value here sets the price paid. >Article: 70921
The whole is solved by a notebook being the work machine at the expense of reduced performance. But yes, the whole is a bit silly. Rene license_rant_master wrote: > I am an ASIC engineer who frequently 'takes work home' with me. > Recently, I began using ssh to remotely login to our company's > servers to run some Verilog/VHDL simulations. Launching > sims (from the UNIX command line) is fairly easy and painless, > but any kind of interactive (GUI) operations are pitifully > slow over an WAN/internet connection. In the past, I > haven't needed to do much more than check on running jobs, > restart them, then logout. Now, I find the need to do some > interactive debugging work (waveform viewing, code editing, > etc.) > > So I thought, ok, I'll just install Linux at home and check > out a license remotely from the company. The system > administrator told me "NO!" this is forbidden, due to the license > agreements of just about every EDA-tool vendor. According to the > language/legalese of the license-agreement, a license 'seat' > is tied to a physical location called 'site.' > > There are minor differences among the 'site-radius', but the > end-result is the same ... no executing the tool on hardware outside > of the radius: > > Cadence : 1 mile radius within licensed machine-node > (Sysadmin told me this...didn't double-check myself.) > > Synopsys: 5 mile radius within licensed machine-node > (couldn't find the agreement, but found this on Solvnet.) > > Model/Mentor: 800 meter (0.5mi) radius within licensed machine-node > (Download the user's manual for any Modelsim product.) [snip] > /RANT OFF > > Any comments?Article: 70922
rickman wrote: > rickman wrote: > >>I just read a press release about "power reduced" Spartan 3s. They >>don't give much in the way of numbers, they just say the quiescent power >>is reduced by *up to* 66%. The last time I checked the data sheets, >>there were no power figures. Anyone know what actuals might be attached >>to this value? Just how much quiescent power do these chips suck down? >>Numbers on the XC3S400 would be useful. > > > I checked the web site and there are new numbers for the quiescent > power. For the XC3S400, Vccint = 35 mA typ, Vcco = 1.5 mA typ and > Vccaux = 20 mA typ. Are these the 'reduced' values, or the standard devices ? The new Lattice devices also show typicals only, and they too are many 10's of mA. Last time I saw a leading edge MAX, it was hundreds of mA.... Sounds like they may be doing do a 'current bin', just like they do 'speed bins'. It will, of course, mean that the non reduced ones have higher typicals, as all the 'good ones' have been removed :) -jgArticle: 70923
> Hi, I have just began working with FPGA devices and have been trying > to apply them in real-world situations. For my first project I need a > very small, relatively inexpensive "bare-bones" type FPGA board. But > I have been having difficulty finding one. I just need one with the > following features (please tell me if I'm missing anything vital): > > -FPGA device with at least 15,000 usable gates (more would be > preferable). I only need a small number of user IOs, so that > shouldn't be an issue at all. The device doesn't need to be very fast > either, as it will be running only at around 4 MHz. > -clock with only around 4 MHz frequency range... higher isn't a > problem however. > -in-circuit reprogrammable non-volatile memory device for storing the > FPGA's configuration data. > -The most important thing is that it all fits within a 40 mm x 30 mm x > 10 mm volume or less. > I didn't check the specs, but I saw some tiny FPGA boards at www.fpga4fun.com J.Article: 70924
Rene Tschaggelar <none@none.net> writes: > The whole is solved by a notebook being the work machine at > the expense of reduced performance. I don't think his company is too happy about spending multi $100,000 for licenses exclusively to a single users notebook... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
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