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Andres First you have to figure out whether the two 90 MHz clocks really have the same frequency, just unknown phase, or whether there might be a frequency difference, in which case you have to develop a strategy about how to deal with overrun or underrun. Peter Alfke > From: ALuPin@web.de (ALuPin) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 22 Mar 2004 06:35:29 -0800 > Subject: Synchronization of data > > Dear Sir or Madam, > > > I want to synchronize 90MHz data which come from an external > 90MHz clock domain (GMII transceiver device) > to my internal FPGA 90MHz clock. > So I have two clocks with the same frequency > but they are asynchronous to each other. > > What possibilities can be used for synchronization? > > Is the following method possible and useful ? : > http://mitglied.lycos.de/vazquez78/ > > Thank you for your time and help. > > Best regards > > Andrés Vázquez > Guntermann & Drunck > System DevelopmentArticle: 67901
On Sun, 21 Mar 2004 18:56:16 -0800, sree wrote: > Hi, > I am new to FPGA's. I am trying to implement a RISC processor with > some instruction set(arithmetic,logical) on VIRTEX-II FPGA,then I want > to program it using the serial port,for this i want to use c++.is > there any resources or any way i can change GCC compiler to work for > my processor.I also want to try to port linux on this to work as > RTOS,but i believe for this i first need the compiler for my CPU.so, i > need help in finding the resources,tutorials.If there is something you > know please let me know.I thank you in advance. > sreeram koneru > koneru.2@wright.edu This is the wrong newsgroup for this question, try comp.os.linux.development.systems comp.os.linux.development.apps gnu.gcc.help It is possible to make gcc work with a custom instruction set but I expect it's a lot of work and getting it to work well enough to compile Linux may be very difficult (but I'm no expert). If I were you I'd choose a supported instruction set. Your email address is .edu so I assume you are doing this as a learning experience not as a product, if that's the case then you can pick any instruction set that appeals to you. If you want to do this as a product then you are going to have to look at the licensing requirements for each set.Article: 67902
Hi Spyros,
Thats odd that you are not gettings an RCF created in your
atom_netlists directory. When you back annotated, did you select
"Routing" as part of the back annotation? I didn't specify that you
needed to, sorry for the confusion. To get the placement and routing
information into the ESF and RCF you must back annotate first.
1) Unfortunately, the default is to make the regions floating
automatically. This is to make sure that the design fits in
situations where there are multiple back annotated instances of the
same entity.
If you are trying to make a MAKEFILE type script, here is a
suggestion. You can use the -update option in Logiclock_import. What
this does is it tries to preserve the placement of the region (and the
parent region hierarchy) during import.
So imagine that you imported a lower level entity, and you locked it
down, perhaps you even moved it somewhere else on the chip. Now you
want to modify the internal placement of that entity at a lower level
and re-import it. The -update option, basically keeps the top level
(already imported) region as it is, and just removes all of its
contents and updates it with the new contents from the lower level.
If the region was locked, then it will remain locked. Note: It is
important to leave the region name the same.
2) Great.
3) Try backannotating the routing first before you try to export.
That should work.
4) Again, here is what I see:
tcl> set_logiclock -h
---------------------------------------------------------------------------
Usage: set_logiclock [-h | -help] [-long_help] -region <region name>
[-height <height in labs>] [-width <width in labs>] [-origin <chip
location>] [-parent <par
ent region name>] [-reserved <true|false>] [-auto_size <true|false>]
[-soft <true|false>] [-flo
ating <true|false>] [-members_floating <true|false>] [-flip]
-h | -help: Short help
-long_help: Long help with examples and possible return values
-region <region name>: LogicLock region name
-height <height in labs>: LogicLock region height
-width <width in labs>: LogicLock region width
-origin <chip location>: LogicLock region origin
-parent <parent region name>: LogicLock region parent
-reserved <true|false>: Set reserved property
-auto_size <true|false>: Set auto_size property
-soft <true|false>: Set soft property
-floating <true|false>: Set floating property
-members_floating <true|false>: Set members floating property
-flip: Flip (mirror) region right-to-left on the chip
------------
Tcl Package:
------------
Belongs to ::quartus::logiclock package.
------------
Description:
------------
If the region specified by -region_name does not exist,
it will be created with the specified properties.
Otherwise, Quartus will change the properties of the
region specified by -region_name to the values specified
by the arguments. Any properties not included as arguments
will remain unchanged.
---------------------------------------------------------------------------
Perhaps there is something wrong with your installation of Quartus.
I'm not sure.
I will check to see if there is a specific TCL guide that I can point
you to.
I hope this helps.
Przemek Guzy
Altera Corp.
lyberis@isd.gr (Spyros Lyberis) wrote in message news:<ebe66d13.0403182327.4504711b@posting.google.com>...
> Hi Przemek,
>
> Thank you for your answers. I still have some questions on them:
>
>
> > 1) Top level regions are automatically made floating. This is the
> > Quartus default. You are free to lock them down yourself. There is
> > only one situation where the default is to keep the region locked:
> > You need to import the routing information for the lower level modules
> > as well. This can be accomplished like this:
> >
> > logiclock_import -no_pins -do_routing
>
> Okay, but the original problem is that I cannot create the .rcf file
> (see nr. 3 below) to try that.
>
> But even if I do not have an .rcf file, is there any TCL command to
> re-make the region locked? Currently I am parsing the .esf file in the
> script and make a substitution of the text "FLOATING" with "LOCKED".
>
>
> > 2) Quartus has a feature called Virtual Pins. Using the assignment
> > editor you can make Virtual_Pin assignments on any pin which you want
> > Quartus to treat as an internal connection. You should however make
> > sure that the clock pins are NOT made virtual. Timing analysis will
> > not be correct if you make your clock pins virtual. The TCL command
> > to make these assignments is as follows:
> >
> > set_instance_assignment -name VIRTUAL_PIN ON -to some_pin_name
> >
> > Another suggestion is to make ALL the pins virtual, and make the
> > clocks Not-Virtual:
> >
> > set_instance_assignment -name VIRTUAL_PIN ON -to \|
> > set_instance_assignment -name VIRTUAL_PIN OFF -to my_first_clock
> > set_instance_assignment -name VIRTUAL_PIN OFF -to some_other_clock
>
> You are right, I tried that and it has worked.
>
>
> > 3) The -routing option in LogicLock export should create an .RCF file
> > in the atom_netlists subdirectory (or whatever directory you specified
> > for the .ESF file to be output to). The .ESF will contain the
> > placement/region information and the .RCF contains the routing
> > information. When doing a LogicLock_import -do_routing, it is
> > important that the .RCF be placed in the same directory as the .ESF.
>
> This still does nothing for me... Note that I am in QuartusII 3.0 SP2,
> can this be the problem? I'm trying to upgrade to QuartusII 4.0 but our
> local Altera representative is on vacation...
>
>
> > 4) I don't know why your Quartus is not showing you any help
> > information. You should be seeing the following:
> >
> > tcl> logiclock_import -h
> > ---------------------------------------------------------------------------
> >
> > Usage: logiclock_import [-h | -help] [-long_help] [-no_pins]
> > [-no_regions] [-no_nonregion] [-no_create] [-update <region name>]
> > [-do_routing]
> >
> > [...]
>
> Yeah, I have help on logilock_import. I do not have help on the
> following commands of the logiclock package (they display nothing):
>
> - set_logiclock
> - get_logiclock_contents
> - set_logiclock_contents
> - get_logiclock_member_priority
> - set_logiclock_member_priority
> - list_nodes
> - initialize_logiclock
> - uninitialize_logiclock
> - logiclock_delete
>
>
> Maybe my biggest question is the following: is there any official
> Altera document which can be used as a helping guide to people who
> want to develop TCL scripts? I mean that apart from the (well
> written) introductions in the Quartus handbook and some (now
> obsolete) application notes, is there something like a TCL API
> reference guide? Even if the online help is complete for all commands,
> it is very brief when you're trying to do complex scripts...
>
> Thanks a lot,
> Spyros
Article: 67903No need for a dc-dc (switching) converter. Just use a cheap 3-terminal regulator, available from any linear-IC manufacturer. Peter Alfke > From: "vax,3900" <vax3900@yahoo.com> > Organization: Ohio State University > Newsgroups: comp.arch.fpga > Date: Mon, 22 Mar 2004 10:13:33 -0500 > Subject: zener power supply to XC95144XL? > > Hello, > I am using a XC95144XL on a 5V board. I need to supply 3.3V to the > XC95144XL. Do I need a 5V/3.3V DC-DC converter, or a zener with some > resistors and capacitors? I heard that XC consumes wide range of current so > I guess the zener might not do the job. Is there any reference about this > issue? Thank you. > > vax, 3900Article: 67904
The current XCell talks about the Virtex-4. Presumably there will be no Virtex-3. And, sadly, no Virtex-IV. We rather looked forward to the Virtex-MCMLXXIX - is it an FPGA or is it the Pope? Scarcely less off-topic, why do decent clocks always show the 4 o'clock as IIII?Article: 67905
john wrote: > Interresting, but is any one know another 64-bits CPU core in > GNULicense to be able to compare it ??? MMIX - the new Knuth machine? A bit tricky on the FP side. It has an opcode SWYM - Sympathise With Your Machine (dual of the SYNC opcode) - which should be a piece of cake in an FPGA.Article: 67906
hi,
I am doing the IOSTANDARD attribute for my lvds buffer: See the
following:
attribute IOSTANDARD : string;
attribute IOSTANDARD of databuf : label is "LVDS_25";
attribute IOSTANDARD of framebuf : label is "LVDS_25";
Of course, there is syntax error above. Could anyone help me to correct
it?
Thanks
Chris
Article: 67907Hal Murray wrote: > > Nonsense, on two levels. Poorly worded perhaps, but not devoid of meaning. And not bad advice for a new FPGA user trying to steer clear of the most common mistakes. -- Mike TreselerArticle: 67908
Could be ABEL, CUPL, or PALASM: http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH09/CH09.2.htm http://www.ee.upenn.edu/rca/software/abel/abel.primer.html http://www.engr.uky.edu/~melham01/ee481/pals/abel_ref.pdf http://www.rexfisher.com/Downloads/CUPL%20Tutorial.htm ABEL is still supported in the Xilinx CPLD tools. HTH -- Georgi "Lee" <melee5@my-deja.com> wrote in message news:a57ea28d.0403210203.40da6c2@posting.google.com... > Thanks for looking. What I got is some .src files with > only input/output pin declarations (pin number and > variable name) and then logic equations for the output > pins VS input states. This file is representing a 16L8 > PAL supposedly. What I need is to go from here to a PAL > JEDEC file suitable for programming, by what method(s) > please? I'm new at this and would dearly like to know if > anyone can recognize this simple .src format and name any > software that can use it.Article: 67909
Does that mean the delay time is fixed for a particular device and speed? Can we program it with variable values? Thanks,Article: 67910
> This is more comparible to an 8-bit CPU in terms of functionality than > a real 64-bit processor. I don't know of many 64-bit processors that > can only access 16k-words of RAM. There are not enough available pins to connect the whole address bus. If you wish to use the full address bus then replace in the entity section 15 by XLEN and below the instanciation of memmux also 15 by XLEN. The above lines will work only if the package has enough pins.Article: 67911
Man, you're hardcore--soldering wires to balls and wire-wrapping. I hope the savings are worthwhile. -Kevin "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0403220442.1e9d0756@posting.google.com... > interesting - while doing wire wrapping to create a development board > with XCV2000E (BGA FG860) I accidently connected VCCINT to 3.3V supply > - I would guessed to see smoke or at least dead FPGA (the power supply > did deliver full 3.3V to VCCINT), but no! The FPGA was a little warm, > but not hot. After fixing the VCCINT back to 1.8V I did get long time > the famous error > > "DONE DID NOT GO HIGH" > > but after reading the datasheet and pulling PROGRAM to high the > XCV2000E did come fully alive, i.e. it really survived several minutes > of 3.3V on VCCINT. > > Antti Lukats > > PS if i get some time to breathe I will upload the picture of this 2M > Gate development board (my self-costs $49!! ) > > just clarification: I am using a FPGA in BGA package that is removed > from equipment and I am soldering wires directly to BGA pads. > The FG860 is actually really easy to handle, and if I dont need many > IO pins such a wire wrap development board can be made in 3 hours max.Article: 67912
Thanks to all respondants, design is now working OK. I have delayed LOCK_1 to DCM_2, but clocked by the input clock of DCM_1, need to change that, OR, go the non-delayed route as suggested by Austin. It's really great to actually get useful replies so quickly. I had originally discounted XAPP132 as it was for Virtex DLL's, & I couldn't find a decent XAPP for DCMs. Xilinx has so much info, it's hard to find the relevant bit IMO. Once again, many thanks all. Niv.Article: 67913
It is fixed, appropriately for device size and speed. Peter Alfke >From: thangkho <> >Organization: (none) >Newsgroups: comp.arch.fpga >Date: Mon, 22 Mar 2004 10:07:24 -0800 >Subject: Re: Virtex-E IOB programmable delay Does that mean the delay time is fixed for a particular device and speed? Can we program it with variable values? Thanks,Article: 67914
I am constructing a user aurora protocol core based on the PLB SSP1 reference. It utilizes the MGT on a V2P-7. I am having difficulty setting the "INST" parameters in the ucf file. I do not know the path to the MGT parameters. I've tried many locations... a subset of the attempts is: INST plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i LOC=GT_X0Y1; INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i ALIGN_COMMA_MSB = ...; INST "plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i" CHAN_BOND_MODE = ...; INST system/plb_gigacore_1/auroracore_i/aurora_lane_0_i CHAN_BOND_ONE_SHOT = ...; INST system/plb_gigacore_1/plb_gigacore_1/auroracore_i/aurora_lane_0_i CHAN_BOND_SEQ_1_1 = ...; My core is instantiated in the EDK as plb_gigacore_1. the path to the aurora core in the VHDL files is as follows: plb_core_ssp1_ref.vhd defines USER_LOGIC_I : user_logic user_logic.vhd defines auroracore_i : auroracore auroracore.vhd defines lane_0_mgt_i : GT_CUSTOM and global_logic_i : GLOBAL_LOGIC The error I receive is always: ERROR:NgdBuild:753 - Line 1074 in 'system.ucf': Could not find instance(s) '<INSERT ATTEMPTED PATH HERE>/auroracore_i/aurora_lane_0_i' in the design. To suppress this error specify the correct instance name or remove the constraint.Article: 67915
Marc Randolph wrote: > Nahum Barnea wrote: > >> Hi. >> How can I run Xilinx map with -timing option through the ise gui ? >> Currently I am using command line, but I wish to use the ise gui. >> >> ThankX, >> NAHUM > > > Howdy Nahum, > > If it doesn't show up in Map -> Properties, you need to turn on > advanced mode... which is under Edit -> Preferences -> Processes. > Obvious, ain't it? :-) > > Have fun, > > Marc > > P.S. If you are an experienced command line user, you may find > yourself disappointed with the flexibility that the GUI provides. The > check boxes and help screens are nice, but if any of your input files > (either .ucf or your real source) change, even if you are just adding > a comment, the gui will try to re-run everything - not a big deal if > your builds are 5 minutes, but some of our designs take something on > the order of half a workday to run through (on a 3.2 GHz machine). This is done to keep everything in your project in sync, but there is a way to avoid the automatic recompilation. Most processes and report files have a local menu pick called "Open Without Updating". This will immediately open the result file or tool (like FPGA Editor) without "pulling" the current design though to that point. thanks, david.Article: 67916
Hi, I want to create a large number of PLB or OPB GPIO nets to connect to many different parts of my own custom logic(on the order of 1000 nets). Does one type of bus do a better job at not using up routing resources? Is one type of bus simplier to use? Is there any limit on the number of GPIO pins I can use? Any help is much appreciated Thanks MattArticle: 67917
HI, I am designing a PCI card which will have a Stratix FPGA as the PCI controller. The Stratix will have a PCI-X core with PCI backwards compatibility. Now from my readings, PCI-X is 3.3V only signalling, whereas today the majority of PC motherboards (pre PCI 2.3 spec) are 5V signalling. For obvious reasons I will have to make my PCI card a universal card (keyed to both 5V and 3V3) in order to accept present day common motherboards (PCI 5V) and future motherboards (PCI-X/PCI 3V3). Is there anything special I need to consider? Does anybody know where I can find info on making my universal card. Any good books or App notes. Thanks, NevenArticle: 67918
Nevin, http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11904 describes 3.3 and 5V solutions for Virtex E and Virtex II. http://www.xilinx.com/xapp/xapp646.pdf describes the generic solution for Virtex II and II Pro (and Pro-X and S3). AustinArticle: 67919
Synplicity has created a "lite" version of the Identify 1.3.1 product and has made this software available free to the public. This version supports the Xilinx Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, and Spartan-3 devices. The full-function Identify software additionally supports Actel proASIC and Altera APEX and Stratix devices. The Identify RTL Debugger provides an Engineer with the ability to perform logic analyzer like debugging inside of their FPGA while using a simulator like interface. Using the Identify Instrumentor application, an Engineer views their HDL source code and selects the signals that he/she wishes to use for triggering and for viewing. This creates an "instrumented" version of the source code (instrumented code = original source + logic analyzer). The instrumented source code is then taken through logic synthesis and place and route. After the design has been downloaded into the FPGA, the Identify Debugger application is used to communicate with the logic analyzer that has been inserted into the FPGA. Communication occurs through the same JTAG interface that was used to download the design into the FPGA. Using the Identify Debugger application the Engineer specifies a trigger condition and "arms" the Logic Analyzer. After the trigger condition occurs, the signal values can be viewed on a waveform viewer, or the state of the signals can be viewed annotated on the original HDL source code. The lite version of Identify restricts the number of RTL signals that can be used for triggering and viewing to 16. This is a significant limitation compared to the full product, which has no such software limitations. But even with these limitations, it should provide sufficient functionality to allow a user to easily perform real debugging. It may not be much help for viewing wide data paths, but it will be useful for control logic debug, small-medium sized state machines, etc. To download the free trial version of Identify lite, please go to the following web page - http://www.synplicity.com/downloads/identifylite/index.html Enjoy, Jim Robinson Director Corporate Applications Engineering FPGA ProductsArticle: 67920
melee5@my-deja.com (Lee) wrote in message news:<a57ea28d.0403210203.40da6c2@posting.google.com>... > Thanks for looking. What I got is some .src files with > only input/output pin declarations (pin number and > variable name) and then logic equations for the output > pins VS input states. This file is representing a 16L8 > PAL supposedly. What I need is to go from here to a PAL > JEDEC file suitable for programming, by what method(s) > please? I'm new at this and would dearly like to know if > anyone can recognize this simple .src format and name any > software that can use it. Sounds like it may be PALASM. You could probably convert it to ABEL with little work, or try to dig up an old copy of PALASM somewhere.Article: 67921
"Martin Maurer" <capiman@clibb.de> wrote in message news:<c3khkj$nqm$03$1@news.t-online.com>... ABEL is not Verilog or VHDL. Unspecified outputs of a state machine in any state are assumed to be zero, not latched to the current state, so your assumption "should not touch TEST_OUT_x" doesn't hold for ABEL. You need to specify the output anywhere it needs to be 1. Where the output needs to hold its previous value you need to specify that, too. Where your state machine has asynchronous outputs, you would need to explicitly create a register to hold the previous state of TEST_OUT_1 through TEST_OUT_3 and assign these outputs to the registered value in states where you need to hold the previous state but don't a priory know what that state is. Hope this helps. My best advice is to use Verilog or VHDL for state machine designs. > Again (continued), sending was too early, sorry: > > Hello, > > i have a problem with a reset condition of a state machine i have written in > ABEL. > Source is like the following (cutted out the relevant parts): > > status state_register; > > wst, ls1, ls2, ls3, ls4... state; // line is shortened, much more > states ! > > xilinx property 'Initialstate status wst'; > > status.clk = MY_CLK; > > STATE_DIAGRAM status > > STATE wst: > TEST_OUT_1 = 1; > TEST_OUT_2 = 0; > TEST_OUT_3 = 0; > IF !MY_CMD THEN ls1 ELSE wst; > > STATE ls1: > TEST_OUT_1 = 0; > TEST_OUT_2 = 1; > TEST_OUT_3 = 0; > goto ls2; > > STATE ls2: > TEST_OUT_1 = 0; > TEST_OUT_2 = 0; > TEST_OUT_3 = 1; > goto ls3; > > STATE ls3: > > goto ls4; > > and so on. Last state jumps back to wst. No other conditions, all like ls3. > > So for every state i reach i think i should see one of my testoutputs at > high level, the other two on low level. It sometimes works fine, but often i > get a low level on all of the three line. In my opinion i should not reach > this condition, because in every state one of these output are set and ls3 > and upwards, should not touch TEST_OUT_x, so level of ls2 is at the outputs > ? Conclusion on my side was, that the state machine is not running. I tried > to manually reset the state machine with status.ar = !RESET, but still no > success. I have redirected a input PIN to an output PIN, feeding some clock > to the input and output is toggling. So i think the chip at all is running, > but my state machine not. > > Can someone help me ? > > Regards, > > MartinArticle: 67922
> What kind of ISP PROM do you use? and is the name of > the programmer you use? I used a Xilinx ISP PROM, and you program it with a JTAG cable. You can find information about these on the Xilinx website. > How much did it all cost for you? On a per board basis? About $150, I think... But I could not make just one, there was a minimum order from the PCB fabrication company. I actually made 12, sold most, and kept the rest for myself. EricArticle: 67923
Antti, Is there a limit to the number of GPIO instances I can create? Thanks Matt >if you really want to use GPIO then the PLB vs OPB doesnt really make a >difference here >single GPIO instane can have 128 outputs and 64 inputs if routed into ISE >toplevel >you can use _O and _T as separate output ports. >but it would really be better to make your own peripheral its not >complicated >AnttiArticle: 67924
We designed a board using the JTAG and passive serial download procedures in AN250 a while back. In Sept of 2003 Altera released their "Configuration Handbook" in which now apparently the JTAG lines have to have pull ups and downs on them (though the down is incorrectly stated as 10K should be 1K apparently). It would seem, if i read between the lines, that the JTAG pullup on the TCK pin within the device can cause some sort of fault The fix for this is to pull the TCK pin low with 1K. If this is so has anyone seen an errata they can point me to? Has anyone seen strange loading faults where CONF_DONE goes high BUT the FPGA is not operating properly? It happens to us only every few thousand loads. I am keen to resolve this in some way.
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