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I wrote a sample VC++ program to download Xilinx FPGAs via slave serial mode using JTAG cable (parallel cable III). I have posted it to my website. Its compiled as a windows console application. I used inpout32.dll library to talk to parallel port of the PC. The program works on my win2K laptop. Sumit ----- http://www.c-nit.netArticle: 67776
Hi Andrés, your files, where you have included your .hex files don't use absolute path names to the directory where the .hex files is stored. So ModelSim can't find the .hex files. You can edit your vhdl files and change the path information or you can copy the .hex file directly into your ModelSim directory. Marc ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0403180755.352e91a8@posting.google.com>... > Dear Sir or Madam, > > I want to simulate a VHDL design. It includes a RAM structure > which I initialize with an hexadecimal Initializations-File > in the MegaWizardPlugInManager in QuartusII version4.0 . > > But when simulating in Modelsim there is the following problem: > When I compile the files "CAM_test.vhd" and the testbench > "tb_CAM_test.vhd", and then start simulation I get the error message > which is shown at > > http://mitglied.lycos.de/vazquez78 > > What does go wrong? > > I would be very thankful if you had the time to have a look at it. > > > Best regards > Andrés Vázquez > Guntermann & Drunck > System DevelopmentArticle: 67777
> # ... and you have to close and open the project at this point,
> # otherwise the fitter crashes(!) with a weird error:
> #
> # > Internal Error: Sub-system: XRU, File: xru_hdb.cpp, Line: 1560
> # > m_got_esf_writelock > 0
> #
> # I tried with export_assignments, but didn't work...
Spyros,
Are you running this script from the Quartus II GUI (Tcl Console) or
from the command-line executable (quartus_cdb in this case) ? From the
fact that you have ESF files, I am guessing you are using V3.0, is
that correct ?
I don't really use the GUI for Tcl-ing, but I have never seen a case
where you need to close the project and re-open it to avoid an
Internal Error.
From quartus_cdb, you should be able to simple
package require ::quartus::flow
project_open bottom
# No need to run map first
set_instance_assignment -to "pin_name" -name virtual_pin on
execute_module -tool map
set_location_assignment -to "pin_name" LAB_X1_Y1
execute_module -tool fit
project_close
or
package require ::quartus::flow
project_open bottom
# No need to run map first
set_instance_assignment -to "pin_name" -name virtual_pin on
set_location_assignment -to "pin_name" LAB_X1_Y1
execute_module -tool map
execute_module -tool fit
project_close
or just
package require ::quartus::flow
project_open bottom
# No need to run map first
set_instance_assignment -to "pin_name" -name virtual_pin on
set_location_assignment -to "pin_name" LAB_X1_Y1
execute_flow -compile
project_close
In terms of where to get help, I recommend that you use "quartus_sh
--qhelp" from the command-line. --qhelp will execute a Tk based GUI
that allows you to browse through the help (both for Tcl commands and
for the command-line executables).
You can also do:
quartus_cdb --tcl_eval help -cmd <command>
or using the Tcl shell:
quartus_cdb -s
tcl> help -cmd <command>
tcl> <command> -long_help
tcl> <command> -h
>
> catch {puts [exec printf ",s/FLOATING/LOCKED/g\nwq\n" | ed top.esf]} dummy
>
This is clever. You can also use the ::quartus::project package to
change the assignments.
Happy Scripting,
-David Karchmer
Altera Corp.
Article: 67778Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote: > In the V2pro, Wut is the main difference between the plb and opb? > I know the plb is faster but if I have a limited number of IOs between my > processor and elsewhere is there good reasons to use the opb? OPB Slave components are much easier to write. Plus, you can not only use them with a PowerPC in a Virtex-II Pro but also in a system with a MicroBlaze, without having to change anything. For most applications, OPB should be sufficient. But when performance is a concern (like when you're connecting high-speed memories and such), the PLB is obviously superior. Another downside is that to use the OPB in a PowerPC-based system you need an additional PLB-to-OPB-bridge, which of course uses up some logik ressources. So it all depends on what you want to do with it. cu, SeanArticle: 67779
In article <MPG.1ab8fec737ed13f29896f2@127.0.0.1>, thomas.nospam@gmx.net says... > Hi Klaus, > > In comp.arch.fpga, Klaus Falser said... > > We are using LVDS together with a low capacitance cable of 10 m > > at 50 MHz clock, and my impression is that it is on it's limit. It is sensitive > > to disturbances and signal quality depends strongly on quality of the cable. > > > > If you really want to do it, do not forget to feed the GND signal too through > > the cable, since the common mode range of the differential receivers is not > > large enough for dealing with differences between the ground levels of > > transmitter and receiver. > > > > I seem to remember that somewhere on the National Semiconductor web pages there is > > a graph about data rates and covered distances. > > > > Convince your boss to use an optical link, you will have only advantages! They are not > > so complicated as it seems. > > Thanks for your help. I have already found the graph before and so I am > a little confused about your experience. On > http://www.maxim-ic.com/appnotes.cfm/appnote_number/1856/ln/en there is > table3 and figure7 which show the relation between cable lengths and > transmission rates. I found a reliable transmission over 60 ft (20 m) at > data rates of about 528 MBit. So your 10 m @ 50 MBit seem to be very > low... Factor 10 should be possible? > > Concerning the optical solution. What do we need for such a thing and > what will it cost? Do you have any experience on this topic? > > Thanks for your help, > > Thomas > > Probabely we did it a little bit too simple. We are using 2 pair of lines, one carrying the clock and the other carrying the signals. When I designed my data link, this nice serializer/deserializer components as this Maxim chip were not available yet. Additionally, we are not using CAT-5 cables, so they may make an inprovement too. For an optical link you need a 8B/10B serializer (or the Maxim chip you were looking at) and feed the output to an optical transmitter (Agilent for example). There are so many, it is probabely best to speek with a FAE to choose the right housing and the right connector. Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 67780
Gupta, Are you willing to release the source code for sasm.exe? Best Regards, Kelvin Sumit Gupta <do_not_reply_to_this_addr@yahoo.com> wrote in message news:4ru6c.26051$nH2.4810@newssvr29.news.prodigy.com... > I wrote a sample VC++ program to download Xilinx FPGAs via slave serial mode > using JTAG cable (parallel cable III). I have posted it to my website. Its > compiled as a windows console application. I used inpout32.dll library to > talk to parallel port of the PC. The program works on my win2K laptop. > > Sumit > ----- > http://www.c-nit.net > >Article: 67781
Hi Przemek, Thank you for your answers. I still have some questions on them: > 1) Top level regions are automatically made floating. This is the > Quartus default. You are free to lock them down yourself. There is > only one situation where the default is to keep the region locked: > You need to import the routing information for the lower level modules > as well. This can be accomplished like this: > > logiclock_import -no_pins -do_routing Okay, but the original problem is that I cannot create the .rcf file (see nr. 3 below) to try that. But even if I do not have an .rcf file, is there any TCL command to re-make the region locked? Currently I am parsing the .esf file in the script and make a substitution of the text "FLOATING" with "LOCKED". > 2) Quartus has a feature called Virtual Pins. Using the assignment > editor you can make Virtual_Pin assignments on any pin which you want > Quartus to treat as an internal connection. You should however make > sure that the clock pins are NOT made virtual. Timing analysis will > not be correct if you make your clock pins virtual. The TCL command > to make these assignments is as follows: > > set_instance_assignment -name VIRTUAL_PIN ON -to some_pin_name > > Another suggestion is to make ALL the pins virtual, and make the > clocks Not-Virtual: > > set_instance_assignment -name VIRTUAL_PIN ON -to \| > set_instance_assignment -name VIRTUAL_PIN OFF -to my_first_clock > set_instance_assignment -name VIRTUAL_PIN OFF -to some_other_clock You are right, I tried that and it has worked. > 3) The -routing option in LogicLock export should create an .RCF file > in the atom_netlists subdirectory (or whatever directory you specified > for the .ESF file to be output to). The .ESF will contain the > placement/region information and the .RCF contains the routing > information. When doing a LogicLock_import -do_routing, it is > important that the .RCF be placed in the same directory as the .ESF. This still does nothing for me... Note that I am in QuartusII 3.0 SP2, can this be the problem? I'm trying to upgrade to QuartusII 4.0 but our local Altera representative is on vacation... > 4) I don't know why your Quartus is not showing you any help > information. You should be seeing the following: > > tcl> logiclock_import -h > --------------------------------------------------------------------------- > > Usage: logiclock_import [-h | -help] [-long_help] [-no_pins] > [-no_regions] [-no_nonregion] [-no_create] [-update <region name>] > [-do_routing] > > [...] Yeah, I have help on logilock_import. I do not have help on the following commands of the logiclock package (they display nothing): - set_logiclock - get_logiclock_contents - set_logiclock_contents - get_logiclock_member_priority - set_logiclock_member_priority - list_nodes - initialize_logiclock - uninitialize_logiclock - logiclock_delete Maybe my biggest question is the following: is there any official Altera document which can be used as a helping guide to people who want to develop TCL scripts? I mean that apart from the (well written) introductions in the Quartus handbook and some (now obsolete) application notes, is there something like a TCL API reference guide? Even if the online help is complete for all commands, it is very brief when you're trying to do complex scripts... Thanks a lot, SpyrosArticle: 67782
Klaus Falser wrote: > > Probabely we did it a little bit too simple. > We are using 2 pair of lines, one carrying the clock and the other > carrying the signals. When I designed my data link, this nice > serializer/deserializer components as this Maxim chip were not > available yet. I do not know the Maxim chip, but made experiments with the similar, but probably older National Semiconductor DS92LV1021 and DS92LV1210 pair, later on with the DS92LV1212 receiver. What we learned from this that the 1:10 bit scheme w/o separate clock line is very sensitive on transmitter clock jitter! In some setups it could not find synchronization at all. We had much better results with the 1:7 coded Channel Link, that forwards the clock line too. This was more robust. Janos Ero CERN Div. EPArticle: 67783
"Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message news:5c4d983.0403181332.15d66f8e@posting.google.com... > Hi David, > > When I want to see all the components in an SOPC system and their base > addresses, I use a script that runs this: > > find . -name "*.ptf" | xargs grep -E > "MODULE[^_]|((SLAVE|MASTER)[^A-Z])|[^_]Base|Is_En|MASTERED" > > This makes a nice printout of every module, its base address(es), > whether it's enabled, and who is mastering it, which is pretty much > all the information the GUI will give you. You can run it from the > Nios SDK shell. > > -- Pete > That's a fine idea. It's not quite as convenient as a "print" button on the SOPC gui (perhaps something for future versions?), but it gets me the information I need, and can be easily fiddled to change the information shown. > > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:<c3c41g$al0$1@news.netpower.no>... > > Is there any way to get a printout from Altera's SOPC Builder, showing the > > components around an embedded processor? It would be nice to have something > > better than using a screen-capture program.Article: 67784
ok, I would like to make my own PCI board (a stand-alone PCI card which I can insert in an computer with a free PCI slot). Nothing fancy just a board that could send out I/O data or what ever. For this task I've heard that FPGA would be a good choice. I don't know how to explain it better but if I've missed something, let me know. Thanks! //SPike "rickman" <spamgoeshere4@yahoo.com> skrev i meddelandet news:405A4A18.5555C689@yahoo.com... > Spike wrote: > > > > I can't say I know enough about FPGA processors to choose a good one, that's > > mainly why asked this question. I was hoping that you could give me some > > advices... > > That will require that you explain in detail what you want to do with > it. And be prepared for a lot of advice on what you want to do as well > as how to do it... ;) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67785
> Also use the following library: > library UNISIM; > use unisim.vcomponents.all; > search for ROC at Xilinx website, you'll find lots of info there. Thank you for the idea. But I'm missing something: UNISIM is post-synthesis library. However, functional and post-synthesis simulations don't require long reset. This problem is observed only in timing simulation.Article: 67786
nospaambrad1@tinyboot.com (Brad Eckert) wrote in message news:<7d4cc56.0403170952.6724372d@posting.google.com>...
> I know this subject has been kicked around a lot here, but here we go
> again.
>
> Where can one get a small quantity of XC3S400s? I already have some on
> indefinite back order at Avnet. Maybe there is another source?
>
> Reminds me of John Cleese in the cheese shop:
> "Do you in fact have _any_ Spartan IIIs?"
> "Yes."
> "Really?"
> "No."
I really got a good start of the day today,
by installing ISE 6.2 on the welcome screen it says:
"Shipping Spartan 3 since March 2003"
ROTFL!
Xilinx way to Go! you made my day today!
But I would rather see the Spartan 3 samples on my desk!
Well good laugh is also something to be thankful :)
Antti
PS Xilinx: really it is isnt funny anymore, I have a product
that is halfway to go the PCB fab and it has a Spartan on it,
but if the Spartan 3 doesnt come available I will have to replace
it with Cyclone. Just cant wait forever. It is either available
or it is not. Cyclone is directly orderable, S3 is not.
And the Xilinx distributors are sending out warning emails
about delays in Spartan IIE, and Digikey has no more real
stock on Spartan IIE so whats happening ??
Article: 67787In Altera Quartus compilation report of Stratix device, it shows the usage of logic cells, registers, memory bits, DSP elements, and etc. From Stratix device documentation, I read about logic cells, memory bits. ... in Stratix architecture except the registers. Just saw some input/output register in the DSP blocks. Can somebody explain to me where is the registers showed by the compilation report in Stratix architecture?Article: 67788
Hi all,
So many Books and articles on Web told me to Avoid Infer
latches in design, But Thay did't give the Proper reason behind this
and i did't convince. So can anybody give me the Short and Sweet
answer about my Question "why it is recommended to avoid latches in
Digital Designs?"
Thanks for any Reply.
Best Regards
Arvind Singh Tomar.
Article: 67789
Hi David,
> Are you running this script from the Quartus II GUI (Tcl Console) or
> from the command-line executable (quartus_cdb in this case) ? From the
> fact that you have ESF files, I am guessing you are using V3.0, is
> that correct ?
From the quartus_cdb. Correct about the version, it's V3.0 Service pack
2 for Linux.
> I don't really use the GUI for Tcl-ing, but I have never seen a case
> where you need to close the project and re-open it to avoid an
> Internal Error.
That's the only solution I found. If I don't close & open the project,
when the script reaches the "initialize_logiclock" command it crashes
with:
Internal Error: Sub-system: XRU, File: xru_hdb.cpp, Line: 1560
m_got_esf_writelock > 0
Exiting...
The problem has to do with the virtual pin assignments and the logiclock
initialization, since each of them works fine on its own...
> From quartus_cdb, you should be able to simple
>
> package require ::quartus::flow
> project_open bottom
> # No need to run map first
> set_instance_assignment -to "pin_name" -name virtual_pin on
> execute_module -tool map
> set_location_assignment -to "pin_name" LAB_X1_Y1
> execute_module -tool fit
> project_close
>
> or
>
> package require ::quartus::flow
> project_open bottom
> # No need to run map first
> set_instance_assignment -to "pin_name" -name virtual_pin on
> set_location_assignment -to "pin_name" LAB_X1_Y1
> execute_module -tool map
> execute_module -tool fit
> project_close
>
> or just
>
> package require ::quartus::flow
> project_open bottom
> # No need to run map first
> set_instance_assignment -to "pin_name" -name virtual_pin on
> set_location_assignment -to "pin_name" LAB_X1_Y1
> execute_flow -compile
> project_close
All of these work fine, you are right. I will remove the second
mapping, it is not necessary.
> In terms of where to get help, I recommend that you use "quartus_sh
> --qhelp" from the command-line. --qhelp will execute a Tk based GUI
> that allows you to browse through the help (both for Tcl commands and
> for the command-line executables).
>
> You can also do:
>
> quartus_cdb --tcl_eval help -cmd <command>
>
> or using the Tcl shell:
>
> quartus_cdb -s
> tcl> help -cmd <command>
> tcl> <command> -long_help
> tcl> <command> -h
Yes, but the problem is that there are no help files for some commands,
so neither of these options works for them (see the other subthread, in
answer to Przemek), e.g. the set_logiclock command.
> >
> > catch {puts [exec printf ",s/FLOATING/LOCKED/g\nwq\n" | ed top.esf]} dummy
> >
>
> This is clever. You can also use the ::quartus::project package to
> change the assignments.
This will be interesting. How exactly? Using a set_global_assignment? This
information is stored hierarchically into the .esf file, so somehow I will
need to specify the LOGICLOCK_REGION for each assignment...
Thanks for the time,
Spyros
Article: 67790damc4@gmx.de (Marc) wrote in message news:<cf0ec8fc.0403182242.791f59a3@posting.google.com>... > Hi Andrés, > > your files, where you have included your .hex files don't use absolute > path names to the directory where the .hex files is stored. So > ModelSim can't find the .hex files. > You can edit your vhdl files and change the path information or you > can copy the .hex file directly into your ModelSim directory. > > Marc > > Hi Marc, thank you for your help. Now it works! :O) Best regards AndrésArticle: 67791
Antti Lukats <antti@case2000.com> wrote: : PS Xilinx: really it is isnt funny anymore, I have a product : that is halfway to go the PCB fab and it has a Spartan on it, : but if the Spartan 3 doesnt come available I will have to replace : it with Cyclone. Just cant wait forever. It is either available : or it is not. Cyclone is directly orderable, S3 is not. : And the Xilinx distributors are sending out warning emails : about delays in Spartan IIE, and Digikey has no more real : stock on Spartan IIE so whats happening ?? Also the availability of Cyclone in a TQ240 package ( with nearly 30 available pins more than the XXTQ208) may influence some design decisions.... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 67792
> Hi all, > So many Books and articles on Web told me to Avoid Infer > latches in design, But Thay did't give the Proper reason behind this > and i did't convince. So can anybody give me the Short and Sweet > answer about my Question "why it is recommended to avoid latches in > Digital Designs?" > > Thanks for any Reply. > > Best Regards > Arvind Singh Tomar. Well, you just can't say that latches are bad or good. It depends on what you are doing. It's a general rule to avoid latches as much as possible because in most cases they are not needed and from timing perspective you can't regard latches to be the same as flipflops. A latch will change if any of the inputs changes, the flipflop will only change on a edge of a clock. Quite a difference. In a asynchronous assignment: if en = 1 then data_out <= data_in; end if; This will infer a latch. The latch will slow down this part of the system and it's relativily large. To avoid a latch be sure that the signal will get a value in every possible solution of the if or case statement: if en = 1 then data_out <= data_in; else data_out <= 0; end if; Now it is simply a demux. If data_in is for instance a tri-state driven signal and the en signal indicates when data_in is valid than a latch is nice to get rid of the tri-state and thus protect the internal logic from (unwanted) unknown behaviour. Now in the first example if data_out propagates to other logic and you still will use latches in stead of flipflops you have no control on when the final data will change. Ending up in rase condintions, spikes and other nasty features of digital design. I always regard a latch the same as a mux, OR, AND, switch,... And I always try to use as simple components as possible. Hence it's just in very rare occasions that I need a latch. hope this clears up a bit, JanArticle: 67793
Kim Enkovaara <kim.enkovaara@tellabs.com> wrote: > I have done some comparisons between 900M UltraIII and 2.5-2.8G P4 > Xeons. And the Pentium chips are about 3 times faster almost in all > cases (multigigabyte gate level simulations, RTL simulations, > synthesis, STA etc.) Only reason to use Sun is the need of bigger > than ~3G processes. Xeons seem to be a bit faster than normal P4 Desktops. What kind of memory do you use? > I don't see very bright future for Sun if they try to live with > Ultra processors. They are just incredibly slow. Indeed. But speed isn't the only thing. We switched because 5 (good) PCs are about the same price than one Sun. On the other side we're still using Suns as licenseserver because of the better reliabillity. bye ThomasArticle: 67794
Hi All, I have to develop a big FPGA core, organized like in the figure below. There is a big synchronous system working with the 40MHz clock. However there is also a subsystem which uses the big combinational network with propagation time ca. 75 ns. (It is almost impossible to assure efficient pipelining in this network :-( ). It is not a problem because the Reg.1 and Reg.2 register are enabled only every fourth clock pulse, so I have 100ns to propagate the data through the Comb.1 subsystem. However the problem is that the synthesis tools do complain about the time constraints (as I declare the clock frequency of 40 MHz for the whole system), and I need to use clock constraints to verify correctness of the whole design... Is it possible to inform the synthesis tool that the part of my system will be effectively clocked with four times lower frequency? How to do it? The design is to be done in VHDL (probably MG Precision), and additionally it has to portable between Altera, Xilinx and Actel devices. Please send me any suggestions how to solve it... Fig. 1: ______________________________________________ |Synchronous system working with CLK clock | | | | _______ _____________________ ______ | | | | | Comb.1 | | | | | | Reg.1 | | Very slow | |Reg.2 | | | | |==| combinational |=| | | | | | | network | | | | | | | | | | | | | |_______| | | |______| | | |_____________________| | | Reg.1 , Reg.2 enabled every fourth | | clock pulse | | Rest of the system - full speed | |______________________________________________| -- Thank you in advance, Regards, Wojtek Zabolotny wzab@ise.pw.edu.pl, wojciech.zabolotny@cern.chArticle: 67795
Hi, > I have to develop a big FPGA core, organized like in the figure below. > There is a big synchronous system working with the 40MHz clock. > However there is also a subsystem which uses the big combinational > network with propagation time ca. 75 ns. (It is almost impossible > to assure efficient pipelining in this network :-( ). > It is not a problem because the Reg.1 and Reg.2 register are > enabled only every fourth clock pulse, so I have 100ns to propagate > the data through the Comb.1 subsystem. What you're looking for a multi-cycle timing constraint. I know that the Quartus timing analyzer supports these constraints, and I checked Synplicity's web site quickly and found reference to it in a Tcl scripting example. I imagine other vendors have support for this too. You would want to indicate that all transfers between reg1 and reg2 have 4 cycles to complete. Regards, Paul Leventis Altera Corp.Article: 67796
Hi, did anyone receive a Spartan-3 DSL-KIT from Memec yet? JanArticle: 67797
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<405a41d9$0$31702$fa0fcedb@lovejoy.zen.co.uk>... > > What package do you need? > PQ208Article: 67798
Thanks Bob, I'll be working with some parts provided by Memec, I'll let you know how much current each pin sinks as soon as I finish the board. I was a bit concerned since I am designing a multichannel system, I need to implement data and address buses with 32 Spartan-3(400). For the data bus there is no problem since while one FPGA provides the data at the bus, the others are in high impedance; however, the adress bus has to be listened by every FPGA (5 pins), if the current that each pin sinks is in micro-amps levels even a normal LVTTL source can provide enough current for all FPGAs (I was thinking to use a CPLD to provide the address bus); nevertheless, if the current is more than that I have other options that involve more components in my board. Another option is to provide a CS signal for each FPGA, then just one listener per source pin is required with 32 tracks more. What do you think?, thanks again for your help SergioArticle: 67799
arvind wrote: > > Hi all, > So many Books and articles on Web told me to Avoid Infer > latches in design, But Thay did't give the Proper reason behind this > and i did't convince. So can anybody give me the Short and Sweet > answer about my Question "why it is recommended to avoid latches in > Digital Designs?" > > Thanks for any Reply. I think you misunderstood. It is not *bad* to infer latches in HDL. It is possible, in fact *easy* to infer latches where they were not *intended*. The authors are properly warning you about HDL that you *think* does what you want, but actually will do something different because you did not completely tell it what you wanted. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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