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Hi Spyros, I haven't done much Tcl scripting of LogicLock regions yet, so I can't help you there. I plan on converting my regions to Tcl-generated in the near future so I bet I'll run into the same issues as you have. As for bottom-level design using physical pins, you can prevent this by enabling the Virtual Pin option for these I/Os in the Assignment Editor. You will see the I/Os mapped into LEs in the Floorplan Editor after the next compile. -- Pete lyberis@isd.gr (Spyros Lyberis) wrote in message news:<ebe66d13.0403160257.14cb334e@posting.google.com>... > I am in the process of building a very large and demanding system on > the Altera Stratix EP1S60 device. It will require most of the memory > resources and has some very tricky parts for timing, since it will > interface a DDR SDRAM at 167 MHz (using the Altera IP for this > specific job). The custom design will also have some parts on 167 MHz > and some others on multiple clock domains. > > To avoid huge compilation times, plus the fact that place & route > tools become less efficient when dealing with big designs, I want to > use the Logiclock approach. My flow is running on Linux machines and > since many developers will be involved I want to automate the > procedure by providing them with TCL scripts. I am using Quartus II > 3.0 service pack 2 (trying to get Quartus 4.0 but not succeeded yet). > > My idea is to make a floorplanning on the FPGA by hand (say dividing > it in around 10 big blocks), fixing these logiclock regions manually > and then letting each developer do his own block. If the blocks are > too big to handle, each developer may repeat this process (specifying > his own regions inside his big region). > > So I guess I have two script requirements: > > - A "bottom" TCL script which defines a LOCKED region, compiles > the design and back-annotates all info (locations, routing, etc) > > - A "top" TCL script which reads all the "bottom" regions plus > back-annotated information and simply routes the top-level > connections. > > I have proceeded in my own, and I am listing the current version of my > two scripts below. It seems I have the following problems: > > - When the regions are imported by the top script, they lose their > LOCKED state and become FLOATING. The fitter puts the regions > wherever it wants, although you can still see their original > assignment. > > - Each botttom design is compiled as a stand-alone project. Is there > any way I can convince Quartus that its I/Os are NOT chip pins? > Now it considers them as I/O pins, and does a less efficient > time-driven fit. > > - I cannot store routing information with the bottom script. The > "-routing" option does nothing on logiclock_export > > - Most commands in the logiclock package do not have help in the > TCL modes! Trying for example "set_logiclock -h" returns nothing! > I have figured out most of the options for the scripts below by > googling and... guessing! Is there any official source like a TCL > commands manual? Even the TCL chapter of the 810-pages new Quartus > II 4.0 manual does not say anything on commands and their options... > In the Altera website I have found a simple skeleton for importing > logiclock regions, but there is no skeleton that _exports_ any > logiclock region. > > My two scripts are below. I am using them with "quartus_cdb -t > <script>". Your suggestions/comments/tributes will be greatly > appreciated. > > Thanks you all in advance for reading so far... > > > ================================================================================ > == BOTTOM SCRIPT > ================================================================================ > > package require ::quartus::project > package require ::quartus::logiclock > package require ::quartus::backannotate > package require ::quartus::flow > > project_new "bottom" > > set_global_assignment -name "VHDL_FILE" "bottom.vhd" > set_global_assignment -name "COMPILER_SETTINGS" "bottom" > > set_global_assignment -name "FAMILY" "Stratix" > set_global_assignment -name "DEVICE" "EP1S60F1020C6" > set_global_assignment -name "FMAX_REQUIREMENT" "167 MHz" > > execute_module -tool map > > initialize_logiclock > > set_logiclock -region "reg_bottom" -auto_size 0 -width 10 -height 10 > -origin X1_Y1 -floating off > set_logiclock_contents -region reg_bottom -to bottom > > execute_module -tool fit > > logiclock_back_annotate -region reg_bottom -routing > export_assignments > > qexec "quartus_cdb bottom --vqm=./bottom.vqm" > > execute_module -tool tan > > project_close > > > > ================================================================================ > == TOP SCRIPT > ================================================================================ > package require ::quartus::project > package require ::quartus::logiclock > package require ::quartus::backannotate > package require ::quartus::flow > > project_new top > > set_global_assignment -name "VQM_FILE" "bottom.vqm" > # (the rest of the "bottom" vqms are put here) > > set_global_assignment -name "VHDL_FILE" "top.vhd" > set_global_assignment -name "COMPILER_SETTINGS" "top" > > set_global_assignment -name "FAMILY" "Stratix" > set_global_assignment -name "DEVICE" "EP1S60F1020C6" > > execute_module -tool map > > initialize_logiclock > logiclock_import -no_pins > uninitialize_logiclock > > execute_module -tool fit > execute_module -tool tan > > project_closeArticle: 67701
More details:
It is an EDIF project in ISE. The EDIF file was not changed when I
switched to ISE 6.2i (I kept ISE 6.1i + sp3 when installing 6.2). I
was just curious to see how faster (and buggier) ISE 6.2i would be
over 6.1i, although I never believed 40% faster Xilinx claimed.
The PC is a dual 2.8GHz CPU, 2GB RAM and XP Pro. I noticed only 500MB
some memory was used by ISE 6.2i.
In ISE 6.1i, the PAR runs only about less than 5 minutes.
In ISE 6.2i, the PAR runs only about one hour.
The design was not contrainted by pin locations and clock timings.
It was definitely a surprise.
-qlyus
Design Summary:
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 14,661 out of 38,784 37%
Number of 4 input LUTs: 7,880 out of 38,784 20%
Logic Distribution:
Number of occupied Slices: 8,400 out of 19,392 43%
Number of Slices containing only related logic: 8,400 out of
8,400 100%
Number of Slices containing unrelated logic: 0 out of
8,400 0%
*See NOTES below for an explanation of the effects of
unrelated logic
Total Number 4 input LUTs: 8,274 out of 38,784 21%
Number used as logic: 7,880
Number used as a route-thru: 392
Number used as Shift registers: 2
Number of bonded IOBs: 210 out of 692 30%
IOB Flip Flops: 205
Number of PPC405s: 0 out of 2 0%
Number of Tbufs: 768 out of 9,696 7%
Number of Block RAMs: 2 out of 192 1%
Number of MULT18X18s: 188 out of 192 97%
Number of GCLKs: 2 out of 16 12%
Number of GTs: 0 out of 12 0%
Number of GT10s: 0 out of 0 0%
Marc Randolph <mrand@my-deja.com> wrote in message news:<-OadnY56jbA5R8rdRVn-uQ@comcast.com>...
> Jim Granville wrote:
>
> > Marc Randolph wrote:
> >
> >> qlyus wrote:
> >>
> >>> Just tried the design of XC2VP40-FF1152 with 40% full.
> >>
> >>
> >>
> >> The design that I'm working on in an XC2VP40-FF1152 is 66% full
> >> currently and PAR takes between 2 and 4 hours (just PAR, not mapping
> >> [another hour] or synthesis [30 minutes]). Times and capacity were
> >> the same for 6.1.3i.
> >>
> >> We have other projects that didn't change any either.
> >>
> >> Using the same project file, have you gone back and re-tried using
> >> 6.1.3i? 10x slower on the newer software is more than a little bizarre.
> >
> >
> > Unless you just fluked onto some threshold, like a PC_RAM resource
> > ceiling ?
> > -jg
>
> Definitely possible since the tools seem to sometimes do wildly
> different things with even the most minor change in source code [I've
> gone from meeting timing to failing timing by quite a bit in an
> unrelated area to where I inverted a bit going into a FF].
>
> Another data point: my memory usage during PAR went down a very marginal
> amount when I went to 6.2.1 (from just above 1.2 GBytes to just below
> 1.2 GBytes).
>
> Marc
Article: 67702im looking more like a book and general architecture, not vendor dependant. as the "hennesy-paterson" book is for RISC, then a book for FPGA. "Ray Andraka" <ray@andraka.com> escribió en el mensaje news:4058950E.1F60D008@andraka.com... > Have you bothered looking at the FPGA vendor's websites, particularly at the > data sheets??? > > paris wrote: > > > hi, > > > > does anybody knows where can i get techinical information about how a FPGA > > works, it's internal architecture, the internal matrix, etc? > > thanks, > > > > paris > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 67703
Vaughn, Thanks for the prompt reply and the various suggestions. As others have noted in this newsgroup, its terrific to be seeing more knowledgeable presence from the good people at Altera. After my post yesterday, I went ahead and manually combined my Memory Sync M512 objects in the vhdl design, so that the synthesizer wouldnt rip them up and change the names (ie workaround). Then, dealing with another issue, I tried wildcards in timing assignments and was delighted with the effects -- in my case I was able to use wildcards to define constraints that are apply even when GENERIC parameters are changed (eg counter or register width). I was also able to make constraints that are valid in either of two conditional GENERATE scenarios. (ie gA:if X generate..., gB:if (not X) generate ...) Coming back to my original problem, I guess I wasn't as clear as I thought I had been. oAA:MemSyncM512 port map(clkFast,InRegAA,OutRegAA); oBB:MemSyncM512 port map(clkFast,InRegBB,OutRegBB); -- oAA, oBB are in different parts of the design -- InRegAA, InRegBB are clocked by clkSlow=(3/8)*clkFast When I try to cut timing paths from InRegAA->oAA|data_a I get a Timing Ignored Message, saying oAA was removed by the synthesizer, because it has combined oAA and oBB, even though the combined object still has the instance-name oAA (albeit the bit-indexing is scrambled). With regard to your suggestions > - Make sure you are cutting the correct name. I'm reasonably confident of this. I usually drag the node from the node finder to the Assignment editor. And the Timing Ignored Message suggests that this is not the problem. > - You can try cutting from the source node: (to *) I can't do this because InRegAA is also used in the ClkSlow domain. > - You can also try cutting all paths from clka to clkb This is a good idea, and "in the end" I should probably do this. In the meantime its good to look at the messages, verify that I am in fact handling the signals with double-sync before cutting the paths. > - You can just define both clocks as absolute (not related) to avoid > the check (note that this is only a good solution if there are no > paths between these clocks you want checked). I didn't know about this. ClkSlow is derived from ClkFast in an on-chip PLL. I should try to see if Quartus will let me assign Absolute Clock settings to separate the input and output of the PLL. Thanks for your help, -rajeev- ---------------- vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0403162332.b99847f@posting.google.com>... > Hi Rajeev, > > I checked with one of our timing constraint gurus. He can't be quite > sure of exactly what the problem is without more information, so he > has several suggestions on ways to fix this: > > - Make sure you are cutting the correct name. It's best to go to the > Timing Report and copy the exact name that we are using (Registers in > the memory will usually have a "~reg_addr" or "~reg_data" or something > like that. You can also try using wildcards to avoid the extra > characters: > set_instance_assignment -to "my_memory_name*" -name CUT ON > > - You can try cutting from the source node: > set_instance_assignment-from "my_source" -to * -name CUT ON > > - You can also try cutting all paths from clka to clkb > set_instance_assignment-from clka -to clkb -name CUT ON > > - You can just define both clocks as absolute (not related) to avoid > the check (note that this is only a good solution if there are no > paths between these clocks you want checked). > > If this doesn't help, please send the list_path output of the timing > path you want to CUT, and it'll help us be more specific. > > Regards, > > Vaughn > Altera > > > Hello All, > > > > I'm doing a Stratix design using Quartus VHDL, I'm using > > memory blocks to double-sync signals crossing clock domains > > from slow to fast. Clocks are fractional multiples. > > > > (1) Static timing analysis checks the paths and complains. > > > > (2) The synthesizer rips up the memory blocks to consolidate > > the instances which are in different places. > > > > I'd like to cut the timing paths, but when I try I get Timing > > Constraint Ignored messages saying memory block MMM was removed > > by synthesis. I'd like to let the synthesizer combine the > > memories (saves device resources), I'd like not to consolidate > > the memories by hand (preserves my existing organization), and > > I'd like the timing analysis complaints to go away. > > > > What's the right thing to do ? > > > > Thanks in advance for your help and suggestions, > > -rajeev-Article: 67704
Ray, Just curious... can you put the UPS lines in and remain code-compliant ? -rajeev- --------------- Ray Andraka <ray@andraka.com> wrote in message news:<40579654.392279D4@andraka.com>... > Sounds like a neat idea. I've gotten pretty good at snaking wires through existing > walls. Managed to get cat5, video and phone to every room in the house I just sold. Just > starting over with the new house. Anyway, never thought of pulling a UPS line through > too. Instead, I have the answer machines etc plugged in where there are computers. > > john jakson wrote: > <...>Article: 67705
Once in a while I have problem uploading quartusII bit file into cyclones. The bitfiles are fully succesfull generated using QuartusII v3 SP1 or SP2 and uploaded using JTAG byteblaster tools. Sometimes (lets say one in every thirty builds) the bit file is refused by the cyclone (located on the NIOS development board). Only thing to get a new (working) bitfile is to make minor changes (add or remove a FF) and try again. Is this a known problem? Does anyone have a clue how to work around this? Regard EddyArticle: 67706
> That's too bad. But you can still try to find something that will fit > the socket and then roll your own board to connect to that. You can do > a board layout with free tools and get one made for under $50. But you > need to find a way to plug it in. I think some of the connector people > sell pins to use on a board to allow it to fit sockets. You have to > layout the pins on your board and will likely have to hand solder them. > But you can end up with a complete solution for around $100. Yep. The more I've searched, the better the homebrew solution sounds. > The interface to the CPU *has* to be the same on all boards with that > socket. The CPUs are not going to change depending on the chip set. > Your software must be written to match the motherboard, but you will > have that regardless of what approach you take. Even with PCI cards, > your software will only support the card it is written for. True. I was thinking more in terms of software but it seems that rewriting the drivers is a small price to pay if I can get a system like this working. > If you go with a PCI approach, you are always limited to the slow bus > speeds relative to the mobo CPU interface. For example, PCI is 133 MB > max. USB2.0 is 60 MB max. How many USB 2.0 can you support while also > talking to an IDE or SCSI controller via the PCI bus? The bandwidth > runs out very quickly with modern devices. USB2.0 and IDE are built > into the Northbridge on most boards now. Good point, I hadn't given that enough thought. By comparison, what bandwidth could I expect from a motherboard? I think you've won me over to the socket. The socket approach offers the most flexibility. Creating the board myself offers a much cheaper solution. I noticed from your post that (I think) you design your own board. If this is true could you recommend a toolset (preferably free) for board layout & design? I don't have a lot of experience in this area but I'm sure I could pick it up pretty fast based on prior experience. It sounds like a good learning experience (and it offers a lot of flexibility). Also, where do you send your designs for production? > If you like the XC3S400, maybe we can do something cooperatively and I > can design and make the board? My board is very crowded, but adding PCI > is something I am planning on in the next year. Sounds interesting. Do you have any specs or photos (on the web)? Thanks so much. You've been a great resource!Article: 67707
The problem is that the architectures are more or less vendor dependent,
especially when you start looking at routing structures and special features.
Many use a 4 input look up table as the basic element, but the similarity
generally stops there. It is also a moving target, so from family to family
within the same vendor you'll see differences in the architecture.
paris wrote:
> im looking more like a book and general architecture, not vendor dependant.
> as the "hennesy-paterson" book is for RISC, then a book for FPGA.
>
> "Ray Andraka" <ray@andraka.com> escribió en el mensaje
> news:4058950E.1F60D008@andraka.com...
> > Have you bothered looking at the FPGA vendor's websites, particularly at
> the
> > data sheets???
> >
> > paris wrote:
> >
> > > hi,
> > >
> > > does anybody knows where can i get techinical information about how a
> FPGA
> > > works, it's internal architecture, the internal matrix, etc?
> > > thanks,
> > >
> > > paris
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67708
Good point, probably not with an off the shelf computer UPS. You'd probably have set it up
with a separate panel similar to a backup generator, and then it would probably need to be a UPS
rated for permanent installation rather than a computer grade portable device. It is probably
cheaper to use separate UPS's where needed. I have invested in a number of the small UPS's
which I have connected to things like the VCR, answering machine, network switch & cable modem.
Rajeev wrote:
> Ray,
>
> Just curious... can you put the UPS lines in and remain code-compliant ?
>
> -rajeev-
> ---------------
> Ray Andraka <ray@andraka.com> wrote in message news:<40579654.392279D4@andraka.com>...
> > Sounds like a neat idea. I've gotten pretty good at snaking wires through existing
> > walls. Managed to get cat5, video and phone to every room in the house I just sold. Just
> > starting over with the new house. Anyway, never thought of pulling a UPS line through
> > too. Instead, I have the answer machines etc plugged in where there are computers.
> >
> > john jakson wrote:
> >
> <...>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67709roland voraberger wrote: > hello! > > i´ve got big problems with RAM in a ACEX 1k design. i can´t get a fit > because i use too much (16/ 12) EAB´s but in total number of bits i´m > far beyond the maximum number of the bits available. > what can i do (software is max+plus II 10.1) Did you try the various options for fitting ? I don't have MaxPlus2 running at the moment, but remember having seen dozends of options. Combinatorial logic being contained in a EAB could be spread out and this sort of things. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 67710
john jakson wrote: > I asked these tool vendors to allow the end user to accept edits at > least for placement of instances and then to remember those as hints. > But they always regenerate them from scratch. I agree that having savable viewer options would be useful. However, not having to draw the boxes and wires is the main thing. I don't want to do graphical editing, I just want to have a look. > If I used the schematic tools, they write the crappiest HDL they can > so its the lesser of 2 evils. Yes. The code's the thing. Simulation waveforms can make up for the HDL's lack of graphical hints. > The other issue I now see is that even the perfect schematic tool with > perfect written Verilog netlist would now have nother problem, I would > want it to write out the Verilog in a precise format and or to write > out a cycle equivalent version in C line by line equivalent. Thats > really asking too much. For me, a schematic is not the source, but a view of the source. If I were to overwrite code from this view, the schematic would become the source document. -- Mike TreselerArticle: 67711
>Chapter 3. See the section on "Using Block SelectRAM Memory." The >actual timing numbers for the RAM can be found in the datasheets or >better yet, the the timing analysis portion of the software after you >target that component. Are the numbers in the on-line data sheets updated when the software gets updated with a new batch of timing parameters? Or is that level of detail (generally?) lost in the noise of routing delays? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67712
In this fast-moving field, any hardcover book would be hopelessly obsolete. Most FPGAs are of the look-up-table-based reconfigurable flavor, commonly called "SRAM-based" although that is a misnomer. For that type, there are two dominant manufacturers, Altera and Xilinx (in alphabetical order!). Their websites are full of interesting information. Peter Alfke, Xilinx Applications ==================== > From: "paris" <malaka@email.it> > Organization: ENST, France > Newsgroups: comp.arch.fpga > Date: Wed, 17 Mar 2004 20:06:06 +0100 > Subject: Re: newbie question about fpga internals > > im looking more like a book and general architecture, not vendor dependant. > as the "hennesy-paterson" book is for RISC, then a book for FPGA. > > > "Ray Andraka" <ray@andraka.com> escribió en el mensaje > news:4058950E.1F60D008@andraka.com... >> Have you bothered looking at the FPGA vendor's websites, particularly at > the >> data sheets??? >> >> paris wrote: >> >>> hi, >>> >>> does anybody knows where can i get techinical information about how a > FPGA >>> works, it's internal architecture, the internal matrix, etc? >>> thanks, >>> >>> paris >> >> -- >> --Ray Andraka, P.E. >> President, the Andraka Consulting Group, Inc. >> 401/884-7930 Fax 401/884-7950 >> email ray@andraka.com >> http://www.andraka.com >> >> "They that give up essential liberty to obtain a little >> temporary safety deserve neither liberty nor safety." >> -Benjamin Franklin, 1759 >> >> > >Article: 67713
george.martin@att.net (George) wrote in message news:<e9d879fa.0403121402.2f50c71a@posting.google.com>... > I've just completes a design change to an Altera ACEX1K100 device. > It's running a NIOS processor and I added more serial ports. Not a > big deal. > > While waiting for the new prototype boards I upgraded from Quartus II > 2.2 to Quartus II 4.0. > > When I connect the new boards using Altera ByteBlasterMV (PC parallel > to JTAG) and attempt to download this new configuration the > programming window just zips through (less than 1 sec). It says it's > done but new configuration has NOT been loaded. > > If I revert to Quartus II Ver. 2.2 BOTH old and new boards can be > loaded with either old or new configuration. > If I upgrade to Quartus II 4.0 NEITHER old or new boards can't be > loaded with any configuration. > > Anyone seen this?? > > Any suggestions?? > > Thanks > George Hi George and Kari, The ACEX1K problem that you report has been verified. For the benefit of everyone here is the problem description: A problem in the Quartus II 4.0 full and web edition software prevents successful JTAG-based configuration of ACEX 1K devices. This problem only affects the Programmer and does not affect configuration file (SOF) generation. All Altera download cables including the USB Blaster, MasterBlaster, ByteBlaster II, and ByteBlasterMV are affected. Fix for the problem: Software patch 0.18 for the Quartus II software version 4.0 resolves this problem. To request this patch, please contact Altera Customer Applications at http:\\mysupport.altera.com. This fix will be included in Quartus II 4.0 Service Pack 1. - Subroto Datta Altera Corp.Article: 67714
Francisco Camarero wrote: > > Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > Fran Try HDL Designer from www.mentor.com I use it with my students, and my company use it too. It is just great and very low cost for uducational. You will pay $500 by year for a complet package. But still stay expensive for company. Students learn both VHDL and structural design. In first step, the student learn system logic, using prededined VHDL graphical cell (mux, and , counter, adder, filter, flip-flop, ALU, register bank ...). Then student learn VHDL and do their own cell or mini-core implementation like UART with FIFOs, SPDIF decoder and encoder ... Laurent www.hevs.ch , the school www.amontec.com , my companyArticle: 67715
Hello, guys, i am implementing a Finite State Machine using VHDL, and trying to get it synthesis, but i came up with the error with ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:528 - Multi-source in Unit <state_control_module> on signal <next_state<2>1> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <state_control_module> on signal <next_state<3>1> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <state_control_module> on signal <next_state<0>1> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <state_control_module> on signal <next_state<1>1> not replaced by logic Signal is stuck at GND ERROR:Xst:415 - Synthesis failed from the XST what is the problem? and how can i solve it, it is very urgent, i am only a beginner, please help~ =( it seems that signal is stuck at ground in the schmetics from a MUX,, here is some of my code that i think the problem i had, the fsm, is 3 process. process1 (current_state, inputs........) begin case current_state is when state0 => next_state <= state1; -- default assignment to avert latch output1 <= '0'; outpput2 <= '1'; if ... else... stuff;; end case; end process; process(CLOCK, RESET, over) variable c_state : std_logic_vector(3 downto 0); begin --current_state <= current_state; if (RESET = '1') then next_state <= "0000"; elsif CLOCK'EVENT and CLOCK='1' then if (over = '1') then current_state <= next_state; --- here might be the problem that produce the XST 5 else current_state <= current_state; end if; end if; end process; process(current_state) begin PRESENT_STATE <= current_state; end process; end Behavioral;Article: 67716
jrh wrote: > > In article <ET0Yb.1$sG5.1036@news.uswest.net>, mygarbagepail@hotmail.com > says... > > > "jrh" <no@spam.com> wrote in message > > news:Si_Xb.57494$P17.17621@fed1read03... > >> Do you want the Forth to supervise a set of DSPs, or be a DSP? > > I want the Forth to direct the operation of a multiply-and-accumulate > > module, and to > > have access to a fast complex multiply. > > > -Davka > > I think there is PLD/FPGA with an array of MACs available, but I don't > remember the details. The ACs are trivial in FPGAs, it is the M that is harder. The more recent versions of the Xilinx and Altera FPGAs have multipliers built in just like memory blocks, ready for you to use. But these are fixed point units, to do floating point you would need to pipeline with the appropriate shifting hardware. I don't know that you need a CPU to "direct" arithmetic operations. If you are considering doing math in an FPGA, it will only be efficient if you are doing pipelined operations such as vector arithmetic. Otherwise you can just use a CPU with an on chip multiplier and get the same or better results. If you are doing pipelined operations, you will need hardware to control the timing, not a CPU. A CPU can set things up, of course, but then you are duplicating what a DSP chip does. It can be fun to use Forth or other interesting ideas in chips, but I don't know of an application where this is a better way to go than an off the shelf DSP or CPU. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67717
Manfred Balik wrote: > > 1)I'm searching for an PC104 Evaluation Board (not PC104+ !!!) with a an > Altera FPGA. > 2)Where can I get a PC104 Core in VHDL ? PC104 is just the PC ISA bus with a different connector and a few minor changes to driver strengths. There is not really a "core" for it since it is so simple. You just decode addresses and control strobes like an async memory device. Our board will have an EP1C50 on the PC104 bus and an ARM CPU to load it. It will also have a DSP chip along with a Xilinx FPGA and various memory on the DSP bus, but you can ignore those parts :) It should be ready by the end of Q2 if you can wait. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67718
John wrote: > > > If you like the XC3S400, maybe we can do something cooperatively and I > > can design and make the board? My board is very crowded, but adding PCI > > is something I am planning on in the next year. > > Sounds interesting. Do you have any specs or photos (on the web)? You can take a look at Eagle. They offer a free, limited version that will do what you want, I think. I can't remember if it will do 4 layer which you definitely want. There are other brands that give you a 30 day eval. Once you are ready to lay out the board, you can certainly do it in 30 days. I don't have any pictures of the new board, but you can view an older board at the web site below. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67719
Marc Randolph <mrand@my-deja.com> wrote in message news:<oZ-dnfdqudEZUMrdRVn-jA@comcast.com>... > qlyus wrote: > > > Just tried the design of XC2VP40-FF1152 with 40% full. > > The design that I'm working on in an XC2VP40-FF1152 is 66% full > currently and PAR takes between 2 and 4 hours (just PAR, not mapping > [another hour] or synthesis [30 minutes]). Times and capacity were the > same for 6.1.3i. > > We have other projects that didn't change any either. > > Using the same project file, have you gone back and re-tried using > 6.1.3i? 10x slower on the newer software is more than a little bizarre. > > Good luck, > > Marc I had similar problem, when adding a new memory block. There is only the slightest difference between the templates for a blockram v a distributed ram, and if you want a BRAM and it figures DistributedRam a 30s compile goes many x slower, otherwise I haven't seen any slowdown other than due to growth of complexity. Did the generated logic stay same as expected?Article: 67720
> It can be fun to use Forth or other interesting ideas in chips, but I > don't know of an application where this is a better way to go than an > off the shelf DSP or CPU. It might be a way to maintain intellectual property. If it's hard to reverse-engineer your chip, it will definitely be hard to reverse-engineer your code for it. And anybody who wants to use it has to get the hardware from you along with the software. Of course that makes your products harder to sell, too. So there's a tradeoff. But if you have customers and competitors that you plain don't trust, and if you've done work that deserves heavy-duty tarde secrets, it's a possible way to go.Article: 67721
rickman <spamgoeshere4@yahoo.com> wrote in message news:<405899B0.ACBE603A@yahoo.com>... > John wrote: > > > > I got a quote back from them and as I expected the CPU socket route will > > cost a lot. They don't have anything already made so they say it will > > have to be cutsom. The price would include: PCB Design, PCB Fabrication, > > PCB Fabrication Test, Solder Stencils, and Setup. This is especially > > not cost effective for small quantities. Here are the estimates (based > > on board complexity): > > > > For 2 Boards: $10000-12000 > > For 50 Boards: $14000-15000 > > > > As you can see, this is very expensive (especially for small quantities). > > That's too bad. But you can still try to find something that will fit > the socket and then roll your own board to connect to that. You can do > a board layout with free tools and get one made for under $50. But you > need to find a way to plug it in. I think some of the connector people > sell pins to use on a board to allow it to fit sockets. You have to > layout the pins on your board and will likely have to hand solder them. > But you can end up with a complete solution for around $100. > > > > > If you plug into the CPU socket, you don't need to build any of the > > > other stuff at all. I am sure you can get adequate info on socket 7. > > > Intel had to document it for the chip makers. This would be part of the > > > chip spec. If not Intel, then AMD likely has a spec. They made parts > > > for it too, didn't they? Why do you need a socket that will be long > > > lived? Changing your FPGA design for a different socket should be no > > > big deal if you need to do that in a couple of years. Are you going to > > > mass produce this thing? snipping that leaves one easy option left, how about the slot A format a PCB edge connector or perhaps the Intel slot design. Only problem is its still a difficult spec to get hold of as its basically the Alpha EV bus licensed to AMD back when it was 100MHz double pumped IIRC. There are always lots of older 500MHz Athlon systems out there that used this connector for which you could easily trash the cpu to examine the design. These mobos with Slot package are very cheap available but the boards probably won't have USB1.1 let alone 2.0. regards johnjakson_usa_comArticle: 67722
The register "next_state" can only be assigned within ONE process. That is what caused the error... Kelvin Kirstie Wong <csleunc@essex.ac.uk> wrote in message news:5607e00d.0403171416.2a1a761f@posting.google.com... > Hello, guys, i am implementing a Finite State Machine using VHDL, and > trying to get it synthesis, but i came up with the error with > > ========================================================================= > * Low Level Synthesis > * > ========================================================================= > WARNING:Xst:528 - Multi-source in Unit <state_control_module> on > signal <next_state<2>1> not replaced by logic > Signal is stuck at GND > WARNING:Xst:528 - Multi-source in Unit <state_control_module> on > signal <next_state<3>1> not replaced by logic > Signal is stuck at GND > WARNING:Xst:528 - Multi-source in Unit <state_control_module> on > signal <next_state<0>1> not replaced by logic > Signal is stuck at GND > WARNING:Xst:528 - Multi-source in Unit <state_control_module> on > signal <next_state<1>1> not replaced by logic > Signal is stuck at GND > ERROR:Xst:415 - Synthesis failed > > from the XST > > what is the problem? and how can i solve it, it is very urgent, i am > only a beginner, please help~ =( > > it seems that signal is stuck at ground in the schmetics from a MUX,, > > here is some of my code that i think the problem i had, the fsm, is 3 > process. > > process1 (current_state, inputs........) > begin > case current_state is > > when state0 => > next_state <= state1; -- default assignment to avert latch > output1 <= '0'; > outpput2 <= '1'; > if ... else... stuff;; > > end case; > end process; > > process(CLOCK, RESET, over) > variable c_state : std_logic_vector(3 downto 0); > begin > --current_state <= current_state; > if (RESET = '1') then > next_state <= "0000"; > elsif CLOCK'EVENT and CLOCK='1' then > if (over = '1') then > > current_state <= next_state; --- here might be the problem that > produce the XST > > 5 > else > current_state <= current_state; > end if; > end if; > end process; > > process(current_state) > begin > PRESENT_STATE <= current_state; > end process; > > end Behavioral;Article: 67723
Try Insight maybe...I just got my Spartan 3 LC board from them...it has a XC3S400 in it. good luck. "Brad Eckert" <nospaambrad1@tinyboot.com> wrote in message news:7d4cc56.0403170952.6724372d@posting.google.com... > I know this subject has been kicked around a lot here, but here we go > again. > > Where can one get a small quantity of XC3S400s? I already have some on > indefinite back order at Avnet. Maybe there is another source? > > Reminds me of John Cleese in the cheese shop: > "Do you in fact have _any_ Spartan IIIs?" > "Yes." > "Really?" > "No."Article: 67724
"Subroto Datta" <sdatta@altera.com> wrote in message news:<Sv_5c.26205 snipping > > The original poster asked for a schematic editor, to enter schematics along > with predefined symbols for ALU's registers etc. Just to make sure there is > no confusion, the Quartus Schematic editor (aka Block Editor) is a different > application from the RTL viewer. This is your classical schematic editor > which allows you to place symbols which are predefined or created on the > fly, in place editor node names, create busses and hook up the ports .... > > The purpose of the RTL viewer is to allow the user to get a visual > description/understanding of the logic generated during RTL synthesis by > Quartus. It requires that the design has been processed by quartus_map i.e. > the synthesis application. The contents of the RTL viewer cannot be modified > or saved into a file. The RTL viewer is not available in the Free Web > Edition. > > > - Subroto Datta > Altera Corp. Does Quartus schematic allow a symbol that is already in place in a schematic to have its self edited, ie can I add more ports to the symbol while viewing it or does it require a new symbol view window to reedit the symbol out of place. In a heavy schematic use environment, this one difference makes it 10x more work if its not present. 2nd Can you ever see allowing what I and Ray have asked for, that is to edit the RTL viewer with the changes only to placement and wire shapes as hints so the next regeneration uses those hints if available for the next draw. Again with out that, the tool is almost useless. I suspect that most RTL viewers come mostly from one little company in Germany, I see them at DAC. They had some interest in this idea but I didn't pursue it. regards johnjakson_usa_com
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