Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi all, can somebody, having experience with gigabit transmission using an FPGA and an external SERDES chip - like the one from TI TLK1501, tell me what the maximum allowable cycle-to-cycle clock jitter is, if you want to xmit-and-rcv a one gigabit serial datastream. TI's data sheet is saying something about ~40psec max. Is that really true, or do I misundertand the spec. Best Regards Markus BTW. What does a DLL - Spartan-IIE - add in clkx1 mode +-100 psec jitter ? -- Mit freundlichen Grüssen Markus Meng ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 ** ** CH-5400 Baden Web www.meng-engineering.ch ** ********************************************************************Article: 67476
What have you found better about Quartus 4 re. LogicLock? I'm working on a project with fairly heavy LogicLock usage which does a good job of crasing Quartus 3.0 SP2, but it also crashed 4.0 the first time I tried to compile it, which had me worried. The next compile worked, so I'm hoping it's more stable. Are you finding LogicLock more stable in 4.0? -- Pete > We have had lots of success so far ... been using it for a while. > > Got any optimisation flags ticked? > > We do a lot of minimise area with chains stuff and logic locking (which is > tonnes better than 3) but there used to be issues with some flags in 3. >Article: 67477
I've been helping to beta test version 3 of Pulsonix for the last few months. It has now been released and is available for download from: http://www.pulsonix.com. Without a license it's a full working demo (up to 100 pins for schematic entry and PCB design) and Pulsonix will provide a 30 day license for a fuller evaluation on request. Pulsonix support is excellent and bugs get fixed very quickly, unlike some other products I could name. Support is also available via the Pulsonix Users Group: http://groups.yahoo.com/group/PulsonixUG/ which doesn't get a lot of use as the software is very intuitive and easy to use. It comes with comprehensive new libraries including lots of Xilinx and Altera parts. There are numerous additions and enhancements including an optional Chip Packaging Toolkit. LeonArticle: 67478
On 5 Mar 2004 14:22:00 -0800, stewart1r1@hotmail.com (Stewart Smith) wrote: >Hi >I have a query for those of you whish to help >My Problem >Variable frequency output via a PLD control of a Switched reluctance >motor. > >(Overview) >The system should be capable of driving a three phase Switched >Reluctance motor open-loop (no current or position feedback), no-load, >at a minimum speed of 10 r.p.m. >The system should include a soft start (frequency ramp) facility and >the ability to operate in either direction. >Any suitable power electronic devices may be used. >The control electronics must be isolated from the power electronics. >The control electronics should comprise of PLD technology. > >So my part is the softstart (thanks guys) > >I have only cupl available and a Lattice Gal20v8 device. >my max frequency output would be 200Hz my minimum requirement is 2 Hz. >from this I would like to try and make the input frequency to say >around 400Hz.Then somehow cut this frequency by use of a counter type >flip-flop array in the Gal, but would also like to take the outputs >from the said (4 bit) counter to use as my ramp. Thus Giving a >possible 16 frequency outputs. >Is it possible to have the counter and then have a state machine use >the outputs of the counter to generate a ramping frequency effect on 1 >single output pin of the GAL? >My knowledge of cupl is to say, at best is limited, I have seen >programs in VHDL (of which my knowledge is even less), which claim to >be able to achieve this. >I am a student undertaking an assignment so I am not looking for >answers (I want to learn) only pointers on how to get there. > >Very best regards >Stewart You can also use an accumulator made from a 4-bit full adder and a quad D-Flop. Connect the adder sum output to the D inputs. Take the Q outputs back to the adder input port B. Apply your velocity command to the adder port A. Clock the quad D-Flop with your frequency of choice. The adder carry-out will be your variable frequency. The relationship will be Fout = n * Fin / 16 where n is a 4-bit value and Fin is your clock frequency. A 74HC283 for the adder and a 74HC174 for the D-Flops will do. MarissArticle: 67479
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0403111600.2664b309@posting.google.com>... > `define wid 4 > > module Add32( > input ck, input [`wid-1:0] a,b, output [`wid-1:0] o); > > reg [`wid-1:0] ra,rb,rz; > assign o = rz; > > always @(posedge ck) > begin > rz <= ra+rb; ra <= a; rb <= b; > end > endmodule Why are you using `define rather than parameters? --aArticle: 67480
Bruno, I have seen this error occasionally when compiled files have become corrupt, or if the project directories are not writeable. Can you select Project -> Cleanup Project Files (if you're using ISE) or remove the xst subdirectory if you are running on the command line? I grabbed the HDL source you have posted and it compiles successfully in ISE 6.2i, so XST has no problems with the code. Which version of software are you using? thanks, david. Bruno Vermeersch wrote: > Hi everybody, > > I'm rather new to the whole VHDL business but I'm surrounded by good > helpfull people. Yesterday I wrote a short block which has caused us > al headaches. The error I get after "Syntax check" is: > > Started process "Check Syntax". > > ========================================================================= > > # HDL Compilation * > ========================================================================= > Compiling vhdl file c:/bruno/tb/test.vhd in Library work. > ERROR:HDLParsers:3214 - HdpStrSafeCatPX: Str2 is NULL > ERROR: XST failed > Process "Check Syntax" did not complete. > > anybody who can help us out? > > thx in advance > > Bruno >Article: 67481
"Nicholas C. Weaver" wrote: > > In article <4051D7D1.15FFE3E7@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >"Nicholas C. Weaver" wrote: > >> > >> Using lots of Altera features and cleverness to combine things, > >> including the LUT cascade chain. > > > >I like the cascade chain concept. It can make wide muxes much easier. > >But I have never been able to get the tools to use it for combining more > >than two LUTs when using HDL. Any suggestions on how to do this? I > >will be optimizing a design after it is fully debugged and this is one > >of the first things I want to address. > > The altera crew hand-mapped the logic, using Altera's features to > specify exactly whats in a LUT. Was this an HDL design instantiating the logic? Or did they work at a lower level? I am not familiar with the techniques of distributing a core. Is this provided as a prerouted macro? Or is it easy to place and route the macro once the cascades and other features are utilized? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67482
Leon Heller wrote: > > I've been helping to beta test version 3 of Pulsonix for the last few > months. It has now been released and is available for download from: > > http://www.pulsonix.com. > > Without a license it's a full working demo (up to 100 pins for schematic > entry and PCB design) and Pulsonix will provide a 30 day license for a > fuller evaluation on request. > > Pulsonix support is excellent and bugs get fixed very quickly, unlike some > other products I could name. Support is also available via the Pulsonix > Users Group: > > http://groups.yahoo.com/group/PulsonixUG/ > > which doesn't get a lot of use as the software is very intuitive and easy to > use. > > It comes with comprehensive new libraries including lots of Xilinx and > Altera parts. There are numerous additions and enhancements including an > optional Chip Packaging Toolkit. I would suggest that the demo version be upped to 500 pins. Heck, most of the chips I use have more than 100 pins. I find that a lot of vendors are so afraid that someone will actually use their product without paying for that they make it hard to eval the product. I can't speak for others, but I don't even bother to eval products unless I can work it into my work schedule as useful work. Why would I bother to spend a couple of days to play with a new tool when I should be working? It's not like there aren't plenty of PCB packages out there that are easy to use. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67483
Leon Heller wrote: > I've been helping to beta test version 3 of Pulsonix for the last few > months. It has now been released and is available for download from: > > http://www.pulsonix.com. > > Without a license it's a full working demo (up to 100 pins for schematic > entry and PCB design) and Pulsonix will provide a 30 day license for a > fuller evaluation on request. > When advertising commercial software it's a good idea to state which platform(s) and/or operating system(s) it is available for. While this product is no doubt excellent, it appears to be be available only for Windows. PaulArticle: 67484
Hi , does any body know how many uAmps a single input configured as LVTTL for Spartan-3 families sink from the driver in both, high and low levels????... thank you SergioArticle: 67485
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:405214D6.9711C1A3@yahoo.com... > Leon Heller wrote: > > > > I've been helping to beta test version 3 of Pulsonix for the last few > > months. It has now been released and is available for download from: > > > > http://www.pulsonix.com. > > > > Without a license it's a full working demo (up to 100 pins for schematic > > entry and PCB design) and Pulsonix will provide a 30 day license for a > > fuller evaluation on request. > > > > Pulsonix support is excellent and bugs get fixed very quickly, unlike some > > other products I could name. Support is also available via the Pulsonix > > Users Group: > > > > http://groups.yahoo.com/group/PulsonixUG/ > > > > which doesn't get a lot of use as the software is very intuitive and easy to > > use. > > > > It comes with comprehensive new libraries including lots of Xilinx and > > Altera parts. There are numerous additions and enhancements including an > > optional Chip Packaging Toolkit. > > I would suggest that the demo version be upped to 500 pins. Heck, most > of the chips I use have more than 100 pins. > > I find that a lot of vendors are so afraid that someone will actually > use their product without paying for that they make it hard to eval the > product. I can't speak for others, but I don't even bother to eval > products unless I can work it into my work schedule as useful work. Why > would I bother to spend a couple of days to play with a new tool when I > should be working? It's not like there aren't plenty of PCB packages > out there that are easy to use. Pulsonix will provide a full 30 day license on request. LeonArticle: 67486
Hello everyone, I have a verilog design, that needs to be targetted on Xilinx FPGA of RC200 board. The design has two 32-bit inputs,2 1-bit inputs, a 32-bit output and a 1-bit output. The data input should be read from files(maybe text containing some 40000 samples of input data) and the output obtained should be written onto some files. Can the input read and written onto files on PC host. If so, can anyone please tell me how to do it(like do we have to use the DSM). Or is there any other way of doing it, like storing the data on SRAM banks of the board. Thank You, KumarArticle: 67487
hello sir, i am new to this field. i need your help to complete my project. i am using xilinx xc4010e fpga board and Xilinx Spartan 4k 4.2. i am using vhdl programming method. i want to know that is it possible to use the bitfile that is generated by other software such as ise 6.2i in my software(Xilinx Spartan 4k 4.2). and am i able to complete my project this way.' please tell me regards rajivArticle: 67488
Leon Heller wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:405214D6.9711C1A3@yahoo.com... > > Leon Heller wrote: > > > > > > I've been helping to beta test version 3 of Pulsonix for the last few > > > months. It has now been released and is available for download from: > > > > > > http://www.pulsonix.com. > > > > > > Without a license it's a full working demo (up to 100 pins for schematic > > > entry and PCB design) and Pulsonix will provide a 30 day license for a > > > fuller evaluation on request. > > > > > > Pulsonix support is excellent and bugs get fixed very quickly, unlike > some > > > other products I could name. Support is also available via the Pulsonix > > > Users Group: > > > > > > http://groups.yahoo.com/group/PulsonixUG/ > > > > > > which doesn't get a lot of use as the software is very intuitive and > easy to > > > use. > > > > > > It comes with comprehensive new libraries including lots of Xilinx and > > > Altera parts. There are numerous additions and enhancements including an > > > optional Chip Packaging Toolkit. > > > > I would suggest that the demo version be upped to 500 pins. Heck, most > > of the chips I use have more than 100 pins. > > > > I find that a lot of vendors are so afraid that someone will actually > > use their product without paying for that they make it hard to eval the > > product. I can't speak for others, but I don't even bother to eval > > products unless I can work it into my work schedule as useful work. Why > > would I bother to spend a couple of days to play with a new tool when I > > should be working? It's not like there aren't plenty of PCB packages > > out there that are easy to use. > > Pulsonix will provide a full 30 day license on request. I read that. But unless a tool allows me to do *useful* work, I don't have the time to eval it. Giving me 30 days puts me in a position where I *have* to buy it if I want to maintain a design. I recently used Eagle to design a small board. I don't think it is the best tool around, but it is good enough for many designs. I will be able to maintain this design indefinitely without having to purchase the SW. If I decide that this tool is good enough for the rest of my work, I *will* buy it. But unless I could have done a useful design initially, I would not even have considered it. My point is that for me, the price of my time for evaluating a product is to provide a tool that I can do *useful* work with as part of the eval. This precludes 100 pins or 30 day limits. This is just my opinion. I am sure you will find lots of users who are willing to spend their time and money to eval a tool. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67489
HI Its not problem with the board or system ACE, its the problem with flash card, your flash card should be formatted with Win 98 machines and not higher versions. Since sys ace has trouble recognizing the format, the error led is always on hope this helps bye RamArticle: 67490
hello dear, there is a free software on the xilinx side that will support your board. and this is Xilinx Spartan 4k 4.2. go to the site and get it. best of luck. rajiv ouadid@iquebec.com wrote in message news:<sg62c.19444$qA2.1319278@news20.bellglobal.com>... > Hi every body, > I tried to make a P&R with ISE 5.2 and i saw that there is no XC4000 > target possible. Is there a library i have to download or do i have to > look for an old version of Xilinx tools. If so what is the last version > and tool that will be capable of making P&R for and XC4003A and an > XC3020A > ThanksArticle: 67491
I've just completes a design change to an Altera ACEX1K100 device. It's running a NIOS processor and I added more serial ports. Not a big deal. While waiting for the new prototype boards I upgraded from Quartus II 2.2 to Quartus II 4.0. When I connect the new boards using Altera ByteBlasterMV (PC parallel to JTAG) and attempt to download this new configuration the programming window just zips through (less than 1 sec). It says it's done but new configuration has NOT been loaded. If I revert to Quartus II Ver. 2.2 BOTH old and new boards can be loaded with either old or new configuration. If I upgrade to Quartus II 4.0 NEITHER old or new boards can't be loaded with any configuration. Anyone seen this?? Any suggestions?? Thanks GeorgeArticle: 67492
Stewart Smith wrote:
> Jim Granville <no.spam@designtools.co.nz> wrote in message news:<%1h2c.34366$ws.3433570@news02.tsnz.net>...
<snip>
> Thank you for taking time to respond
> Have looked into the link you suggested and, no problem for me to use
> this type of device, in fact they have them in stock at uni which is
> handy. This definitely seems a step in the right direction.
>
> The external clock source I thought was maybe to use a waveform
> generator which could be fine tuned to my max Frequency requirements.
>
> When you suggest using the phase signal to clock the step rate is the
> Mergecell you refer to, which in turn then would be the clocking
> signal to the counter pld. Can this be done internally or do I need to
> feed back physically to three input pins.
On the little SPLDs like the 20V8 you mentioned, you cannot clock
internally, so will need an external wire.
16V8/20V8 also cannot use the CLK pin as a product term ( historical
legacy reasons, when these devices were first invented fuses were VERY
expensive in $, power and yield, so some compromises were made )
The newer CPLDs above 22V10 level, all have internal clock capability.
They also have clock-enables.
> Would be interested on what you think, the Dirn bit should look like.
> I am still looking into the coding for the saturating up/down counter,
> can get it to count up and down no problem getting it stop any stage
> is another thing.
On a 20V8 you need to code a HOLD stage, something like a state engine
Qfield = CountUp & FieldPlusOne
# CountUp & FieldMinusOne
# Hold & QField;
ie, for hold, simply feed the .Q back to the .D
-jg
Article: 67493I did it with RS232.Article: 67494
In article <40512826@news.starhub.net.sg>, Kelvin @ SG <kelvin8157@hotmail.com> wrote: >I am wondering whether XST handles // synopsys parallel_case? > >Plus, How do I know XST has taken in the // synthesis parallel_case? I >didn't see any such >information in the synthesis transcripts with either //synopsys or >//synthesis... > >Best Regards, >Kelvin My advice is to not use the parallel_case directive. If you specify all the cases, it's redundant. If you haven't, then your synthesis tool will generate hardware that will not match your simulator. This is usually a bad thing to do. Just specify all of the cases explicitly or write your code differently. For similar reasons, avoid Verilog's casex in synthesized code as well. KentArticle: 67495
Hi folks, Is there any tutorials/examples on Transport Stream, Program Stream transcoding for MPEG2 application ? I would like to do the transcode on FPGA. I would be happy if someone shed me a light. Thanks in advance.Article: 67496
Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: > In article <adb3971c.0403110735.71e1b6e8@posting.google.com>, > john jakson <johnjakson@yahoo.com> wrote: > >jon@beniston.com (Jon Beniston) wrote in message > >news:<e87b9ce8.0403110225.313772a3@posting.google.com>... > >> > I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the > >> > fmax has shot up to 430MHz overall and the 2 larger blocks besides > >> > blockram are in the 550MHz ballpark. > >> > >> If true, then Wow! Your FPGA based CPU is faster than 0.13 ASIC CPUs. > >> > > > >Only because of HT and 3 level of LUT logic. HT means the pipelines > >are mostly independant but cyclic like the spokes of a wheel. Just > >like DSP (which is what I have been doing alot of over the years since > >my Inmos days). > > Actually, thats not hyperthreading/SMT, thats > interleaved-multithreading or C-slowing. See Chapter 11 and Appendix > B: > > http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf Any particular reason you didn't use the term 'barrel processor'? C-slow appears to be either a very new or very obscure term. > > It is a big win in FPGA-based CPUs if you can't get your forwarding > path small enough. -- Sander +++ Out of cheese error +++Article: 67497
On Fri, 12 Mar 2004 20:47:17 -0000, "Leon Heller" <leon_heller@hotmail.com> wrote: >Pulsonix will provide a full 30 day license on request. Wouldn't be any good for me, at least. I've had stacks of 30 day evaluation copies of all sorts of software over the years but the continual problem I face is in not being able to spare enough time in one month between first trying to use the program and its expiry to be able to produce anything useful or even form any constructive opinions. It would be far better IMV if the developer provided say a 72 hour limit on actual use (tallying up several seperate periods of such use) rather than a plain 30 days to expiry where during most of that time, we've more pressing matters to attend to and the clock's ticking away with the program laying idle on hard disk. -- The BBC: Licensed at public expense to spread lies.Article: 67498
Hello Chi! > I'm using Nios Development Kit (general purpose, APEX). Is it > outdated? IMO yes! I'm still using it because I have designed my own APEX board, and still have stock of the PCBs and APEX chips! > It seems hard to find reference. All references are talking > about Cyclone and Stratix. IMO you should not use APEX for new designs. I believe Cyclone is cheaper and that Nios runs significantly faster on it (sorry, I can't find specific figures at the moment). That said, I'm waiting for Nios II and Cyclone II before designing my next Nios board. > I even could not find the software development tutorial for APEX. Did you not get a complete kit? Mine came with hardware, software and tutorials. I was up and running in ten minutes. > I'm new to this tool suit. Does anyone > have good suggestions to shorten time to hand on? Thanks! Have you tried the following (Nios 2.1) tutorial? http://www.altera.com/literature/tt/tt_nios_hw_apex_20k200e.pdf You could well have problems if your versions of Nios do not match those used in the tutorial, or with tutorials targeting Cyclone or Stratix. For example, the hexout2flash utility has been changed on the Nios 3.x release, such that its default target address matches the Cyclone and Stratix dev kit boards. Use it the way the tutorial tells you and your attempts to program a configuration into flash will lockup and/or fail :-( If you have Nios 3.1 type "hexout2flash" in the bash shell for details. I'm no expert, but I've used Nios 1.1, 2.1 & 3.1 . Let me know details of your Nios and Quartus versions (preferably posted here) and I'll try to compile some quick-start suggestions. Regards, TerryArticle: 67499
not much of a choice...i got the codes without simulator or test vectors from those chinese en- gineers...those people tend to be quite wishy-washy, they put synopsys directives, incomplete case statements, inconsistant coding styles here and there...not much of a choice as now i am targetting it for FPGA but it seems a function call in a case statement gave me 200 after adding two 0s, so I am suspecting the directives, but it will take few hours to do a P&R respin. Kelvin "Kent Dickey" <kadickey@alumni.princeton.edu> wrote in message news:c2tfbf$210944$1@ID-174604.news.uni-berlin.de... > In article <40512826@news.starhub.net.sg>, Kelvin @ SG <kelvin8157@hotmail.com> wrote: > >I am wondering whether XST handles // synopsys parallel_case? > > > >Plus, How do I know XST has taken in the // synthesis parallel_case? I > >didn't see any such > >information in the synthesis transcripts with either //synopsys or > >//synthesis... > > > >Best Regards, > >Kelvin > > My advice is to not use the parallel_case directive. If you specify all > the cases, it's redundant. If you haven't, then your synthesis tool will > generate hardware that will not match your simulator. This is usually > a bad thing to do. > > Just specify all of the cases explicitly or write your code differently. > > For similar reasons, avoid Verilog's casex in synthesized code as well. > > Kent
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z