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hello all, can you explain me the meaning of "EDIF".Article: 67526
Hello, sirohi_rajiv@rediffmail.com wrote: > hello all, > can you explain me the meaning of "EDIF". EDIF = Electronic Design Interchange Format http://www.edif.org/about.html http://www.edif.org/introduction.html Marc -- Réponse par email http://cerbermail.com/?C9OVeUlzPc Answer by email http://cerbermail.com/?C9OVeUlzPcArticle: 67527
I think that it is a supply susceptability problem we are experiencing. "DaS" <none@nospam.com> wrote in message news:40502C56.2000300@nospam.com... > Hi, > > not with Cyclone, but with Excalibur. Not really the same thing, but > similar : device makes a new configuration every n secondes. > Asked help from Altera, but we don't still have found why. > We still go on searching : bug on device ? On our design ? On suplly > (they seem to be stable). > We don't know. > Let me know if you find for your Cyclone. > > Damien. > > > rAinStorms a écrit: > > Hi, > > > > I am wondering if anyone out there has experienced random spurious > > reconfiguration issues with Cyclone devices? > > We have an issue where the FPGA in our design configures correctly but then > > a short time later for apparently no reason goes int a reconfig cycle > > and stays there (as its not loaded). I suspect that there might be an issue > > with our power supply design but still have not isolated the problem ... and > > on the off-chance this is a larger issue, it seems like a good idea to see > > whether other people have experienced similar problems. > > > > Thanks, > > Chris > > > > >Article: 67528
Markus Meng wrote:
> Hi all and hi Xilinx,
>
> actually dealing with gigabit transmission using
> external SERDES devices from TI, I just wonder if
> the app note xapp607 is just paper-and-vhdl-work,
> or if it is based on measurements on a real design.
>
> The general advices are 'nice', however at that frequency
> in multigigabit transmission, I would like to know
> a little bit more about the clock source for the
> GTX_CLK. According to the datasheet from TI clock
> jitter is a non-trivial requirement.
>
> If Xilinx has really build such a system and made some
> measurements, what kind of clock sources have been used?
>
> It seems to be obvious, that no DCM is involved in the
> design, however it is somehow not clear enough stated,
> that it will not work for more than half an hour or so,
> before failure if the GTX_CLK is coming out of a DCM ...
>
> Any comments on this?
>
> Have a nice weekend
> Markus
Howdy Markus,
The copy of XAPP607 that I have explains that the note is based on a
real-world eval board called the "XLVDS demonstration board," so I'm not
sure why you'd think it's a paper only design.
Also, page 13 of the copy that I have (v1.0) indirectly says that
GTX_CLK should not come from a DCM.
If you are using a device without DDR flops (like a Spartan IIE or
less), you'd want to follow the advice of the last sentence on that
page, where is says that the clock from the external oscillator should
be routed directly to both TLK and FPGA devices. You can do this as
long as each leg of the traces going to the two devices are close to the
same length.
Good luck,
Marc
--
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Article: 67529rickman <spamgoeshere4@yahoo.com> wrote in message snipped > You might consider building a board that has an FPGA and can plug into a > socket A, 478 or one of the other standard x86 sockets. Then you can > run your CPU in any motherboard. Go with a socket 940 and you can > design your own memory controller! > > -- Now thats an interesting idea, but I think it would be plagued with IP difficulties and patents. Also most of these sockets are supporting busses that might already be hard to meet, esp the AGP, and the DRAM controller is now in the bridge instead of the cpu. For what its worth there are new Amigas out there that are almost regular x86 mobo chipsets but with a PPC there instead, and far more pricey than Soyos. Still an older socket for p100, might work. There is no reason in principal why an x86 partial compatible isn't doable, dog slow, but there are 86 cores. Now a slow compatible core could just front a much faster risc core as AMD & Intel already do, but they never opened up the internal rich register set arch with a separate polished 32b ISA that could later deprecate the old baggage. The ISA register renaming they include works well enough to recompile 8regs on the fly to the 40 odd regs, but better to have a full regular RISC ISA. Well AMD does have the new opcodes for 64b but they are hanging off the variable length opcodes, nicer if there was something like a Thumb switch saying , "I am all grown up now". Also take a look at the Freedom cpu, I don't buy the religion but they had some results, I can't find the speed. The modules I would like to build will look alot like credit card size TRAMs, a cpu FPGA and something else. Once a great business for Inmos too and the early FPGA players. regards johnjakson_usa_comArticle: 67530
Hi, I've got a design with a VME core(IP) which simulates just fine. However, the real chiponly works occasionallyafter powerup, if at all. The DONE pin goeshigh OK. Tried to reconfigure to noavail. Anyone any ideas please? -- Niv. Remove **SPAM_OFF** to reply.Article: 67531
i have downloaded at link for 3.0 .. but that is always the 2.1 version !! Pierre "Paul Burridge" <pb@osiris1.notthisbit.co.uk> a écrit dans le message de news:usk45010mu8mtvfqs26b238t6a0k8o5d00@4ax.com... > On Fri, 12 Mar 2004 20:47:17 -0000, "Leon Heller" > <leon_heller@hotmail.com> wrote: > > >Pulsonix will provide a full 30 day license on request. > > Wouldn't be any good for me, at least. I've had stacks of 30 day > evaluation copies of all sorts of software over the years but the > continual problem I face is in not being able to spare enough time in > one month between first trying to use the program and its expiry to be > able to produce anything useful or even form any constructive > opinions. > It would be far better IMV if the developer provided say a 72 hour > limit on actual use (tallying up several seperate periods of such use) > rather than a plain 30 days to expiry where during most of that time, > we've more pressing matters to attend to and the clock's ticking away > with the program laying idle on hard disk. > -- > > The BBC: Licensed at public expense to spread lies.Article: 67532
"ABCDEF" <F5BJR@10online.fr> wrote in message news:c2vb13$au7$1@apollon.grec.isp.9tel.net... > i have downloaded at link for 3.0 .. > > but that is always the 2.1 version !! This has been raised on the Pulsonix User Group forum. I've checked and the download is really Version 3.0 Build 1563. They updated the web page in a hurry and got the version number wrong when they rebuilt the software. I've told them about it and they should be rectifying it on Monday. LeonArticle: 67533
Hi, Have a look at micro controller design from Xilinx, they have a GPIO connected to the OPB BRAM bus with opb_bram_if controller Ram Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote in message news:<Pine.LNX.4.58-035.0403112220270.21663@unix45.andrew.cmu.edu>... > Hi, > I have been creating a design extensively in hardware and I would like to > be able to have a powerPC write to block RAMs that are in my HW design. > Can someone point me in the right direction. > > What sort of bus do i need to create? > > Any pointers would be much appreciated. > > Thanks > > MattArticle: 67534
Hi 1. Write your desing in VHDL 2. Synthesis your desing for specific part 3. Creat UCF file 4.Run MAP, par 5. Create Bit stream download to the board. Search xilinx website for tutorials. Ram sirohi_rajiv@rediffmail.com (sirohi_rajiv@rediffmail.com) wrote in message news:<c8cb1645.0403130224.632294d2@posting.google.com>... > hello all, > i want to download my program using Xilinx Spartan 4k 4.2 > on xilinx xc4010e fpga board by programming in vhdllanguage. > as i am new to this field i need your help . > please tell me the steps in details. > thanking you.Article: 67535
hum ?? Current download version is Revision 3.0 :: Build 2150 :: 10-Mar-2004 not found 36 mo and not 51 mo ?? Pierre "Leon Heller" <leon_heller@hotmail.com> a écrit dans le message de news:405335cf$0$28269$cc9e4d1f@news.dial.pipex.com... > > "ABCDEF" <F5BJR@10online.fr> wrote in message > news:c2vb13$au7$1@apollon.grec.isp.9tel.net... > > i have downloaded at link for 3.0 .. > > > > but that is always the 2.1 version !! > > > This has been raised on the Pulsonix User Group forum. I've checked and the > download is really Version 3.0 Build 1563. They updated the web page in a > hurry and got the version number wrong when they rebuilt the software. I've > told them about it and they should be rectifying it on Monday. > > Leon > >Article: 67536
"ABCDEF" <F5BJR@10online.fr> wrote in message news:c2vgnh$lpu$1@aphrodite.grec.isp.9tel.net... > hum ?? > > Current download version is Revision 3.0 :: Build 2150 :: 10-Mar-2004 > > not found 36 mo and not 51 mo ?? I downloaded the demo, it acts as a full version with the license file. It is definitely identified as version 2.1 Build 1563. Leon LeonArticle: 67537
> Basically a PC - the x86. Yep. > I would probably say that either A Nios or X MB is fine for what you > propose. Check their respective web zones to see what looks more > comfortable and then compare with boards that look like a PC, there > are several I am thinking. I was am maybe tempted by the XESS board > that also looks like a PC -x86. The XESS board was the first board I considered (this was some while ago so I don't remember what the problems were) but I remember thinking that most of the issues it had should not exist for a board of that cost. My price range has changed recently (from around $300 to a max of $1000) so I'll take a look at that. They came out with a new version of their high end board that might be good. > Do go for a board that has the largest FPGA that the free SW will > allow, thats about 1/3 of way from the bottom up in any family. Check > free Webpack or Quartus 1st to see limit. Also try these SWs 1st > before you buy the board, that will lock you in for sure. After you > choose the tool, the board will be safe investment for a while. Most > of these boards will only have a part small enough to work with free > SW or even smaller (too much cost saving). That would rule out MJLs Stratix as it requires the expensive software. Good point. > to get the faster bigger part, but most of these PC-x86 boards I see > seem to use Spartan2, so look for E version & get extra blockrams. > There are specific boards made for the Nios & MB markets that don't > look like the PC-x86 thing that are probably better for serious work > on those. So the Spartan2E's will give enough performance to make the system usable on a basic level? > The really good stuff that uses the v2 or v2pros or the Stratix won't > come to you looking like a PC -x86, instead it will look like a PCI64 > or some other serious factor with rockets and lasers and other wonder > bits. Those parts don't go to the <1K experimenting crowd. Although I ruled this out due to expensive development software, check out this link: http://www.mjl.com/product/mjlstratix.asp It has a pretty standard motherboard layout for a stratix for only $795. > good luck Thanks!Article: 67538
> the bottleneck. Remember, you can put a lot of logic on these chips, > but you won't ever get much cache in comparison to the 512 MB and 1 GB > they are making today in CPUs. I'd like a CPU with 1GB of cache but that doesn't seem possible with today's technology. I only have 1GB of total memory in my system (plus 1MB of cache on each of my Opterons). What kind of cache could be expected to fit into an FPGA today? > You didn't say how much extra money it costs! In general, I don't think > you will find your designs will fit or run better in the higher priced > families. The high dollar parts mainly are either larger, or they have > special features (like very high speed serial IO) that you likely don't > need. Just make sure your FPGA is large enough for the design you are > building. It is $100 more for the Stratix and 256K of SRAM. The devices both have about the same capacity but I was wondering about the speed grade, if that is even an issue. > If you want to wait for the Spartan 3, be prepared for a long wait. > They have been promising chips for months now and most people are still > waiting. Don't blame BurchED, they likely aren't getting the chips they > were promised. Yes. I understand that there have been problems. I don't mean to blame BurchED but I don't really want to wait forever unless it will offer a big payoff in terms of performance. > You might consider building a board that has an FPGA and can plug into a > socket A, 478 or one of the other standard x86 sockets. Then you can > run your CPU in any motherboard. Go with a socket 940 and you can > design your own memory controller! That's a really interesting idea! That would be the ideal situation (just think of an FPGA board with PCI slots!!!). I've been doing some experimenting with socket 940 (my home workstation is a dual Opteron machine) and I find the concept really interesting. However, if I were to do this with an FPGA I would most likely choose something like Socket A. This approach would save a lot of money in terms of board costs (the FPGAs, especially parts like the Cyclone and Spartan are really cheap) because the FPGA is really the only thing you'd need to buy (not counting the socket interface). The motherboards are made avaliable cheaply from many retailers. It would really prevent getting locked into a certain technology (and its vendor). My resources are limited as to actually creating my own PCB, do any of you know of any readily avaliable PC socket interfaces for FPGAs? That would be a really interesting concept to explore! Thanks!Article: 67539
John wrote: > > > the bottleneck. Remember, you can put a lot of logic on these chips, > > but you won't ever get much cache in comparison to the 512 MB and 1 GB > > they are making today in CPUs. > > I'd like a CPU with 1GB of cache but that doesn't seem possible with > today's technology. I only have 1GB of total memory in my system (plus > 1MB of cache on each of my Opterons). What kind of cache could be > expected to fit into an FPGA today? Yeah, I mixed up my kB, MB and GB. You know what I meant... :) > > You didn't say how much extra money it costs! In general, I don't think > > you will find your designs will fit or run better in the higher priced > > families. The high dollar parts mainly are either larger, or they have > > special features (like very high speed serial IO) that you likely don't > > need. Just make sure your FPGA is large enough for the design you are > > building. > > It is $100 more for the Stratix and 256K of SRAM. The devices both > have about the same capacity but I was wondering about the speed > grade, if that is even an issue. How important is a few extra MHz? If you get 200 MHz on the cheaper system and 250 MHz on the more expensive, is that really an issue? I don't think anyone can tell you how much difference a chip family will make because of the design specific variables. The new Stratix family coming out later will have a new architecture that should be *much* faster for a lot of things. In reality, do you need hardware until you have a design working? You can work with the tools and run simulations for quite a lot of development until you are ready to download into hardware. Until you optimize for a given architecture (which should be the last thing you do, even after you test on hardware) you can move your design to *any* platform. > > If you want to wait for the Spartan 3, be prepared for a long wait. > > They have been promising chips for months now and most people are still > > waiting. Don't blame BurchED, they likely aren't getting the chips they > > were promised. > > Yes. I understand that there have been problems. I don't mean to blame > BurchED but I don't really want to wait forever unless it will offer a > big payoff in terms of performance. > > > You might consider building a board that has an FPGA and can plug into a > > socket A, 478 or one of the other standard x86 sockets. Then you can > > run your CPU in any motherboard. Go with a socket 940 and you can > > design your own memory controller! > > That's a really interesting idea! That would be the ideal situation > (just think of an FPGA board with PCI slots!!!). I've been doing some > experimenting with socket 940 (my home workstation is a dual Opteron > machine) and I find the concept really interesting. However, if I were > to do this with an FPGA I would most likely choose something like > Socket A. > > This approach would save a lot of money in terms of board costs (the > FPGAs, especially parts like the Cyclone and Spartan are really cheap) > because the FPGA is really the only thing you'd need to buy (not > counting the socket interface). The motherboards are made avaliable > cheaply from many retailers. It would really prevent getting locked > into a certain technology (and its vendor). My resources are limited > as to actually creating my own PCB, do any of you know of any readily > avaliable PC socket interfaces for FPGAs? That would be a really > interesting concept to explore! Not off the top of my head. I think these sockets are PGA, so there should be adapters available from ET and Ironwood, but they will be pricy, like a few hundred dollars. You might start out with something simpler and cheaper like socket A or 370. Fewer pins means fewer dollars. That is true for both the adapters and the FPGAs. You can always go big later. For starters, I would go small initially. You might also consider getting a passive backplane and putting an FPGA on a PCI board. You can get nearly any peripheral on PCI for the FPGA to control. The only real problem with any of these approaches, is that designing a PCB for a high speed interface is not trivial. It is not hard, but you have to do your homework and make sure you do the layout correctly. There is a lot more to it than just connecting the dots. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67540
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<rdx4c.1044$u%1.166050@news02.tsnz.net>... > Stewart Smith wrote: > > <snip> > > Thank you for taking time to respond > > Have looked into the link you suggested and, no problem for me to use > > this type of device, in fact they have them in stock at uni which is > > handy. This definitely seems a step in the right direction. > > You could also check if they have, or can easily get (Digikey?), the > Atmel ATF750CL. > > http://www.atmel.com/dyn/resources/prod_documents/doc0776.pdf > > That has the same package(s) and tool flow as the 20V8 you use now, > but has 20 D/T registers, and allows multiple clocks. > (Also lower standby, but that's not likely to be too critical). > -jg Ah, sorry about the mis-understanding with 7497 (although quite liked it). I seem to be getting myself a bit confused with what goes where in each pld. In PLD 1 which would be the freqDiv I should have a four bit up/down/hold counter to divide the external clock source, the outputs of this is to be the source for a 4-bit rate divider in pld 2 which in turn contains the phase switching along with a merge bit from the phase switch sequence that is fed back externally as its clk source. I apologise if I seem a bit dozy on this but it is all relatively new, I've only done a 7 seg display before this all seems quite a long way from that. It will take me a good few days to investigate your suggestion on Atmel ATF750CL. We're off uni until weds and then getting hold of the tutor could be hard as well. But please keep your suggestions coming I am finding them intensely interesting even if sometimes it takes me a day or so understand them. I will also try to look into the flip-flop and adder idea as well just in case I don't manage to master this PLD method, but this is the preferred route. Thanks StewartArticle: 67541
Hi Antti, > has anyone have had any luck with Quartus II ver 4? > > Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line: > 5797 number_of_res == 0 || number_of_res == 1 > (Fitter pre-processing) > Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition Version 4.0 works fine for me. I'm not saying I'm not getting any errors, but that's more in exotic cases (turning all gate level retiming optimizations on plus specific timing constraints plus low on memory on one (huge) specific design) than what you describe. Judging by all the errors you've been getting it looks like your registry is fscked up, or your sysadmin has not given Quartus 100% rights to change the registry. Drop our local Altera or disti FAE a line and see what he can come up with. Best regards, BenArticle: 67542
Hi Pawel, > I drive 16 LED's, 10mA per each. I don't know if i need any external > dirver (some HC chip) or not. At 10mA and 16 LEDs you shouldn't worry about a thing. Altera FPGAs can easily drive and sink 160mA. I've even seen them draw around 3A worth of I/O (200x15mA) with a heatsink and a bit of active cooling without failing for one month. Best regards, BenArticle: 67543
Stewart Smith wrote: > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<rdx4c.1044$u%1.166050@news02.tsnz.net>... > >>Stewart Smith wrote: >> >><snip> >> >>>Thank you for taking time to respond >>>Have looked into the link you suggested and, no problem for me to use >>>this type of device, in fact they have them in stock at uni which is >>>handy. This definitely seems a step in the right direction. >> >> You could also check if they have, or can easily get (Digikey?), the >>Atmel ATF750CL. >> >>http://www.atmel.com/dyn/resources/prod_documents/doc0776.pdf >> >> That has the same package(s) and tool flow as the 20V8 you use now, >>but has 20 D/T registers, and allows multiple clocks. >> (Also lower standby, but that's not likely to be too critical). >>-jg > > > > Ah, sorry about the mis-understanding with 7497 (although quite liked > it). I seem to be getting myself a bit confused with what goes where > in each pld. > > In PLD 1 which would be the freqDiv I should have a four bit > up/down/hold counter to divide the external clock source, the outputs > of this is to be the source for a 4-bit rate divider in pld 2 which in > turn contains the phase switching along with a merge bit from the > phase switch sequence that is fed back externally as its clk source. You will need to be carefull in that a 20V8 can have only a single clock - that will restrict your options a little. Solutions are to put one major function block per PLD, or add a Clock enable Logic to the Phase drives (so simulates two clock sources), or move to the ATF750CL. > I apologise if I seem a bit dozy on this but it is all relatively new, > I've only done a 7 seg display before this all seems quite a long way > from that. If it was too easy, you would not learn anything :) Coding wise, it is not much more complex than 7 Seg Disp/counters, but you do have multiple frequency domains and that can be tricky to keep track of... > It will take me a good few days to investigate your suggestion on > Atmel ATF750CL. We're off uni until weds and then getting hold of the > tutor could be hard as well. Just think of the ATF750CL as 2 1/2 20V8's, but with toggle FF option, and better clock options. -jgArticle: 67544
Leon Heller posted in sci.electronics.cad , in article <4052d7a8$0$10149$cc9e4d1f@news.dial.pipex.com>, at Sat, 13 Mar 2004 09:43:04 - 0000: > If you want another shock look at this abortion: > > http://www.otl.co.uk/ > > The developer seems to have a very high opinion of it, but it doesn't even > have rubber-banding on the connections! And it does not run on Windows 98 (yeah, I know Kevin will flame me after this). For other shock i'd look at VUTRAX, that has a GUI which I would call a CUI (Confusing User Interface), IMHO. Their help system is a pain on the a**. -- Chaos Master® - Porto Alegre, RS, Brazil irc.brasnet.org - #xlinuxnews and #poa marreka.no-ip.com (ainda não pronto) LRU #327480 "quotes with no meaning, are meaningless" - Kevin AylwardArticle: 67545
"Chaos Master" <wizard_of_yendorIHATESPAM@hotmail.com> wrote in message news:c30b4j$22gb0t$3@ID-88878.news.uni-berlin.de... > Leon Heller posted in sci.electronics.cad , in article > <4052d7a8$0$10149$cc9e4d1f@news.dial.pipex.com>, at Sat, 13 Mar 2004 09:43:04 - > 0000: > > > > If you want another shock look at this abortion: > > > > http://www.otl.co.uk/ > > > > The developer seems to have a very high opinion of it, but it doesn't even > > have rubber-banding on the connections! > > And it does not run on Windows 98 (yeah, I know Kevin will flame me after this). > > For other shock i'd look at VUTRAX, that has a GUI which I would call a CUI > (Confusing User Interface), IMHO. Their help system is a pain on the a**. A friend of mine has used the original DOS version of Vutrax for about 25 years. It's probably because he comes from Yorkshire. 8-) I find it very strange that several PCB packages don't conform to the usual intuitive way of selecting objects - just put the pointer on them and click the mouse button. That's the way most other applications work these days. LeonArticle: 67546
On Sun, 14 Mar 2004 02:44:23 -0000, the renowned "Leon Heller" <leon_heller@hotmail.com> wrote: > >"Chaos Master" <wizard_of_yendorIHATESPAM@hotmail.com> wrote in message >news:c30b4j$22gb0t$3@ID-88878.news.uni-berlin.de... >> Leon Heller posted in sci.electronics.cad , in article >> <4052d7a8$0$10149$cc9e4d1f@news.dial.pipex.com>, at Sat, 13 Mar 2004 >09:43:04 - >> 0000: >> >> >> > If you want another shock look at this abortion: >> > >> > http://www.otl.co.uk/ >> > >> > The developer seems to have a very high opinion of it, but it doesn't >even >> > have rubber-banding on the connections! >> >> And it does not run on Windows 98 (yeah, I know Kevin will flame me after >this). >> >> For other shock i'd look at VUTRAX, that has a GUI which I would call a >CUI >> (Confusing User Interface), IMHO. Their help system is a pain on the a**. > >A friend of mine has used the original DOS version of Vutrax for about 25 >years. It's probably because he comes from Yorkshire. 8-) > >I find it very strange that several PCB packages don't conform to the usual >intuitive way of selecting objects - just put the pointer on them and click >the mouse button. That's the way most other applications work these days. > >Leon Backward compatibility has its downside. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 67547
Leon Heller <leon_heller@hotmail.com> wrote in message news:4053c705$0$28271$cc9e4d1f@news.dial.pipex.com... [clip] > A friend of mine has used the original DOS version of Vutrax for about 25 > years. It's probably because he comes from Yorkshire. 8-) [clip]. > > Leon > It's tight fisted sods like him that gives the rest of us poor buggers a bad name :-) regards john (born and bred in gods own)Article: 67548
"Kelvin" <kelvin8157@hotmail.com> wrote in message news:<c2tkqn$3kd$1@mawar.singnet.com.sg>... > not much of a choice...i got the codes without simulator or test vectors > from those chinese en- > gineers...those people tend to be quite wishy-washy, they put synopsys > directives, incomplete > case statements, inconsistant coding styles here and there...not much of a > choice as now i am > targetting it for FPGA but it seems a function call in a case statement gave > me 200 after adding > two 0s, so I am suspecting the directives, but it will take few hours to do > a P&R respin. > > Kelvin --- <snip> ---- As per the following link, XST should be able to handle synopsys parallel and full case directives - http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap05/xst05009.htm I have personally not used XST, so cannot confirm this, but you can check the actual logic being synthesised. Preferably, stay away from parallel/full case directives as they can cause more harm than do good ...... Hope this helps, Vikram.Article: 67549
> Not off the top of my head. I think these sockets are PGA, so there > should be adapters available from ET and Ironwood, but they will be > pricy, like a few hundred dollars. You might start out with something > simpler and cheaper like socket A or 370. Fewer pins means fewer > dollars. That is true for both the adapters and the FPGAs. The more research I'm doing the less likely this idea seems. I searched Ironwood's online catalog and I couldn't find anything for either of those sockets. Also, is it practical to plug an FPGA directly into the motherboard by converting the package to a common socket or would it be better to put it on a PCB complete with extra hardware such as: *SRAM for some sort of L2 cache *JTAG port or some other programming interface *Flash memory for bitstream storage *CPLD for device management (loading config from flash) Also, I'm not that familiar with the operation of a standard PC motherboard. It seems that there would need to be a bit of board reconfiguration in order to get the board to boot a chip based on another architecture. As for the idea of putting it on a PCI card, although it would allow for integration into a PC motherboard, how much of the board would it actually be able to control? Could the board even be properly booted without a CPU in the main socket? If you have any suggestions, feel free to let me know. Also, as the posts have suggested, I should probably pick a vendor based on design software rather than device capability as they (Altera and Xilinx) both seem to be offering good products at comparable prices. I've been doing some reading and comparing the free "Web" editions of the design suites but I was wondering if anyone here would like to share the reason for their choice. Thanks!
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