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"Antti Lukats" <antti@case2000.com> wrote in message news:<c2nrp7$2b5$06$1@news.t-online.com>... > "Subroto Datta" <sdatta@altera.com> wrote in message > news:QmG3c.57551$yJ6.24061@newssvr33.news.prodigy.com... > > Hi Antti, > > snipping have you tried cleaning the registry before hand There are a couple of tools to do this. regclean IIRC I am sure that installs done when the registry is not kosher have led to problems in the past too for me, I clean it regularly anyway since so many SW tools leave it in a mess. Sometimes when it say do you want to reboot, you have to. regards johnjakson_usa_comArticle: 67376
Dennis Kr=F8ger wrote: > On Wed, 10 Mar 2004 04:02:23 -0800, sirohi_rajiv@rediffmail.com wrote: >>i am working with xilinx ise webpack 6.2. >>i want to know that how i can upload my program on "xilinx xc4010e" kit= =2E >=20 > You say that it is a XC4010E kit...=20 I'd be very surprised if Webpack will even synthesise for such an old=20 part?? Maybe that's the root of the problem? Regards, JohnArticle: 67377
Thank you very muchArticle: 67378
Hi Antti,
The Quartus Web Edition License and Nios Eval license are separate. I
have forwarded your reply to a Applications engineer to help you out on this
as it will be a quicker process, instead of trying to resolve it through the
newsgroup. If you can do send me by email the Quartus Web Edition License
and the Nios eval license files.
Regards,
- Subroto Datta
Altera Corp.
"Antti Lukats" <antti@case2000.com> wrote in message
news:c2nrp7$2b5$06$1@news.t-online.com...
> "Subroto Datta" <sdatta@altera.com> wrote in message
> news:QmG3c.57551$yJ6.24061@newssvr33.news.prodigy.com...
> > Hi Antti,
> >
> > Just to make sure that everything is on the Altera web site is OK, I
> did
> > the following:
> >
> > 1. Downloaded the Quartus II 4.0 Web Edition ( used the
> > quartuii_40_web_edition_single.exe download, all 144.7 MB of it),
> installed
> > it on my PC,
> > 2. Got myself a license from the Altera Licesning Center,
> > 3. Compiled a one wire design, (input followed by lcell followed by
> output),
> > for the APEX20KE, Cyclone, Stratix, and MaxII families, both with Auto
> > Device Selection and Specifying a fixed Device (from the list shown in
the
> > Assign Device Box).
> > 4. Compiled the fir_filter Tutorial design
> >
> > All without any problems.
> >
> > Based on your description of the internal error, I believe your
> installation
> > was incomplete, and that some of your device databases may not been
> > installed. This may happen if you ran out of disk space during the
> > installation, or your downloaded image was corrupt. It is probably the
> > former. Give the installation a try again, and send me the results.
>
> It was nothing wrong with during the installation, 30GB DISK, 2GB RAM
> but there was Q v3 what was auto unistalled, before the Q v4 installed
> and afterwards I started Q v4 without re boot, and got results as I
> described.
> after reboot, I also got errors, but then changed device type what was
> Stratix II
> (even though I think I was trying to wire only in MAX-2)
> anyway, it works now.
>
> but the first frustration was real.
> now having again problems with NIOS eval license :(
> got it working in Q v3 and now it again doesnt work.
> Quartus Licensing says all OK, SOPC builder does all OK,
> but quartus compile complains about license missing.
> oh well need to fight again!
>
> Antti
>
>
>
>
>
>
>
>
>
>
>
Article: 67379The design is 100% routed but still doesn't meet timing until the number in parentheses is zero. The router has to keep ripping up and rerouting paths until timing is met. -Kevin "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:404fbb0f$1@news.starhub.net.sg... > Hi, there: > > I have been confused why ISE6 always spend a lot of time after it has > completed routing... > On the routing log, it seems at Phase 7, it accomplished all routing > already...but why Phase 8? > > Best Regards, > Kelvin > > > > Phase 9.27 > Phase 9.27 (Checksum:55d4a77) REAL time: 5 mins 4 secs > > Writing design to file switch_top.ncd. > > Total REAL time to Placer completion: 5 mins 7 secs > Total CPU time to Placer completion: 5 mins 3 secs > > > Phase 1: 13137 unrouted; REAL time: 5 mins 10 secs > > Phase 2: 12564 unrouted; REAL time: 5 mins 57 secs > > Phase 3: 3148 unrouted; REAL time: 6 mins 3 secs > > Phase 4: 3148 unrouted; (22384) REAL time: 6 mins 4 secs > > Phase 5: 3161 unrouted; (22208) REAL time: 6 mins 5 secs > > Phase 6: 3161 unrouted; (22208) REAL time: 6 mins 6 secs > > Phase 7: 0 unrouted; (22732) REAL time: 6 mins 27 secs > > Writing design to file switch_top.ncd. > > Phase 8: 0 unrouted; (22195) REAL time: 10 mins 24 secs > > >Article: 67380
I know; this is off-topic: I can't figure out why, when there is a brief power outage, my answering machine loses time information but retains voice messages. I guess the messages must be stored in FLASH. Is it just too much of a pain to write the time into FLASH as well? If it can't be written into FLASH, couldn't it use a small cap to back up the volatile RAM? Maybe I shouldn't expect too much for $25. -KevinArticle: 67381
I've been reading about CORDIC engines (in a paper by Andraka) and I was wondering if they are still relevant in parts with a lot of blockRAM. I've always used sin, cos, and arctan lookup tables in blockRAM, which yield two results per blockRAM per cycle in a Xilinx V2 (each 18 bits with 88 millidegree phase resolution), and I was wondering if there is a compelling advantage of a CLB-based CORDIC engine in, for example, a V2 part. I know the CORDIC can multiply as well, but the V2 parts also have embedded multipliers. Perhaps those big ROMs and multipliers are making me lazy. -KevinArticle: 67382
Except that if you are in an invalid state, you have no assurance that
the terminal state will ever be reached. FSMs are not counters. They
interact with the environment and illegal states can get them
deadlocked.
Ray Andraka wrote:
>
> You can do that by having the terminal state assert a synchronous reset to the entire
> state machine with considerably less logic.
>
> Jim Granville wrote:
>
> > Ray Andraka wrote:
> >
> > > Peter,
> > >
> > > Consider the case where you have 1 input high to one of your luts, and 2 inputs
> > > high to another lut. It is clearly an illegal state, as it has two extra '1' bits,
> > > but it will be detected as OK by your circuit because exactly one LUT is indicating
> > > one input on. Each group of four requires two outputs to distinguish 0,1 or more
> > > than 1 input on.
> >
> > I think Peter was partly correct. You can protect/correct a 16 stage
> > One-Hot engine against illegal states with 5 LUTs, but it will not
> > recover in a single clock cycle.
> > Simplest topology is to have 15 shifters, and #16 loads a HI ONLY if
> > all Prev15 are 000000000000000, if not, it simply waits until
> > the bogus ones ripple out.
> >
> > -jg
> >
> > >
> > > Peter Alfke wrote:
> > >
> > >
> > >>Eh, what? Unfortunately anonymos...
> > >>
> > >>Each first level LUTs detects (output High) that exactly one of its inputs
> > >>is High.
> > >>The second tier LUT detects that exactly one of the first-tier LUT outputs
> > >>is high, which mans that there is exactly one High input.
> > >>Agreed ?
> > >>Peter Alfke
> > >>
> > >>
> > >>>From: user@domain.invalid
> > >>>Newsgroups: comp.arch.fpga
> > >>>Date: Tue, 09 Mar 2004 05:24:26 GMT
> > >>>Subject: Re: Release asynchrounous resets synchronously
> > >>>
> > >>>Peter Alfke wrote:
> > >>>
> > >>>>LUTs are very efficient "illegal state" detectors.
> > >>>>Let's say you have a 16-state one-hot machine. Four LUTs can each detect
> > >>>>"exactly one of my inputs is High", and a fifth LUT does the same with the
> > >>>>four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it
> > >>>>from there...
> > >>>
> > >>>Eh, what? So the first tier LUT compute f, where
> > >>>f(a,b,c,d) = 1 iff a+b+c+d = 1, else 0.
> > >>>For the 5th LUT we have the same property that a legal 16-state would
> > >>>map exactly one of the four first tier LUTs to 1, thus it sounds like
> > >>>what you have in mind is something like this:
> > >>>
> > >>>f({f(s[3:0]), f(s[7:4]), f(s[11:8]), f(s[15:12])})
> > >>>
> > >>>but this could accept states like 16'b1111_1110_1100_0001.
> > >>>
> > >>>I don't see how you can detect legal states with only five four-input LUTs.
> > >>>
> > >>>
> > >>>Peter, the FPGA reset question has come many times. What does Xilinx
> > >>>recommend in general? Async-reset+Sync-release, all-sync, or all-async?
> > >>>Which uses fewest resources?
> > >>>
> > >>>Thanks,
> > >>>
> > >>>Tommy
> > >>>
> > >
> > >
> > > --
> > > --Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930 Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
> > >
> > > "They that give up essential liberty to obtain a little
> > > temporary safety deserve neither liberty nor safety."
> > > -Benjamin Franklin, 1759
> > >
> > >
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 67383Stephen Pelc wrote: > > On Thu, 26 Feb 2004 14:25:11 -0500, rickman <spamgoeshere4@yahoo.com> > wrote: > > >> Mops can generate PowerPC code. As for embedded PowerPC I was surprised > >> that I didn't see a SwiftX or VFX implementation on their websites > >> although both supported ColdFire. > > > >I believe that is because both companies are reactive rather than > >proactive. They port to a new platform when they are paid to do it. > Sorry Rick, but it isn't always true. We certainly port when paid > to do so, but we also do it when we like the CPU. The ARM and > Coldfire VFX ports were done on our own dime. There are several > CPUs we've done cross compilers for that I wish we hadn't wasted > time on. We just don't have the budget to do every CPU on the > market. In retrospect I consider the decision to support ARM > rather than PPC a good one. > > >They don't speculate on their own dime. > Oh yes we do. The VFX code generator was a speculative venture. > Yes, we do it with commercial (and sometimes cautious) interest, > but MPE at least has a long track record in speculative R&D > ventures, including what eventually became the basis of the > Europay OTA system. Actually, I was referring more to my experiences trying to get Forth Inc to produce a port to the ARM. I thought it was pretty clear that the ARM is a CPU with as much future as the x86 architecture and still could not get Forth, Inc to do it without paying them. I'm curious, which CPUs did you feel were not worth the port? I have been looking at the various CPUs for FPGA implementation. I am pretty convinced that a simple Forth CPU can be done very efficiently (others have done it) and would run rather quickly (again, others have done it). One thing that prevents me from using a design like this is that I would be on my own for tools. Although that seems to be OK with a typical Forther, I am a bit shy of the idea. Is it at all practical to consider an HDL Forth alternative to the NIOS and microBlaze? What would you require to do the software side of such a port? I am aware that you market an HDL version of an older Forth processor, but I expect that is not well optimized for FPGA implementation. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67384
Hal Murray wrote: > > >The only reason I could see to do a Forth machine in an FPGA is that you > >might have valuable Forth code that needs to run 100x faster than the > >microprocessor curretly hosting it. So, you do a 6502 (or whatever) on > >steroids or a true Forth machine in a fast FPGA and solve your problem. > > Suppose I had some Forth code that I wanted to run. How would a > special system in an FPGA compare to an emulator/inteperator on > a normal CPU (take your pick)? > > I guess I'm curious about $/instruction or $/MIPS as well > as absolute speed. > > I'd expect a resonably vanilla X86 or embedded system would do > quite well in the $/instruction department. I'd expect a > modern PC to go pretty fast, depends upon the skill of the > guys writing the compiler/interpreter/emulator. > > Can I actually build a system in a FPGA that runs faster? I don't think this is what people are referring to, but yes, I expect you *could* build a system that runs faster if it is targeted to a specific application. That *is* what FPGAs are all about. Sort of like the way a DSP is used to do signal processing even though they process instructions more slowly than a Pentium 4. They are optimized for vector processing and do it using a lot less power and space. I think the idea of any CPU in an FPGA is not to compete with a desktop system, but to provide a very low cost solution for an embedded system that requires an FPGA to implement custom hardware to optmize it for a particular app. > The FPGA system might be a great idea if you already need > the FPGA for something else, especially if your program/system > is small enough so that you won't have to add a lot of memory chips. Yes, that is the point. Forth typically has a very small memory footprint (the stack can be less than 256 cells on many systems) and has a very simple structure. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67385
Brian Philofsky wrote: > > You can dowload a free version of ISE 4.2i that does support the XC4010E > device from the Xilinx Web Site at: > http://www.xilinx.com/webpack/classics/spartan_4k/index.htm > > The main gotcha with this version is that it does not include a syntheis > tool so you must get your design to an XNF or EDIF netlist before using > the tool. There are some free and pay-for synthesis/schematic tools > available if you look around for them but I will leave that exercise up > to you. This should be better than the 2.1i version you have found and > it is how I would suggest you go forward if you want to use the XC4010E > device. The XC3142 (about a 15 year old part) on the other hand is too > old to be even suppoorted by the 4.2i or 2.1i versions and you would > need to go back to the XACT tools (circa 1995) to use it which I do not > suggest doing at this point. > > Hope this helps, Can the webpack tools be used to synthesize the design to an XNF or EDIF file to use in the ISE 4.1 tool? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67386
john jakson wrote: > > A while back I mentioned I'd post an update on progress for this R3 > hyperthreaded cpu project. > ...... > > Licensing > I have been contemplating how to license the design, I would like to > see the final design in its Transputer form open to individuals and > dot edu, but $ for commercial interest. Trolltech does this with Qt, > gpl for non commercial Linux and the KDE world while still doing well > for $ Windows market. > > I am interested in other points of view on this. What exactly is the purpose of this CPU, that is, why would a user want this CPU instead of a commercial CPU? It sounds like it uses a fair amount of FPGA real estate, although the speed is impressive. But it requires a memory interface that can keep it fed which will use a lot of IOs. Also, what do you mean about it's "Transputer form"? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67387
Kevin Neilson wrote: > > Maybe I shouldn't expect too much for $25. > -Kevin Yes, dollars are a strong incentive to optimize away features aren't they? I have an old analog cordless phone/answering machine that allows me to listen in on a message being left via the handset while I am outside or in the basement. But my new, 5.4 GHz machine with all sorts of bells and whistles (and every other digital cordless I looked at) does not have this feature. That is because they use voice compression on a DSP to record the message to RAM. They also use the same DSP to make the digital link to the handset. They did not build in enough DSP horsepower to do both and saved a $ on a $150 phone set. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67388
"Subroto Datta" <sdatta@altera.com> wrote in message news:QmG3c.57551$yJ6.24061@newssvr33.news.prodigy.com... > Hi Antti, > > Just to make sure that everything is on the Altera web site is OK, I did > the following: > > 1. Downloaded the Quartus II 4.0 Web Edition ( used the > quartuii_40_web_edition_single.exe download, all 144.7 MB of it), installed > it on my PC, > 2. Got myself a license from the Altera Licesning Center, > 3. Compiled a one wire design, (input followed by lcell followed by output), > for the APEX20KE, Cyclone, Stratix, and MaxII families, both with Auto > Device Selection and Specifying a fixed Device (from the list shown in the > Assign Device Box). > 4. Compiled the fir_filter Tutorial design > > All without any problems. > > Based on your description of the internal error, I believe your installation > was incomplete, and that some of your device databases may not been > installed. This may happen if you ran out of disk space during the > installation, or your downloaded image was corrupt. It is probably the > former. Give the installation a try again, and send me the results. It was nothing wrong with during the installation, 30GB DISK, 2GB RAM but there was Q v3 what was auto unistalled, before the Q v4 installed and afterwards I started Q v4 without re boot, and got results as I described. after reboot, I also got errors, but then changed device type what was Stratix II (even though I think I was trying to wire only in MAX-2) anyway, it works now. but the first frustration was real. now having again problems with NIOS eval license :( got it working in Q v3 and now it again doesnt work. Quartus Licensing says all OK, SOPC builder does all OK, but quartus compile complains about license missing. oh well need to fight again! AnttiArticle: 67389
Kevin Neilson wrote: > I've been reading about CORDIC engines (in a paper by Andraka) and I was > wondering if they are still relevant in parts with a lot of blockRAM. I've > always used sin, cos, and arctan lookup tables in blockRAM, which yield two > results per blockRAM per cycle in a Xilinx V2 (each 18 bits with 88 > millidegree phase resolution), and I was wondering if there is a compelling > advantage of a CLB-based CORDIC engine in, for example, a V2 part. I know > the CORDIC can multiply as well, but the V2 parts also have embedded > multipliers. Perhaps those big ROMs and multipliers are making me lazy. CORDIC lets you trade cycles for precision, while LUT lets you trade logic (area) for precision. Which you choose depends on what you are doing, and what you are doing it with! In some applications, cycles are a lot "cheaper" than logic. In others, you must spend lots of logic (= $$$), to save a few cycles (or more likely, to make the computation time constant). Regards, JohnArticle: 67390
Hi all, Does anybody know what are basic techniques to achieve a throughput of 4 bits per clock in FPGA for a viterbi decoder. Basically, what I want is the following: (1.) If I clock Viterbi decoder at clock frequency of 50 MHz to implement in FPGA/ASIC, what basic algorithm should I choose to achieve 200 Mbps throughput that means computing 4 decoding bits per clock. And I don't want to use Radix 16 ACS that being very complex. Any thoughts on this will be appreciated. Thanks and Regards NitinArticle: 67391
hi,
thanks for u r help. my main problem is synthesis. It is
simulating and working properly and individual blocks are
synthesizing. i am ready to send the total code. Please give u r mail
i.d.
again i am giving my error nad code of some part.
FATAL_ERROR:HDLParsers:vhptype.c:270:$Id: vhptype.c,v 1.1 2001/03/22
18:59:29 kingsley Exp $:200 - INTERNAL ERROR... while p
arsing G:/sunil/totaldecoder.vhd line 108. Contact your hot line.
Process will terminate. To resolve this error, please con
sult the Answers Database and other online resources at
http://support.xilinx.com
EXEWRAP detected a return code of '1' from program
'F:/Xilinx/bin/nt/xst.exe'
Done: failed with exit code: 0001.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity totaldecoder is
Port ( s1 : in std_logic_vector(2 downto 0);
s2 : in std_logic_vector(2 downto 0);
T3 : in std_logic_vector(3 downto 0);
clk : in std_logic;
clk1 : in std_logic;
reset : in std_logic;
val : out std_logic );
end totaldecoder;
architecture Behavioral of totaldecoder is
component BMUnew
port ( S1 : in std_logic_vector(2 downto 0);
S2 : in std_logic_vector(2 downto 0);
BM0 : out std_logic_vector(3 downto 0);
BM1 : out std_logic_vector(3 downto 0);
BM2 : out std_logic_vector(3 downto 0);
BM3 : out std_logic_vector(3 downto 0));
end component;
component comparatortreenew
port( k1 : in std_logic_vector(5 downto 0);
k2 : in std_logic_vector(5 downto 0);
k3 : in std_logic_vector(5 downto 0);
k4 : in std_logic_vector(5 downto 0);
k5 : in std_logic_vector(5 downto 0);
k6 : in std_logic_vector(5 downto 0);
k7 : in std_logic_vector(5 downto 0);
k8 : in std_logic_vector(5 downto 0);
k9 : in std_logic_vector(5 downto 0);
k10 : in std_logic_vector(5 downto 0);
k11 : in std_logic_vector(5 downto 0);
k12 : in std_logic_vector(5 downto 0);
k13 : in std_logic_vector(5 downto 0);
k14 : in std_logic_vector(5 downto 0);
k15 : in std_logic_vector(5 downto 0);
k16 : in std_logic_vector(5 downto 0);
address : out std_logic_vector(3 downto 0);
min : out std_logic_vector(5 downto 0));
end component;
component TOTALACSUNITS
port( B0 : in std_logic_vector(3 downto 0);
B1 : in std_logic_vector(3 downto 0);
B2 : in std_logic_vector(3 downto 0);
B3 : in std_logic_vector(3 downto 0);
clk : in std_logic;
T : in std_logic_vector(3 downto 0);
reset : in std_logic;
minimum : in std_logic_vector(5 downto 0);
d16 : out std_logic_vector(15 downto 0);
re_traceback,re_counter : out std_logic;
com_smu,com_traceback : in std_logic;
IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8,
IN9,IN10,IN11,IN12,IN13,IN14,IN15 : out std_logic_vector(5 downto
0));
end component;
component tracebackunitnew
port( clk1 : in std_logic;
decisionbits : in std_logic_vector(15 downto 0);
address : in std_logic_vector(3 downto 0);
output : out std_logic;
complete_smu : out std_logic;
complete_traceback : out std_logic;
reset_traceback : in std_logic;
reset_counter : in std_logic);
end component;
signal B0,B1,B2,B3 : std_logic_vector(3 downto 0);
signal addre : std_logic_vector(3 downto 0);
signal d116 : std_logic_vector(15 downto 0);
signal minimm : std_logic_vector(5 downto 0);
signal r_traceback,r_counter,co_smu,co_traceback : std_logic;
signal YN0,YN1,YN2,YN3,YN4,YN5,YN6,YN7,YN8,YN9,YN10,YN11,YN12,YN13,YN14,YN15
: std_logic_vector(5 downto 0);
begin
BMU1 : BMUnew port map ( S1 => s1,
S2 => s2,
BM0 => B0,
BM1 => B1,
BM2 => B2,
BM3 => B3);
TREE : comparatortreenew port map ( k1 => YN0,
k2 => YN1,
k3 => YN2,
k4 => YN3,
k5 => YN4,
k6 => YN5,
k7 => YN6,
k8 => YN7,
k9 => YN8,
k10 => YN9,
k11 => YN10,
k12 => YN11,
k13 => YN12,
k14 => YN13,
k15 => YN14,
k16 => YN15,
address => addre,
min => minimm );
TRACEBACK : tracebackunitnew port map ( clk1 => clk1,
decisionbits => d116,
address => addre,
output => val,
complete_smu => co_smu,
complete_traceback => co_traceback,
reset_traceback => r_traceback,
reset_counter => r_counter);
TACS : totalacsunits port map( B0 => B0,
B1 => B1,
B2 => B2,
B3 => B3,
clk => clk,
T => T3,
reset => reset,
minimum => minimm,
d16 => d116,
re_traceback => r_traceback,
re_counter => r_counter,
com_smu => co_smu,
com_traceback => co_traceback,
IN0 => YN0,
IN1 => YN1,
IN2 => YN2,
IN3 => YN3,
IN4 => YN4,
IN5 => YN5,
IN6 => YN6,
IN7 => YN7,
IN8 => YN8,
IN9 => YN9,
IN10 =>YN10,
IN11 => YN11,
IN12 => YN12,
IN13 => YN13,
IN14 => YN14,
IN15 => YN15);
end Behavioral;
Article: 67392*sigh* - is speed the thing that everyone is concerned with? Hands down, hardware is faster than software - most non-technical folks know this. End of story. Now if you are looking at complex algorithm implementations algorithm COMPLEXITY is of paramount concern. Time complexity is independent of platform: sw/hw. It provides a designer with a means of judging unit-less time efficiency. Here is a classic example: while bubble sorting 10 items is fine, 1 million items? Uhhh... in this case, an efficient SW implementation would be alot faster (even with the OS overhead). Complexity can allow a designer to come up with new algorithms and make statements about room for improvement, algorithm comparisons, or to simply offer others a platform-free metric by wich to judge suitability of an algorithm to a given problem. I am assuming you are more into algorithm design so look it up properly since you are feeling smart. Speed is not everything. Reduced complexity is.... increased speed just follows a good reduced (time) complexity design. Once the algorithm is in place, then once again - hw wins for speed. At this point, the hardware boys can start looking at their bread and butter: space complexity. Sorry for throwing theory in. I figure I should post as many times as possible to technical forums before I quit engineering for med school. *sigh* I will miss it dearly. J. "OP" <omnipresent@hotmail.com> wrote in message news:a0539759.0402251309.55f0ebaa@posting.google.com... > Hi, > > Feeling really intelligent today.. I would like to know some basic > stuff.. > > What is the difference between a hardware implementation of an > algorithm and a software one. > > How do you say an algorithm is faster in one and slower in other.. if > it's based on timing how do you do that?? What makes it faster in one > and not in other?? > > all the help is appreciated. > > OP.Article: 67393
Jim,
your comment seems logical, except for the fact the nowhere in my code "Str2" can be found. I put my whole code in comment and slightly took it out again. This made me wiser, I now know the error is found in the line in comment (almost at the end of the code). I suppuse the error is caused because count is not a static value, but I'm not sure, since ... I'm still a novice.
Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity peak_of_peaks is
generic( data_width : integer := 16;
index_width : integer := 15);
Port ( clk : in std_logic;
reset : in std_logic;
sending_pulse : in std_logic;
peak_index : in std_logic_vector(index_width-1 downto 0);
peak_amplitude : in std_logic_vector(data_width-1 downto 0);
peak : in std_logic;
max_peaks : out std_logic_vector(data_width+index_width-1 downto 0);
ready : out std_logic);
end peak_of_peaks;
architecture Behavioral of peak_of_peaks is
constant length : integer := 4;
type state_type is (IDLE,START,FIND_PLACE,PLACE,STOP);
signal state, next_state : state_type;
type shiftregister is array((length-1) downto 0) of std_logic_vector(index_width+data_width-1 downto 0);
signal reg : shiftregister;
signal filling : std_logic_vector(index_width+data_width-1 downto 0);
signal count : integer range 0 to length :=0;
signal send_count : integer range 0 to length :=0;
begin
process(clk, sending_pulse) is
begin
if(clk'event and clk = '1') then
if(sending_pulse = '1' and send_count < length) then
if (reg(send_count) /= "0000000000000000000000000000000") then
max_peaks <= reg(send_count);
ready <='1';
send_count <= send_count + 1;
else
ready <= '0';
send_count <= length;
end if;
else
ready <= '0';
end if;
end if;
if (sending_pulse = '0') then
send_count <= 0;
end if;
end process;
state_register : process (clk, reset) is
begin
if (reset = '1') then
state <= IDLE;
elsif (clk'event and clk = '1') then
state <= next_state;
end if;
end process state_register;
next_state_function : process (state, clk, sending_pulse, peak, peak_amplitude, count) is
begin
case state is
when IDLE =>
if (sending_pulse = '1') then
next_state <= START;
else
next_state <= IDLE;
end if;
when START =>
if (peak = '1') then
if( peak_amplitude > reg (0)(data_width-1 downto 0)) then
next_state <= FIND_PLACE;
else
next_state <= START;
end if;
else
next_state <= START;
end if;
when FIND_PLACE =>
if ((count /= length-1)) then
if (peak_amplitude > reg(count)(data_width-1 downto 0)) then
next_state <= FIND_PLACE;
else
next_state <= PLACE;
end if;
end if;
when PLACE =>
next_state <= STOP;
when STOP =>
if (sending_pulse = '1') then
next_state <= IDLE;
else
next_state <= START;
end if;
end case;
end process next_state_function;
datapath_function : process (clk) is
begin
if (clk'event and clk = '1') then
case state is
when IDLE =>
for j in 0 to (length - 1) loop
reg(j) <= (others => '0');
end loop;
count <= 0;
when FIND_PLACE =>
if (peak_amplitude > reg(count)(data_width-1 downto 0)and (count /= length-1)) then
count <= count + 1;
filling(index_width+data_width-1 downto 0) <= peak_index & peak_amplitude;
end if;
when PLACE =>
if (count = length-1) then
reg(length-1 downto 0) <= filling & reg(length-1 downto 1);
else
-- reg(length-1 downto 0) <= reg(length-1 downto count) & filling & reg(count-1 downto 1);
end if;
when STOP =>
count <= 0;
when others =>
null;
end case;
end if;
end process datapath_function;
end Behavioral;
Article: 67394what is the oftenly used algorithms for RC4 encryption in an FPGA? is it true that i have to use at least 256X8X2 registers or RAM? best regards, kelvinArticle: 67395
Hi, not with Cyclone, but with Excalibur. Not really the same thing, but similar : device makes a new configuration every n secondes. Asked help from Altera, but we don't still have found why. We still go on searching : bug on device ? On our design ? On suplly (they seem to be stable). We don't know. Let me know if you find for your Cyclone. Damien. rAinStorms a écrit: > Hi, > > I am wondering if anyone out there has experienced random spurious > reconfiguration issues with Cyclone devices? > We have an issue where the FPGA in our design configures correctly but then > a short time later for apparently no reason goes int a reconfig cycle > and stays there (as its not loaded). I suspect that there might be an issue > with our power supply design but still have not isolated the problem ... and > on the off-chance this is a larger issue, it seems like a good idea to see > whether other people have experienced similar problems. > > Thanks, > Chris > >Article: 67396
I'm desiging at a 3 wire pcm audio interface with clock, frame sync and data. Clock, data and frame sync are fed from extern. The external clock rate starts at 64kHz and the maximum is 2.048MHz. This clock generates interanlly a 12.288MHz clock. So far so good. The problem is, that I have to synchronize the incoming singal with the 12.288MHz signal but I don't know the phase between the 12.288MHz Clock and the incoming signals. The problem is, that I'm using an external PLL (CY27EE16) to multiply the 2.048M to 12.288M. This PLL has an divider at the output, and that means, that you never know the phase between the input and output signal. The usage of this PLL is a must due to several reasons, one important is flexibility. Due to this reason, I cannot pick an fixed edge because after a startup this edge could be the edge which causes metastablity. For this I need a circuit, which allows me during the synchronziation between the external signal and my circuit to detect the optimum edge (positive or negative) of the 12.288MHz signal. Any ideas?Article: 67397
I have a development board that gives me the option of using both JTAG and an onboard PROM for programming the FPGA, but like i say, i've yet to have any problems creating a .mcs file??? If you have any luck on the Xilinx support site or otherwise, post the solution if you have time! Good luck Mike emanuel stiebler wrote: > Mike Nicklas wrote: > >> I suggest looking through the iMPACT related answers in the database >> on support.xilinx.com >> >> I get no such error when running the process. >> >> What exactly are you trying to do if you don't mind my asking? > > > I got my board working using jtag, but it is too expensive > to sell a pc with every board. So I tried to use the PROM for > the FPGA configuration, but I need a .mcs file to program it ... > ;-) > > cheers > > >> Mike >> >> emanuel stiebler wrote: >> >>> Just tried, and I get: >>> >>> Launching Application for process "Generate PROM, ACE, or JTAG File". >>> >>> // *** BATCH CMD : setPreference -pref UserLevel:NOVICE >>> // *** BATCH CMD : setMode -bs >>> ERROR:iMPACT:355 - Open file error, bypass >>> // *** BATCH CMD : setMode -bs >>> >>> Cheers >>> >>> Mike Nicklas wrote: >>> >>>> I just tried this, it should launch the iMPACT program which then >>>> gives you the option of selecting your target type device i.e. PROM, >>>> ACE, JTAG etc. >>>> >>>> it's pretty intuitive from then on. >>>> >>>> Mike >>>> >>>> Mike Nicklas wrote: >>>> >>>>> have you tried expanding the "Generate Programming file" option in >>>>> the processes for source pane of ISE. >>>>> >>>>> The option to generate PROM, ACE or JTAG file is there, try running >>>>> that? >>>>> >>>>> Mike >>>>> >>>>> emanuel stiebler wrote: >>>>> >>>>>> Hi all, >>>>>> >>>>>> Where is the strange checkmark hiding in ISE 6.1 >>>>>> to create the .mcs files for programming the proms ? >>>>>> >>>>>> Thanks >>>>>> >>>>> >>>> >>> >> > -- _ Michael Nicklas FPGA Design Engineer michaeln@slayer.com.remove To email, remove 'remove'! Seven Layer Communications Ltd. URL: www.slayer.com SSPC, Station Road, tel: +44 (0) 131 331 6170 South Queensferry, EH30 9TG fax: +44 (0) 131 331 7772 -Article: 67398
Bruno a écrit:
> Jim,
>
> your comment seems logical, except for the fact the nowhere in my code
> "Str2" can be found. I put my whole code in comment and slightly took it
> out again. This made me wiser, I now know the error is found in the line
> in comment (almost at the end of the code). I suppuse the error is
> caused because count is not a static value, but I'm not sure, since ...
> I'm still a novice.
You'll have a problem if count = 0 because then reg(count-1 downto 1)
will be a null range vector.
If count can be 0, make your assignment conditional:
if count /= 0 then
reg(length-1 downto 0) <= reg(length-1 downto count) & filling &
reg(count-1 downto 1);
end if;
or define count as an integer with a range 1 to length.
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
Article: 67399I am assuming that you are feeding this into a FPGA or CPLD given the newsgroup you are addressing. My suggestion is make a digital phase locked loop, or more simply a phase tracker as your clock presumably tracks the data in frequency drift. Your clock is 6X the maximum data rate. Take you data input and feed it into a shift register. You have at least 6 positive and 6 negative clock edges to work with per data bit. The first register in the shift chain should take out most of the potential metastability issues. Then you just look somewhere down the shift register and monitor to find a data edge (transition). From this you can work out where the data is likely to be stable. This would probably be 3 clocks later at the same point (as edge detection) in the shift register. You will need some kind of free running state machine (phase tracker) or DPLL to collect data when there isn't an edge to work from, i.e. consecutive '1's. Hope this helps. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Martin" <visepp@yahoo.de> wrote in message news:2eca51ca.0403110115.5ef88844@posting.google.com... > I'm desiging at a 3 wire pcm audio interface with clock, frame sync > and data. Clock, data and frame sync are fed from extern. The > external clock rate starts at 64kHz and the maximum is 2.048MHz. This > clock generates interanlly a 12.288MHz clock. So far so good. The > problem is, that I have to synchronize the incoming singal with the > 12.288MHz signal but I don't > know the phase between the 12.288MHz Clock and the incoming > signals. > The problem is, that I'm using an external PLL > (CY27EE16) to multiply the 2.048M to 12.288M. This PLL > has an divider at the output, and that means, that you > never know the phase between the input and output > signal. > The usage of this PLL is a must due to several > reasons, one important is flexibility. > Due to this reason, I cannot pick an fixed edge because > after a startup this edge could be the edge which causes metastablity. > For this I need a circuit, which allows me during the synchronziation > between the external signal and my circuit to detect the optimum edge > (positive or > negative) of the 12.288MHz signal. > Any ideas?
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