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Call for Papers
7th Mil/Aerospace Applications of Programmable
Logic Devices International Conference (MAPLD)
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 8-10, 2004
Hosted by the NASA Office of Logic Design
Abstracts due April 26, 2004 to mapld2004@klabs.org
The 7th annual MAPLD International Conference's extensive program
will include presentations, seminars, workshops, and exhibits
on programmable logic devices and technologies, digital engineering,
and related fields for military and aerospace applications.
Devices, technologies, logic design, flight applications, fault
tolerance, usage, reliability, radiation susceptibility, and
encryption applications of programmable devices, processors,
and adaptive computing systems in military and aerospace systems
are among the subjects for the conference.
We are planning an exciting event with presentations by
Government, industry, and academia, including talks by
distinguished Invited Speakers. This conference is open to
US and foreign participation and is not classified. For related
information, please see the NASA Office of Logic Design Web Site
(http://klabs.org).
This year, there will be special emphasis on the following themes:
"War Stories" and Lessons Learned
Programmable Logic and Obsolescence Issues
Implementing high performance, high reliability processor cores.
Logic design evaluation, design guidelines, and recommendations.
Verification methods for radiation hardness and fault tolerance.
Applications such as MIL-STD interfaces, UAV's, and controllers.
Automated Checkers for low reliability design constructs.
PLD tools/methods that we need but vendors don't supply.
CONFERENCE HOME PAGE - http://klabs.org/mapld04 - contains
an abundance of information on both technical and programmatic
aspects of the conference.
WELCOME AND OPENING REMARKS
Rear Adm. Craig E. Steidle, USN (Ret.)
NASA Associate Administrator for Exploration Systems
SEMINARS - Two full-day seminars will be presented:
VHDL Synthesis for High-Reliability Systems
Aerospace Mishaps and Lessons Learned
PANEL SESSION:
"Why Is Space Exploration So Hard? The Roles of Man and Machine"
WORKSHOPS & "BIRDS OF A FEATHER" SPECIAL SESSIONS
Mitigation Methods for Reprogrammable Logic in
The Space Radiation Environment
Reconfigurable Computing - New Extended Format!
PLD Failures, Analyses, and the Impact on Systems - NEW for 2004!!!
Digital Engineering and Computer Design - A Retrospective and
Lessons Learned for Today's Engineers
* Includes a disassembly and discussion of a Block II
Apollo Guidance Computer by the engineers who designed it.
"An Application Engineer's View" - Back for 2004!
"NESC and Software" - a joint session of MAPLD and the NASA
Engineering and Safety Center
TECHNICAL SESSIONS:
Applications: Military and Aerospace
Systems and Design Tools
Radiation and Mitigation Techniques
Processors: General Purpose and Arithmetic
Reconfigurable Computing, Evolvable Hardware, and Security
Poster Session
INDUSTRIAL and GOVERNMENT EXHIBITS AND SPONSORS
(early reservations, more to come):
NASA Office of Logic Design Mentor Graphics Corporation
Xilinx Corporation Synthworks
Tensilica Actel Corporation
Annapolis Microsystems Space Micro, Inc.
SEAKR Engineering Aldec
IEEE Aerospace and Electronics Systems Society
Hier Design Global Velocity
Lattice Semiconductor Quicksilver Technology
Celoxica BAE Systems
Nallatech The Andraka Consulting Group
Aeroflex Synopsys
Peregrine Semiconductor Starbridgesystems
Condor Engineering AccelChip
NASA Engineering and Safety Center Synplicity
Defense Microelectronics Activity Southwest Research Institute
Altera
For more information, please visit http://klabs.org/mapld04
or contact:
Richard Katz - Conference Chair NASA Goddard Space Flight Center
mapld2004@klabs.org Tel: (301) 286-9705
Late abstracts will be accepted for poster and worshop sessions only.
Article: 68876Thanks, I did get the gcc-nios compiler working. I just didn't realize I needed to install Quartus AND the Gnu tools AND the Nios kit to get there. I spent way too much time on the Altera website trying to figure this out. Since Gnu is about sharing source, I see no reason not to publish the download link, particularly since Altera seems to want to hide the fact that it is free. Maciej Witaszek wrote: > On Sun, 18 Apr 2004 00:10:58 +0200, tns1 wrote: > > >>What's the story? Are the SW tools free or not, and where do I get them? > > > Hi, > The path to gnupro tool that's published at > http://www.altera.com/support/kdb/rd11272000_7307.html > are wrong. You may ask a Support to correct one, because > I obtain it from them. If they don't want to tell you, > ask me to send you the address. The gnupro tools are published > under GPL, so it's free. But I don't know if I can publish > a path to it. (??) > > It's a source code of tool chains only:gcc, gdb, ld, ... > It doesn't have nios-build and nios-run tools, > a SOPC Builder and NIOS components like CPU core. > You should obtain them with your dev board. > > The source code is at some pleaces broken. There are new line > where it shouldn't be. In some files there are new lines > in DOS format rather than in Unix. So it needs some expererience > in Unix/Linux programming. I compiled it with gcc-3.3.3 from > Gentoo Linux. I was trying older gcc-2.54, but without success. > I thin that it's possible to compile gnupro under Windows using > Cygwin libraries. > > Best Regards, > Maciej Witaszek >Article: 68877
Peter Alfke <peter@xilinx.com> wrote in
news:BCAB2347.5F88%peter@xilinx.com:
> Many years ago, i tried to come up with the largest number of 2-input
> NAND gates that could be hidden in a 4-LUT.
> I thing the number was around 20. It involved many XORs which count as
> four NANDs.
> There must be a scientific answer to this:
> What's the function of four variables that irreducibly requires the
> largest number of 2NAND functions to implement ?
A 4-input truth-table can be represented by a 16-node hypercube. You can
select 8 nodes of the 16 such that none of these selected nodes are
adjacent. Each of these nodes represents a 4-input minterm and since
they are non-adjacent there is no possibility of combining minterms. A
4-input minterm requires 3 AND gates and some inverters. Then the 8
minterms have to be OR'ed together which requires another 7 OR gates. So
that totals to 8 * 3 + 7 = 31 2-input gates. I don't have any proof that
this is a maximum, but it seems adding more minterms would allow some
combining of minterms and that would reduce the number of gates needed,
as would removing any minterms.
Here's a function derived using this idea:
F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D +
A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D
If you allow some of the outputs of the 2-input AND gates to be shared
across minterms, then you can cut 8 AND gates and get down to 23 2-input
gates.
>
> Peter Alfke
>
>> From: hmurray@suespammers.org (Hal Murray)
>> Newsgroups: comp.arch.fpga
>> Date: Wed, 21 Apr 2004 00:08:31 -0000
>> Subject: Re: calculate the number of logic gate in FPGA
>>
>>> After synthesis(Synplify Pro), I got how many LUTs I consumed,
>>> How to equally convert it to the number of logic gates? The device
>>> is the Xilinx VirtexE.
>>
>> Quick answer: There isn't any easy way. It depends upon how much
>> logic your design put in each LUT.
>>
>> Crazy question... What's the most number of gates that anybody
>> has ever put into a LUT? Might be a fun hack to try all possible
>> functions, translate to gates, maybe run some minimization stuff,
>> and remember the worst case.
>>
>> --
>> The suespammers.org mail server is located in California. So are all
>> my other mailboxes. Please do not send unsolicited bulk e-mail or
>> unsolicited commercial e-mail to my suespammers.org address or any of
>> my other addresses. These are my opinions, not necessarily my
>> employer's. I hate spam.
>>
>
>
--
|| Dr. Dave Van den Bout XESS Corp. (919) 363-4695 ||
|| devb@xess.com PO Box 33091 ||
|| http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||
Article: 68878>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + > A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D > >If you allow some of the outputs of the 2-input AND gates to be shared >across minterms, then you can cut 8 AND gates and get down to 23 2-input >gates. That looks like odd parity, aka an XOR tree. If Peter's claim of a (2 input?) XOR counting as 4 NANDs, then we can built it in 2 layers using 12 gates rather than 23. Did I miss something? I'm assuming NOR and NAND count the same. Is that generally true? How do ASIC people count inverters? A whole gate or a partial gate? How about AND vs NAND? Do I get a free inverter sometimes? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68879
> I avoid directly instantiating vendor library models as much as > possible, as it makes porting between vendors (and even device > families within a single vendor's portfolio) difficult. If there's > something that I must instantiate, I put it in a module instantiated > by the higher-level code. A generate can be used to select the module > with the library element or a different module with a behavioral > model, or a module with a library element for a different > device/family. Yes, I've done also the same! > > Really, trying to pigeonhole all of your designs into one style of > coding is a bad idea. > Well, that's supporting my own conciderations. Thank you all! Best regards, Thomas.Article: 68880
Paris,
None of your solutions are that far away fronm working.
> i know i could use a function, but that only works when i've a small amount
> of data to read, cause otherwise, storing a HUGE array slows down the
> simulation, without saying that modelsim tells me that i has not enough
> memory and will start paging to disk and after a while it says that i got
> completely out of memory.
You could use a procedure and never exit.
Pass out one set of data values on every clock.
> now i need to open an arbitrary file, so i tried "file_open(fp,
> filenameString, READ_MODE);" the problem is that somehow it doesnt work, as
> it seems that if i open the file in one process (i have to open the file
> just once and read it till the end of the file at every rising_edge(clk), so
> that's two processes). It doesnt work cause it seems that the file is
> "closed" outside the process it was opened (i think i even read about that
> issue).
I am guessing that your file handle declaration is in the process and
not the architecture. If the file handle declaration were in the
architecture, I suspect that this would work. With your file handle
declaration in a process, only the process that declares the file handle
can see it.
> Also i cant find "file_open" declaration.
It is built into the language.
> i also tried with a process like this: (im at home now, so i dont have the
> real sources, but i cant sleep so im writing to ask for help :) please)
>
> process
> begin
>
> if (filenameString /= nothing) then
> file_open(fp, filenameString, READ_MODE);
>
> while (not endfile(fp)) loop
> wait until rising_edge(clk);
> read(fp, data);
> etc, etc
> end loop;
> file_close(fp);
else
wait ;
> end if;
> end process;
This can work too, however, when filenameString = nothing,
then the process goes into an infinite loop.
If filenameString = nothing means do nothing forever,
add an else branch with a wait statement in it as shown
above.
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 68881Hi, Sorry. Was my fault when typewriting; I also use "elsif" clause in the second process instead of "if" clause. > Logic looks OK except I would have used elsif clause. I suspect > that your "input" signal, although synchronous, is external to > the block you're simulating. Yes, the input signal is external to my block, it's a clock divider output and 3 clock period wide. > If so, assert it _in_the_simulation_ > on a falling clock edge. Think of it this way. Label the rising > edges T=0,1,2,3. Then if input goes high on clk T=2, it really > goes high "a little while after" T=2 but well before T=3 (we hope! > but timing is outside the scope of functional simulation). So > by asserting it at T=2.5 (ie falling edge) you're telling the > simulator that "input" was low at T=2 but high at T=3... which is > (hopefully) what you want. I found it confusing at first but > got used to it after a while. It could be a solution; I'll try it. But I cannot see why doesn't my design work. I have created another design where the input signal is an input port instead of an output of an internal register. I have simulated it functionally changing the input value from 0 to 1 together with a rising edge of the clock. As in the other case a glitch is appeared in the functional simulation but now the design works and the FF is reseted. I cannot see why ModelSim works fine with an input port and not with the output of an internal FF. Thanks in advance, Arkaitz. --------------------------- Electronics Area IKERLAN Pš J. M. Arizmendiarrieta, 2 20500 Arrasate (Gipuzkoa) ---------------------------Article: 68882
it should perhaps be pointed out that UART's aren't in fact clockless.. they are self clocking... that is the clock is passed with the data (i.e. the leading edge of the start bit is the re-syncing edge) Simon "Peter Alfke" <peter@xilinx.com> wrote in message news:BCAB2209.5F87%peter@xilinx.com... > Simple answer: You cannot. You can of course generate your own clock... > Peter Alfke > > > From: shashi22k@rediffmail.com (Shashi) > > Organization: http://groups.google.com > > Newsgroups: comp.arch.fpga > > Date: 20 Apr 2004 16:35:16 -0700 > > Subject: Issues on Shift Register in a Clockless UART > > > > Hi, > > I'm doing a project in clockless uart..as u know that the primary > > function of uart is parallel to serial conversion while transmitting > > and serial to paralel conversion while receiving..I was wondering if > > someone could tell me as how can i do a parallel to serial conversion > > and vice versa without using a clock. > > > > Thank You > > SHASHI >Article: 68883
> After synthesis(Synplify Pro), I got how many LUTs I consumed, > How to equally convert it to the number of logic gates? The device is > the Xilinx VirtexE. I've got a similar problem: I want to know how much Resources in my FPGA are used ... so I'm not interested in the Gate-Count but in the number of Flipflops, Luts, BRams ... The Map-Report shows: BRams 25 of 40 DFF 5200 of 10240 FGs 4200 of 10240 But I expected 28 Blockrams to be used so I opend the (routed) design in the Floorplanner and there the usage was higher ... Floorplanner says something like: BRams 28 of 40 DFF 5800 of 10240 FGs 4500 of 10240 As I know the Number of used Blockrams I tend to say the Florplanner is probably right - but whats wrong with my map report?? I'm using Xilinx XST 5.2 for a Virtex-2-1000 ff896, but there is the same problem in a project for a Spartan2-200 bye, MichaelArticle: 68884
Simon Peacock wrote: > it should perhaps be pointed out that UART's aren't in fact clockless.. they > are self clocking... that is the clock is passed with the data (i.e. the > leading edge of the start bit is the re-syncing edge) The LIN Bus takes this a step further, in that a BAUD rate is not assumed, but they send a known preamble byte (55H or AAH IFW), and that allows 'floor sweepings grade' uC / RC osc to autobaud. No reason the same ideas could not be used on a FPGA. You would start a low precision burst oscillator on the leading edge, calculate your AutoBAUD divisor on the first byte, and run until a known stop char/count, then go back to clockless-sleep. Rather high baud rates would seem to be possible... -jgArticle: 68885
HI,
I want to generate VCD file for my VHDL file. I am using modelsim
5.6f. If anybody knows the commands which we have to run to get VCD
file please mail those.
thanking you all.
Article: 68886Andrew, OK, off-topic, but a valuable question nonetheless... My experiences are in the US: "Andrew Leo" <asdf@aef.com> wrote in message news:<c635ne$sjp$1@reader01.singnet.com.sg>... > Hi, there: > > I went for an interview with a R&D center of an american company. > One week after the interview the interviewer sent me a letter asking me > to sign a paper for background check..What does that mean? AFAIK 1. As others have noted, permissions requested for background checking have increased in the last several years (IIRC well before 9/11). They can ask permission to check things like medical and credit history besides educational and professional references. > this is not customery in my country...Under what circumstance do they > ask for background check? 2. My opinion is that most bigger companies ask for the background check because the lawyers have said that the HR (Human Resources, aka Personnel) department should do so. I would guess they do it as a matter of routine for all applicants. > How do I know whether they abuse my > rights? You don't. > What kind of information may they check and what not? They may check any information you give them permission to check. Note that there probably will be some information they can check even without your permission. > Is it compulsory for an american co to perform this check? No it is not. > Best Regards, > Leo My practice has been to read carefully what they are asking me permission for and cross out anything I don't wish to give sign. I usually explain to whoever has given me the form (since this is bigger companies it is usually HR department) that I don't believe some of the requests are reasonable, but to please let me know if this prevents them from offering me a job, so we can try to work it out. As best I recall, I have gotten offers from every company where this situation has occurred, definitely 3 and perhaps as high as 4 or 5. Of course this is easier to do if you have other options and can afford to walk away from the job. I suspect that many companies only require that the form be signed, the background check may or may not occur. They cannot appear to discriminate in who they ask to check backgrounds of, but they don't need to actually check everyone who gives permission. Be watchful for the following: are you being asked to sign some permission that lasts forever, including during the tenure of your employment ? Does the permission last forever even if they don't hire you or you turn down the offer ? The lawyers who dream up these agreements only care about the company's interests, and have also been known to be sloppy. What happens to the information they collect ? Will they destroy it, turn it over to you, or are you giving them permission to do whatever they want (ie publish or resell) with your information. Not that they will, but why should they have permission to ? It is a sad day when we need to have the services of a lawyer merely to apply for a job. Good luck and let us know how it turns out, -rajeev-Article: 68887
Jon, jon.parker@flextronics.com (Jon Parker) wrote in message news:<a76c9332.0404200716.4f8622f6@posting.google.com>... > I have a DSP development kit, Stratix Edition. I obtained a license > for the development kit, using the link: > > https://mysupport.altera.com/lic/devKitNic.asp?product=stratix > > I received the license, installed it per the instructions. Quartus II > seems to work OK but when I try to run the Filtering Reference Design > Lab, exercise 3, and run the Signal Compiler 2.1.3, I get the error > message "! Unable to check a valid DSP Builder License". I was under > the impression from the Altera Licensing web link that the DSB Builder > License was included as a feature of the licensing file. I've > contacted Altera but so far no response. Does anyone have any > experience with this problem? Thanks a million. > > Jon Been there done that. More experience that I could wish for. Go to the user guide, UG_DSPBuilder.pdf, and read the section titled "Error Message: Signal Compiler is Unable to Check a Valid License." In fact keep the whole troubleshooting section handy, because once you get past the license hurdle, you're likely to need other portions of it. Now, why would Altera document all these problems instead of fixing them ? And yes there are problems that aren't neatly documented. Bless your stars if you don't run into them. Regards, -rajeev-Article: 68888
Can someone tell me about the steps to partially reconfigure Vertex-II FPGA's with some simple example? Shahzad SaleemArticle: 68889
ssaleem wrote: > Can someone tell me about the steps to partially reconfigure Vertex-II > FPGA's with some simple example? I recommend Application Note 290: http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf There are no really simple examples for partial reconfiguration, since it just is not that simple... cu, SeanArticle: 68890
On 21 Apr 2004 04:04:14 -0700, inaganti_suni@yahoo.com (sunil) wrote:
>HI,
> I want to generate VCD file for my VHDL file. I am using modelsim
>5.6f. If anybody knows the commands which we have to run to get VCD
>file please mail those.
> thanking you all.
If you have a license that allows Verilog + VHDL co-simulation, you
can add this to a Verilog module somewhere:
initial
begin
$dumpfile("myfile.vcd");
$dumpvars(1, mytopinstancename );
$dumpon;
end
Regards,
Allan.
Article: 68891hmurray@suespammers.org (Hal Murray) wrote in news:108c3g94o54ek1a@corp.supernews.com: >>F(A,B,C,D) = /A*B*C*D + A*/B*C*D + A*B*/C*D + /A*/B*/C*D + >> A*B*C*/D + /A*/B*C*/D + /A*B*/C*/D + A*/B*/C*/D >> >>If you allow some of the outputs of the 2-input AND gates to be shared >>across minterms, then you can cut 8 AND gates and get down to 23 2-input >>gates. > > That looks like odd parity, aka an XOR tree. If Peter's claim > of a (2 input?) XOR counting as 4 NANDs, then we can built it in > 2 layers using 12 gates rather than 23. Did I miss something? I agree with you on that. There must be more resource sharing that allows you to reduce the 23 gates down to 12. > > > > I'm assuming NOR and NAND count the same. Is that generally true? > How do ASIC people count inverters? A whole gate or a partial gate? > How about AND vs NAND? Do I get a free inverter sometimes? > -- || Dr. Dave Van den Bout XESS Corp. (919) 363-4695 || || devb@xess.com PO Box 33091 || || http://www.xess.com Raleigh NC 27636 USA FAX:(919) 367-2946 ||Article: 68892
Hi, I do not know if this matters: it is a Spartan IIe 50k device, interfaces are - or JTAG or parallel. One project, a small test vhdl code, can be loaded and works correct. Both ways JTAG and parallel are possible. Another larger project cannot be loaded. The Impact-Loader says after 'loading' that the 'done-pin does not go high'. Indeed the done-pin remains low, also when loading via parallel interface via microprocessor. The BIT-file which is used in any of the cases, was compiled with ISE 4.2i as well as with the newest WebPack 6.2.02i Any hint how a compiled file can be wrong so the BIT-file cannot be loaded? Klaus HiltropArticle: 68893
--------------------------------------------------------------
2004 IEEE 16th International Conference on Microelectronics (ICM'04)
December 6-8, 2004.
Tunis, (Tunisia)
--------------------------------------------------------------
The ICM 2004 Organisation Commitee is pleased to announce the
Call for Papers :
http://www.gmslab.org/conferences/icm2004/call_for_papers.htm
http://www.gmslab.org/conferences/icm2004/icm_files/cfpICM2004net.pdf
======================================
extended summaries by August 10, 2004
======================================
Information about the conference available at :
http://www.gmslab.org/conferences/icm2004
==============
GENERAL SCOPE:
==============
Microelectronics technology:
============================
· Device characterisation and modelling
· Device physics and novel structures
· Materials and material characterisation techniques
· Process technology, CMOS, BJT, BiCMOS, GaAs.
· Reliability and failure analysis
· Radiation effects
· Packaging, surface mount technology
· Opto-electronics
· MEMS and MOEMS Devices
· Smart power and sensors
Design and application of integrated circuits and systems:
-----------------------------------------------------------
· Custom and semi-custom circuits (design concepts, architectures,
high-performance and low-power circuits).
· Embedded system design
· Systems on Chip (SoCs)
· Digital signal and data processing
· Analog circuit techniques
· Design for testability
· Low-voltage, low-power VLSI design
· Applications to computer and telecommunications systems
· ANN applications
· Wireless Communication Applications
Computer-aided design for microelectronics:
============================================
· Simulation (process, device, circuit, logic, timing, functional).
· Layout (placement, routing, floorplanning, symbolic, ERC, DRC)
· Test (generation, testability, build-in test, simulation).
· Systems (design synthesis, compilation, expert systems, too
integration, hardware acceleration, CAD systems).
· Formal verification.
======================
SUBMISSION OF PAPERS:
======================
Author(s) should submit extended summaries by August 10, 2004. The
summary must clearly indicate the area of the papers, the main results
and contributions. The summary should not exceed four pages, and should
strictly follow the IEEE journal two-column format. Summaries should be
submitted as PDF files attached to an Email. Notification of acceptance
will be mailed by September 16th, 2004. The four pages summary of
accepted papers will be published in the Conference proceedings, subject
to the payment of the conference registration fees. The conference
Language is English. Extended summaries must be forwarded to the
conference secretariat :
conference@gmslab.org
============= http://www.gmslab.org/conferences/icm2004
Article: 68894Hi everybody, I'm currently working on a demonstration project of a lightweight vehicle. We would like to include a large FPGA to do some control and signal processing. This would ideally be a totally contained development board, that could be wired into some kind of bus. (Avoiding using a heavy backplane) Or a dual processing system with a conventional processor and FPGA on the same embedded card. Unfortunately we're trouble identifiying a suitable device. There appears to be many PCI/VME ready devices, but few that can be used standalone (Attached to just communications and power!) Does anybody know if there are suitable devices commercialy available? Could you point me in the right direction please? Also is there any information available on similar projects. (Where an FPGA has been used as the controler for a vehicle)Article: 68895
Jim Granville wrote: > > Simon Peacock wrote: > > it should perhaps be pointed out that UART's aren't in fact clockless.. they > > are self clocking... that is the clock is passed with the data (i.e. the > > leading edge of the start bit is the re-syncing edge) > > The LIN Bus takes this a step further, in that a BAUD rate is not > assumed, but they send a known preamble byte (55H or AAH IFW), and > that allows 'floor sweepings grade' uC / RC osc to autobaud. > > No reason the same ideas could not be used on a FPGA. > > You would start a low precision burst oscillator on the leading edge, > calculate your AutoBAUD divisor on the first byte, and run > until a known stop char/count, then go back to clockless-sleep. > > Rather high baud rates would seem to be possible... But this is not "clockless". If the OP really means a UART using *no* clock, I don't see how this can be done. Sequential logic can be made that does not require a clock, but a UART must have a clock to measure time. The UART data format provides information on the timing of the start of a word, but you still need a clock to measure the bit times. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68896
hello all; i am new to this fpga field. i am working on a project to made eight bit alu by using single bit alu as the main component. i want to know that how i can add single bit alu in the library and use it to make eight bit alu. please help me. thanking all. rajivArticle: 68897
> I want to generate VCD file for my VHDL file. I am using modelsim > 5.6f. If anybody knows the commands which we have to run to get VCD > file please mail those. > thanking you all. After "vsim" command use following commands to create a VCD file vcd file file_name.vcd vcd add -r * run -all "vcd file" command creates a vcd file and "vcd add -r *" logs all signals in the design. Refer Modelsim manual for further description and examples. -VikramArticle: 68898
sunil wrote: > HI, > I want to generate VCD file for my VHDL file. I am using modelsim > 5.6f. If anybody knows the commands which we have to run to get VCD > file please mail those. > thanking you all. I don't know for Modelsim 5.6, but in 5.7: open Modelsim, do "Help" -> "SE PDF Documentation" -> "Command Reference", and look in the index under "VCD Files". There are multiple commands that can be used from a TCL script or the Modelsim command line to create VCD files and add signals to them. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68899
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4086954D.FDCD1100@yahoo.com... > But this is not "clockless". If the OP really means a UART using *no* > clock, I don't see how this can be done. Sequential logic can be made > that does not require a clock, but a UART must have a clock to measure > time. The UART data format provides information on the timing of the > start of a word, but you still need a clock to measure the bit times. > > -- > > Rick "rickman" Collins You could have a huge delay line with taps spaced at the center of each bit period. Latch the taps' output with the stop bit. I'll get me coat.... Cheers, Syms.
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