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Messages from 69225

Article: 69225
Subject: Re: Comment on my code style
From: Chris Carlen <crobc@BOGUS_FIELD.earthlink.net>
Date: Fri, 30 Apr 2004 11:10:38 -0700
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:
>>Are you thinking it is possible for some of the 
>>flops in the counter to interpret a clock edge close to the release of 
>>reset as happening before the reset removal, but some of the other flops 
>>interpreting it as not happening before the reset removal? 
> 
> 
> Exactly so.  In general, it is unsafe for an asynchronous signal
> to influence more than one FF.  The jargon is "input hazard".

I see.  I will have to keep this in mind for future stuff.

>>One can 
>>envision this happening due to propagation delays over physical wires. 
>>But perhaps in the case of starting from zero, this isn't an issue.
> 
> 
> This is indeed the case.  If the counter is held at zero, then
> only the very first flip-flop can be affected by the first clock
> after reset is removed;  so the timing of reset w.r.t. clock
> doesn't matter (except that you might get metastability on the
> LSB counter bit, but that's another story).  However, if you are
> trying to clock the counter very fast, it's just conceivable that
> the skew on Reset between bit 0 and bit 1 of the counter is
> greater than one clock period;  in this case, it's just possible
> that the counter could successfully increment from 0 to 1, but
> the next bit is still held in reset by the time the NEXT clock
> arrives - so the counter goes back to zero again.  However,
> this is very unlikely because the synth tools will surely lay
> out the counter so that its FFs are rather close together (so
> that it can use the ripple carry chain) and therefore the reset
> distribution skew is likely to be quite small.  So don't worry,
> it's just me being paranoid as usual.

Things should be Ok at my 10kHz clock rate ;-D

> Sure.  A fully synch design has -0/+1 "jitter" both at the start and 
> at the end, I think.  No escape.  (It's not "jitter" in the usual
> sense, rather "quantization error", but I guess that depends on what
> you're trying to do with the resulting signal).
> 
> OTOH you should trawl through the last few months' comp.arch.fpga
> archives and take a look at what Peter Alfke and others have had
> to say about using polyphase clocks for very high resolution 
> time measurements.  The Xilinx DLLs make all sorts of interesting
> things possible.  I haven't followed that discussion in detail,
> but it sounds like a lot of fun.


I noticed that discussion, and my reaction was "what in the heck are 
they talking about?"  I think after getting some experience with logic 
at the CPLD level I will head towards FPGAs.  I'd like to first complete 
a formal text or course on the matter.

Thanks for the input.


Good day!


-- 
_____________________
Christopher R. Carlen
crobc@earthlink.net
Suse 8.1 Linux 2.4.19


Article: 69226
Subject: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
From: "nappy" <no_spam_@sorry.com>
Date: Fri, 30 Apr 2004 19:06:20 GMT
Links: << >>  << T >>  << A >>
Look at the STMicro parts.. the 242 part has a 4 clock 8051. The up coming
243 part has a 1 clock 51.


"RM" <mainr@_spamjam_bigfoot.com> wrote in message
news:P8-dnWASwLiTjBHdRVn-vA@edaptivity.com...
> I'm looking a microcontroller with the following properties:
> - Includes a USB port interface, which is used for programming all
functions
> (ideal case). Alternatively, initial function programming could be via
JTAG,
> but once programmed the device must support USB.
> - Program should be flash-based. EZUSB requires initial program load via
USB
> whenever the device is re-attached to the USB host. I wish to program
device
> functionality once, and this program should be retained when the device is
> detached from USB.
> - CPLD (or FPGA with non-volatile program storage / autoload (autoload
could
> be performed by microcontroller)) to support reconfigurable hardware
> functions.
>
> Anyone know of such a device?
>
> Thanks,
> R. Main.
>
>
>



Article: 69227
Subject: Correction
From: "nappy" <no_spam_@sorry.com>
Date: Fri, 30 Apr 2004 19:26:43 GMT
Links: << >>  << T >>  << A >>
The SMSC part is the 243. I have been looking at so many parts lately I am
going blind.

go to www.smsc.com


"nappy" <no_spam_@sorry.com> wrote in message
news:Msxkc.58161$V%3.18296@newssvr25.news.prodigy.com...
> Look at the STMicro parts.. the 242 part has a 4 clock 8051. The up coming
> 243 part has a 1 clock 51.
>
>
> "RM" <mainr@_spamjam_bigfoot.com> wrote in message
> news:P8-dnWASwLiTjBHdRVn-vA@edaptivity.com...
> > I'm looking a microcontroller with the following properties:
> > - Includes a USB port interface, which is used for programming all
> functions
> > (ideal case). Alternatively, initial function programming could be via
> JTAG,
> > but once programmed the device must support USB.
> > - Program should be flash-based. EZUSB requires initial program load via
> USB
> > whenever the device is re-attached to the USB host. I wish to program
> device
> > functionality once, and this program should be retained when the device
is
> > detached from USB.
> > - CPLD (or FPGA with non-volatile program storage / autoload (autoload
> could
> > be performed by microcontroller)) to support reconfigurable hardware
> > functions.
> >
> > Anyone know of such a device?
> >
> > Thanks,
> > R. Main.
> >
> >
> >
>
>



Article: 69228
Subject: Re: Correction
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 01 May 2004 09:45:05 +1200
Links: << >>  << T >>  << A >>
nappy wrote:
> The SMSC part is the 243. I have been looking at so many parts lately I am
> going blind.
> 
> go to www.smsc.com
> 
> 
> "nappy" <no_spam_@sorry.com> wrote in message
> news:Msxkc.58161$V%3.18296@newssvr25.news.prodigy.com...
> 
>>Look at the STMicro parts.. the 242 part has a 4 clock 8051. The up coming
>>243 part has a 1 clock 51.

Is the smsc '243 going to be FLASH based ?
-jg


Article: 69229
Subject: Re: SpyGlass Software
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 30 Apr 2004 15:16:31 -0700
Links: << >>  << T >>  << A >>
ijazag@yahoo.com (Ijaz Ahmad) writes:
>  Can anyone send me Evaluation version of SpyGlass Software.

Presumably the publisher can.

Article: 69230
Subject: No net attached
From: sumeet1981@yahoo.com (Sumeet)
Date: 30 Apr 2004 21:07:19 -0700
Links: << >>  << T >>  << A >>
Dear sir,

I have been troubled by this bug for past couple of hours. When i
sythesize my verilog code it says: warning no Port FPGA51 has no net
attached to it - no pad cells inserted at this port.

Port FPGA51 is where my serial data output from ADC is connected.

In my main module i have declared FPGA51 as an input. in the same
module i also write:
 
//DOUT isn't a direct input
//FPGA51 is DOUT, wire DOUT to this pin
input FPGA51;
wire DOUT;
assign DOUT = FPGA51;

DOUT is passed as an input into module instantiation, and in that
module it is utilized after being synchronized with BCK.

Adc_Data_Manager data1(Reset, data_read_flag, DOUT, FSYNC, LRCK, BCK,
VOC_DATA_MOD, AMB_DATA_MOD, data_ready_mod);

Adc_Data_Manager module declaration is as follow:
module Adc_Data_Manager(Reset1, data_rd_flag, DOUT1, FSYNC1, LRCK1,
BCK1, //input signals
VOC_Result, AMB_Result, data_ready);	//output signals

input DOUT1;
input FSYNC1;
input LRCK1;
input BCK1;
input data_rd_flag;

input Reset1;

output data_ready;
output [8:0] VOC_Result;
output [8:0] AMB_Result;

wire [8:0]VOC_SQD;
wire [8:0]AMB_SQD;

wire sync_DOUT;
wire sync_FSYNC;
wire sync_LRCK;

//Synchronizing FSYNC, LRCK, DOUT with respect to BCK
synch s1(BCK1, Reset1, DOUT1, sync_DOUT);
synch s2(BCK1, Reset1, FSYNC1, sync_FSYNC);
synch s3(BCK1, Reset1, LRCK1, sync_LRCK);

and the later in the code i am utilizing sync_DOUT when i start
shifting data into my voice register with statements like these.
VOC_DATA <= VOC_DATA << 1;
VOC_DATA[0] <= sync_DOUT;

Please let me know what i can do to rectify this.

Sumeet.

Article: 69231
Subject: Re: Slack gets worst as I relax timing
From: vbetz@altera.com (Vaughn Betz)
Date: 30 Apr 2004 21:27:13 -0700
Links: << >>  << T >>  << A >>
> I am using QuartusII 3.0. I setup a tsu requirement on some input pins
> and quartus did a P&R and said it could not meet the tsu by 0.5ns on
> only one of the paths. So I relaxed my tsu by about 1ns on all pins
> and did an incremental fitting. Now Quartus came back and said it
> could not meet timing on about 15 paths by 1.5ns. Why is this? Is
> there anyway of adding more predictibility in the P&R of Quartus?
> Thanks & regards 
> tushit

Hi Tushit,

If you simply want to change your timing requirements and re-do timing
analysis, you don't have to re-run the fitter.  Just run the timing
analyzer (quartus_tan).

Most people use incremental fitting when they have a small change to
the circuit, rather than a timing requirement change.  In that case,
incremental fitting usually results in a small timing change (there is
generally some small change in timing with incremental fitting, since
the routing changes --incremental fitting only tries to re-use the
placement).

Did you notice if the logic cell count was different in the two
compiles?  There are some algorithms before fitting that would be
affected by this timing requirement change, and this could change the
netlist enough that incremental fitting wouldn't be able to maintain a
placement similar to what you had in the first fit.

For "hard" control over fitting results, you can back-annotate your
placement.  This will lock every LE etc. in your design down, which is
OK if you don't plan on changing your design source anymore, but
definitely isn't a good idea if you're still going to be changing
source and resynthesizing.  If you back-annotate both placement and
routing, you lock everything down, for even more control.

I'd be interested in getting this circuit as a test case so we can see
why incremental fitting produced a noticable timing change.  We'd only
use it to debug this issue and as a CAD tool test case.  If you're
interested, send me the Quartus archive at vbetz@altera.com.

Vaughn
Altera

Article: 69232
Subject: Re: No net attached
From: =?iso-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@ratnet.stw.uni-erlangen.de>
Date: Sat, 1 May 2004 10:26:19 +0200
Links: << >>  << T >>  << A >>
> DOUT is passed as an input into module instantiation, and in that
> module it is utilized after being synchronized with BCK.
[...]
> and the later in the code i am utilizing sync_DOUT when i start
> shifting data into my voice register with statements like these.
> VOC_DATA <= VOC_DATA << 1;
> VOC_DATA[0] <= sync_DOUT;

are you sure that the last signal (in this case VOC_DATA) in the 
chain is used? If not -  everything will be optimized away and 
there is no use for the input FPGA51 ...


bye,
Michael


Article: 69233
Subject: Re: Altera ByteBlaster II schematic
From: Rene Tschaggelar <none@none.net>
Date: Sat, 01 May 2004 11:24:04 +0200
Links: << >>  << T >>  << A >>
Leon Heller wrote:

>  I just came across this schematic for the ByteBlaster II:
> 
> http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA
> 
> Someone has probably worked out the circuit by tracing the connections on a
> unit as Altera hasn't published it, AFAIK.

Did anyone succeed in getting it to run ?
It appears to be too simple.  Even simpler than the MV.
Not partwise, but from the functionality.

I didn't even try as I get one from Altera.
But, just in case one of my customers
is going to need one ...

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 69234
Subject: Nexar for FPGA Design?
From: William <postmaster@127.0.0.1>
Date: Sat, 01 May 2004 19:16:19 +0930
Links: << >>  << T >>  << A >>

Has anyone tried Nexar? (http://www.altium.com/nexar/)
Is it any good?


Article: 69235
Subject: Connecting a crystal to a Cyclone or Max PLD
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Sat, 1 May 2004 14:47:51 +0200
Links: << >>  << T >>  << A >>
Is it possible to connect a crystal to an Altera Cyclone or a Max pld rather
an an external oscillator?  And if so, is it possible to use a low frequency
crystal as a reference for the Cyclone PLLs, or do they require a high
minimum frequency?

--
David

"I love deadlines.  I love the whooshing noise they make as they go past."
Douglas Adams



Article: 69236
Subject: Re: Connecting a crystal to a Cyclone or Max PLD
From: Marc Guardiani <marc@guardiani.com>
Date: Sat, 01 May 2004 23:56:26 GMT
Links: << >>  << T >>  << A >>


David Brown wrote:
> Is it possible to connect a crystal to an Altera Cyclone or a Max pld rather
> an an external oscillator?  

Not really. You *might* be able to use a couple of pins and create an 
inverter between them and turn this into an oscillator. Of course, this 
sort of oscillator depends on using the "linear" region of an inverter 
which a CPLD or FPGA may not possess (ie, I wouldn't count on this working).

> And if so, is it possible to use a low frequency
> crystal as a reference for the Cyclone PLLs, or do they require a high
> minimum frequency?

The Cyclone only needs a high frequency if you use the PLL. Otherwise, 
you can use any arbitrarily low frequency as a clock for the Cyclone 
and/or MAX PLDs.

> 
> --
> David
> 
> "I love deadlines.  I love the whooshing noise they make as they go past."
> Douglas Adams
> 
> 

Article: 69237
Subject: Re: Connecting a crystal to a Cyclone or Max PLD
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sun, 02 May 2004 02:08:27 GMT
Links: << >>  << T >>  << A >>
Marc Guardiani wrote:

> David Brown wrote:

>> Is it possible to connect a crystal to an Altera Cyclone or a 
 >> Max pld  rather an an external oscillator?

> Not really. You *might* be able to use a couple of pins and create an 
> inverter between them and turn this into an oscillator. Of course, this 
> sort of oscillator depends on using the "linear" region of an inverter 
> which a CPLD or FPGA may not possess (ie, I wouldn't count on this 
> working).

Does it really operate in the linear region?  I would have thought
that it depended on the propagation delay not being too
large, but that more gain wouldn't be a problem.  The ones I
used to know in CD4000 CMOS days used three inverters in
series to get, I thought, more gain.

-- glen


Article: 69238
Subject: Re: Connecting a crystal to a Cyclone or Max PLD
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 02 May 2004 14:59:17 +1200
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> Marc Guardiani wrote:
> 
>> David Brown wrote:
> 
> 
>>> Is it possible to connect a crystal to an Altera Cyclone or a 
> 
>  >> Max pld  rather an an external oscillator?
> 
>> Not really. You *might* be able to use a couple of pins and create an 
>> inverter between them and turn this into an oscillator. Of course, 
>> this sort of oscillator depends on using the "linear" region of an 
>> inverter which a CPLD or FPGA may not possess (ie, I wouldn't count on 
>> this working).
> 
> 
> Does it really operate in the linear region?  I would have thought
> that it depended on the propagation delay not being too
> large, but that more gain wouldn't be a problem.  The ones I
> used to know in CD4000 CMOS days used three inverters in
> series to get, I thought, more gain.

  It should operate in the linear region for best oscillator performance.
  It will oscillate with more chained-buffers, but then you have more
elements that the XTAL determining the frequency :)
  One problem is 'edge-fur' or multiple edge transistions : the Xtal
spins at the expected frequency, but the slew/edge specs fail at the 
Logic threshold, and >> 100MHz burst oscillations can result.
Very process and temperature dependant.  Not nice on a clock :)

  Pins with Hysteresis solve the transistion oscillation problem, but
moves the issue to one of two oscillation elements in parallel :
  The crystal, and also the RC-Schmitt bias feedback element.
( remove the Xtal, and it still oscillates just fine !)

  For a small solution that lets you use a Xtal, take a look at
http://www.semiconductors.philips.com/cgi-bin/pldb/pip/74LVC1GX04GV.html
-jg



Article: 69239
Subject: Re: Altera ByteBlaster II schematic
From: "Simon Peacock" <nowhere@to.be.found>
Date: Sun, 2 May 2004 15:10:59 +1200
Links: << >>  << T >>  << A >>
Basically they are the same.  if you check the pinouts all that's been done
is to make the levels far more variable.  You could probably do the same job
with 74VCX series from Fairchild except you would loose 5V operation.  (but
the comparator is a nice touch).  I have seen a 3V3/5V version of this
design but using logic gates already.

Simon

"Rene Tschaggelar" <none@none.net> wrote in message
news:40936ce6$0$715$5402220f@news.sunrise.ch...
> Leon Heller wrote:
>
> >  I just came across this schematic for the ByteBlaster II:
> >
> > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA
> >
> > Someone has probably worked out the circuit by tracing the connections
on a
> > unit as Altera hasn't published it, AFAIK.
>
> Did anyone succeed in getting it to run ?
> It appears to be too simple.  Even simpler than the MV.
> Not partwise, but from the functionality.
>
> I didn't even try as I get one from Altera.
> But, just in case one of my customers
> is going to need one ...
>
> Rene
> -- 
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net



Article: 69240
Subject: frequency multiplication
From: "Jim" <Jim@eab.nl>
Date: Sun, 2 May 2004 15:24:09 +0200
Links: << >>  << T >>  << A >>
Hi, for a re-desing i'd like to omit a 'standard' pll with counters etc.
used for
frequency multiplication, by a cpld.
Among other things, the cpld has to perform a 128x frequency multipliction
 48KHz to 6144Khz).
Some (many) cpld's have on-board pll's but these are not usefull because
they are inteded
for clock distribution and the lowest operating frequency is much lower than
48KHz.

Therefor i'd like to implement a 'dpll' in a cpld, that can multiply 48KHz
to 6144KHz, or
is there perhaps another way?

Are there any free vhdl sources for this pll?

Best,
Jim





Article: 69241
Subject: Re: CPLD input
From: Kroko <Kroko@Nil.com>
Date: Sun, 02 May 2004 21:07:28 +0200
Links: << >>  << T >>  << A >>
Thanks for your help, It actually WAS a broken input.
The behaviour is OK when I use a new chip ..


>Here's a weird thought...  Try VOLT_SENSE: in
>              -- sense power
>
>
>"Hans Maier" <Hans@Maier.com> wrote in message
>news:1f8t80lcr6kj8ghv4dao4qb6spbfhvrct1@4ax.com...
>> >  You could clarify if your 50mA meant 50 microamps, or
>> >50 milliamps. Many times I've seen the greek 'u' in uA
>> >morph into mA on the internet as it jumps fonts....
>> >  50uA could be a normal pin pullup, 50mA sounds like
>> >the PFET is on.
>>
>> it is 0.050 A or 50 milliamps
>>
>>
>> >  A simple test is to try moving the function to another pin,
>> > or simply swap the pin allocates (two same-class pins).
>>
>> Thanks I will do that.
>>
>> >  If the problem stays with the pin, it's likely to be
>> >chip related, if it moves with the function, suspect something
>> >in your code...
>>
>> code is very simple:
>>
>> VCC_SENSE: in    std_logic;                       -- sense power
>>
>>
>


Article: 69242
Subject: Re: Connecting a crystal to a Cyclone or Max PLD
From: "Kasper Pedersen" <ngfilter@kasperkp.dk>
Date: Sun, 2 May 2004 22:49:26 +0200
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:LrZkc.885$s3.102775@news02.tsnz.net...
>   Pins with Hysteresis solve the transistion oscillation problem, but
> moves the issue to one of two oscillation elements in parallel :
>   The crystal, and also the RC-Schmitt bias feedback element.
> ( remove the Xtal, and it still oscillates just fine !)
>

Not only that, but the xtal is capacitive, and forms a divider with the
input-load capacitor.
If you take a CoolrunnerXL and try to use a clock input for input (since it
has no pullup or bus hold), the shoot through is enough to overcome the
hysteresis, giving you a 100+MHz oscillator. You can try to tweak it by
adding series resistors but then the darn thing won't oscillate.

Been there, redone that. It was power-ramp dependant, temperature dependant,
look-at-dependant and debug-unfriendly.

/Kasper
Digital people should leave their digital shoes behind when wandering into
the analog domain.



Article: 69243
Subject: Cheap SRAM?
From: Florian Student <studenfn@trick.informatik.uni-stuttgart.de>
Date: Sun, 02 May 2004 23:57:28 +0200
Links: << >>  << T >>  << A >>
Hi comp.arch.fpga,

I know it's a bit off-topic but because I think that some of you might 
be able to help me I'll ask anyway.

I'm planning to connect some ram to a cpld for fast data acquisition. 
Probably using sram instead of dram should be easier because no refresh 
signal is needed and it might also be faster(?)

Does anybody of you have a recommendation what device I should use; it 
should have >= 1 MBit capacity and not be to expensive. Also, it should 
be possible to order very low quantities of it.

Thank you in advance,
   Florian







Article: 69244
Subject: Behavioural Simulation of a RPM using ModelSim XE
From: josh_graham5@hotmail.com (Josh Graham)
Date: 2 May 2004 21:50:56 -0700
Links: << >>  << T >>  << A >>
Hello all,
I have created a RPM using XST (ISE) 6.2i. Now I want to include this
in another design and do a behavioural simulation of this new design.
The RPM has been created after PAR and the netlist (ngc file) contains
placement and other constraints. I can do a successful post PAR
simulation of the new design which includes this RPM but Modelsim
fails to do a behavioural simulation. It complains about not finding a
default binding for the RPM entity.
I am starting ModelSim from ISE Project Navigator.
Can anybody please help me with this, how can I do a behavioural
simulation ?
Thanks
Josh

Article: 69245
Subject: Re: EDK 3.2
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Mon, 3 May 2004 09:49:34 +0200
Links: << >>  << T >>  << A >>
Check your environment variables XILINX and XILINX_EDK. The must point to
the correct versions (I guess you have multiple ISE versions and/or EDK
versions installed?).

Frank

"Vinod" <vananth@gmail.com> wrote in message
news:6cd79f5.0404290353.72cc5a88@posting.google.com...
> Hi,
> I am having problems starting up the Xilinx Platform Studio. I have
> installed EDK 3.2 with service pack 2. When I run it, I get a message
> saying
>
> "The procedure entry point
> ?GetProjectToolBarID@Dco_PlToolBarManager@@SAIXZ could not be located
> in the dynamic link library libDco_Plugin.dll"
>
> Im running Windows XP professional with SP1. Also have Xilinx ISE
> 5.1.3i installed. My env variables seem to be pointing to the correct
> location. I've tried reinstalling, but of no avail.
>
> Any help will be appreciated.
>
> Vinod



Article: 69246
Subject: Re: Connecting a crystal to a Cyclone or Max PLD
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Mon, 3 May 2004 09:49:51 +0200
Links: << >>  << T >>  << A >>
>
> Been there, redone that. It was power-ramp dependant, temperature
dependant,
> look-at-dependant and debug-unfriendly.
>

Ah well, it looks like the answer to my question is "no" - at least if I
want the card to work reliably!

Thanks to those that replied.

David




Article: 69247
Subject: Re: Cheap SRAM?
From: "Dave Garnett" <dave.garnett@metapurple.co.uk>
Date: Mon, 3 May 2004 09:20:00 +0100
Links: << >>  << T >>  << A >>
A good place to start is something like the DigiKey catalogue (because they
will happily sell you one of !). Cypress, for instance make a wide range of
async and sync srams - however, your choice may well be limited by the
package types available. Many devices now are only available in surface
mount and the high performance ones really need to be mounted on something
with proper ground and power planes.

If you are thinking faster than 80MHz, then Synchronous is the way to go (or
you could double buffer, or go narrow->wide in the cpld). The possibilities
are endless ...

If you went to something like a spartan IIe fpga, then you could use the
internal memory as part of the buffering strategy, and get a more flexible
architecture than you would with the cpld !!

enjoy !

Dave

"Florian Student" <studenfn@trick.informatik.uni-stuttgart.de> wrote in
message news:c73qvi$aju$1@inf2.informatik.uni-stuttgart.de...
> Hi comp.arch.fpga,
>
> I know it's a bit off-topic but because I think that some of you might
> be able to help me I'll ask anyway.
>
> I'm planning to connect some ram to a cpld for fast data acquisition.
> Probably using sram instead of dram should be easier because no refresh
> signal is needed and it might also be faster(?)
>
> Does anybody of you have a recommendation what device I should use; it
> should have >= 1 MBit capacity and not be to expensive. Also, it should
> be possible to order very low quantities of it.
>
> Thank you in advance,
>    Florian
>
>
>
>
>
>



Article: 69248
Subject: [ANN] Altera Cyclone EP1C12 FPGA Board
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Mon, 03 May 2004 10:00:23 GMT
Links: << >>  << T >>  << A >>
The successful Cyclone EP1C6 FPGA module is now available with the larger
Cyclon EP1C12. The board is an ideal module for SoC design with soft-core
CPUs such as NIOS or JOP. Additional to the FPGA it conatins a three
stage memory hirarchy:

    Fast asynchron memory as main memory.
    Conventional Flash for coniguration data and application.
    A big NAND Flash for solide state disc.

The board comes as module ready to be plugged in your expansion board or
an an expansion board with Ethernet connection.
The board is not only usefull for FPGA prototyping, but is a ready to use
module for your application board. Ask for price on larger quantities.

The Facts:

    Altera Cyclone EP1C6Q240 or EP1C12Q240 FPGA
    Step down voltage regulator (1V5)
    Crystal clock (20 MHz) at the PLL input (up to 640 MHz)
    512KB Flash (for FPGA configuration and program)
    up to 1MB fast async Ram
    up to 128MB NAND Flash
    ByteBlasterMV port
    Watchdog with LED
    EPM7064 PLD to configure Cyclone from flash (on watchdog reset)
    serial interface (MAX3232)
    56 general IO pins

The RAM consists of two independent 16 Bit banks (with own address and
control lines). Both RAM chips are on the back side of the PCB direct
under the FPGA pins. The traces are very short (below 10 mm) so it is
possible to use the RAMs at full speed without reflection problems. The
two banks can be combined to form 32 Bit RAM or support two independent
CPU cores (A dual processor system in a FPGA :-).

Further information: http://www.jopdesign.com/cyclone/index.jsp

Kind regards
Martin Schoeberl
martin@jopdesign.com





Article: 69249
Subject: Re: EDK 3.2
From: Vinod <vinod@nospam.net>
Date: Mon, 03 May 2004 05:51:34 -0700
Links: << >>  << T >>  << A >>
Yes they are pointing to the correct locations. Also I have Xilinx ISE
5.2.3i and not 5.1.3i .. so thats not the problem.

any other suggestions?

thanks
vinod

On Mon, 3 May 2004 09:49:34 +0200, "Frank van Eijkelenburg"
<someone@work.com> wrote:

>Check your environment variables XILINX and XILINX_EDK. The must point to
>the correct versions (I guess you have multiple ISE versions and/or EDK
>versions installed?).
>
>Frank
>
>"Vinod" <vananth@gmail.com> wrote in message
>news:6cd79f5.0404290353.72cc5a88@posting.google.com...
>> Hi,
>> I am having problems starting up the Xilinx Platform Studio. I have
>> installed EDK 3.2 with service pack 2. When I run it, I get a message
>> saying
>>
>> "The procedure entry point
>> ?GetProjectToolBarID@Dco_PlToolBarManager@@SAIXZ could not be located
>> in the dynamic link library libDco_Plugin.dll"
>>
>> Im running Windows XP professional with SP1. Also have Xilinx ISE
>> 5.1.3i installed. My env variables seem to be pointing to the correct
>> location. I've tried reinstalling, but of no avail.
>>
>> Any help will be appreciated.
>>
>> Vinod
>




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