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Thanks Ulf, your implemention works fine! :-) I think my problem was the <while ... loop> constuct. Changing this to a defined loop <for I in 1 to 31 loop> works. Maybe there is a problem with FPGA Express 3.4. "Ulf Samuelsson" <ulf@atmel.spammenot.com> schrieb im Newsbeitrag news:i%IJ5.4917$Z75.10786@nntpserver.swip.net... > Try this one which I happened to write Yesterday ! > It is not general purpose, but it is good enough for the intended use > and does not use nasty divisions... > > > > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > library WORK; > use WORK.all; > package MATH is > function LOG2(MAXADDRESS : INTEGER) return INTEGER; > end MATH; > > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > library WORK; > use WORK.all; > package body MATH is > -- Will work for up to 32 bit > function LOG2(MAXADDRESS : INTEGER) return INTEGER is > variable temp : INTEGER; > begin > temp := 2; > for I in 1 to 31 loop > if(temp > MAXADDRESS) then > return I; > end if; > temp := temp + temp; > end loop; > return 32; > end; > > end MATH; > > > -- > Best regards, > ulf at atmel dot com > The contents of this message is intended to be my private opinion and > may or may not be shared by my employer Atmel Sweden > > "Peter Lang" <Peter.Lang@rmvmachinevision.de> wrote in message > news:8t6m9d$abi$00$1@news.t-online.com... > > Hi, > > I am doing my first steps in VHDL. > > I wanted to implement a log2-function using > > Xilinx Foundation 3.1i with Synopsis FPGA Express 3.4. > > I tried the following source-code, which I found here in the newsgroup. > > But the Compiler found an error > > > > Dpm: Error: Non-static loop or event waits in only some branches detected > > > > I have no idea whats wrong. > > > > > > package MATH is > > function log2 ( num : integer) return integer; > > end MATH; > > > > package body MATH is > > function log2 ( num : integer) return integer is > > variable diviser : integer; -- Divided to > form > > result > > variable acc : integer; -- accumulates > > result > > begin > > diviser := num; > > acc := 0; > > LogLoop : while (diviser >= 2) loop > > diviser := diviser / 2; > > acc := acc + 1; > > end loop LogLoop; > > return acc; > > end function log2; > > end MATH; > > > > > > > > > >Article: 26726
Hi, Maybe a stupid question but, How can I compile a hierarchical VHDL Design to a single LIB-Object? This LIB-Object I want to use in a schematic top-level design. I yet found only the possibility to include single VHDL sourcefiles into a schematic top-level design by using <create macro>. But I have there many underlaying (hierarchical)VHDL Files. I am using Xilinx Foundation 3.1i with Synopsis FPGA Express 3.4.Article: 26727
http://www.cmosexod.com/Article: 26728
I'm trying to use the GSR network in my design but I keep getting the infamous "there is not a unique net that sets or resets..." error. My project consists of six modules, a root module that just includes the other five, and the other five modeuls. I can compile each of the five modules into it's own project and they work fine using the GSR network. But when I put them together *poof* I get the errror message. Does anyone have any ideas how I can figure out what is causing this ? I'm using student edition 1.5 software. PS. How do you figure out where inferred latches are ? I spent several hours breaking source code down and assembling it piecemeal to locate a couple of inferred latches. There has got to be a better way. (There aren't any inferred in my design anymore). Thanks RobArticle: 26729
In article <39F57AF3.DACE8CD1@hephy.oeaw.ac.at>, Franz Hollerer <hollerer@hephy.oeaw.ac.at> wrote: > Hi, > > I have some questions about timing simulation and I hope > that somebody can help me. > > The Xilinx software creates time_sim.vhd and time_sim.sdf. > I now want to do a timing simulation with Fusion/SpeedWave. > It principally works. But if I choose time_sim.sdf for further > timing data, fusion prints a lot of error messages (see below). > > Do I really need the .sdf file for a correct timing simulation or is > the > time_sim.vhd file enough? > > Any hints? > > Thanks > Franz Hollerer > > ---------------------------------------------------------------------- - > error message > ---------------------------------------------------------------------- - > Starting VITAL SDF Backannotation. > Processing SDF file: D:\hollerer\vhdl\tcs\export_dir\time_sim.sdf > Hierarchical Path Prefix: / > Timing mode: Max > Hierarchy divider character: / > Timescale factor: 0.001 ns > ** Error at SDF file line number 21: > For this hierarchical path name in the SDF file: > '/PRE1_CNT_REG_0_Q' > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > ** Error at SDF file line number 22: > For this hierarchical path name in the SDF file: > '/PRE1_CNT_REG_0_Q' > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > ** Error at SDF file line number 23: > For this hierarchical path name in the SDF file: > '/PRE1_CNT_REG_0_Q' > : > : > : > and so on > > -- > Institut fuer Hochenergiephysik > Nikolsdorfer Gasse 18 > 1050 Wien > Austria > > Tel: (+43-1)5447328/50 > > Hello, I think you failed to indicate the Hierarchical Path Prefix for the sdf-file. Your sdf-file describes the timing relative to your synthesized entity, but during simulation your this entity is not the top level. During simulation your testbench is the the top level entity (root) and the synthesized entity is only a subentity. Therefore you have to specify the path to the subentity together with the sdf-file to which it applies. For instance, if the instance name of your synthesized entity in the testbench is "DUT", then your hierarchical path prefix must be "/DUT" Hope this helps. -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26730
hello: when i am doing timing simulator for a project,the follwoing message occures: "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." what's meaning?how do i? Best regradsArticle: 26731
ASICs have a considerable NRE, so they make sense when volumes are high enough to amortize the NRE far enough to make the per unit cost cheaper than an FPGA. Another place ASIC make sense is in the performance/density corner that FPGAs can't hit (yet). That corner has gotten progressively smaller every year. korg wrote: > > Hi there! > > I would like to know where can I look for this topic and if you have some > tipps plz, tell me. > > tx > > korg -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26732
Well now the cat's out of the bag, I'll jump in. As I understand it, only the key is kept by the battery back up, so while there is a chance of upset from these things, the probability is much smaller than the chance of upset on an entire device. The device can still be programmed in the clear, it just won't accept the encrypted bitstream anymore. eml@riverside-machines.com.NOSPAM wrote: > > On 25 Oct 2000 20:25:39 GMT, nweaver@soda.CSUA.Berkeley.EDU (Nicholas > Weaver) wrote: > > > This model only requires that I hook up a battery to 2 > >specific pins on the device, with no other external or internal logic > >required, yet it brings security ALMOST to the level of a battery > >backed up device with the configuration loaded/always on. > > Yes, I agree - it's a lot more practical and may even be feasible in a > real product. But look at it from the customer's point of view. If > something does go wrong (sunspots? lightning? someone brings their > radioactive watch dial too close to the case? whatever..) then they > have to return the box to the manufacturer to get it fixed. > > PC's used to (still have?) a battery-backed CMOS RAM. It hasn't > happened to me over the last few years, but I'm pretty sure that I've > had problems with the RAM being corrupted. I'm also pretty sure that I > wouldn't have bought the PC in the first place if it had to be shipped > back to the (possibly defunct) manufacturer to reload the CMOS. > > Evan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26733
Hello, I was wondering if it is possible to use a Virtex BUFG buffer to drive a non clock signal ( in my case it is a CE signal with a very heavy fan-out (all DFF CE ports)) StevenArticle: 26734
On Thu, 26 Oct 2000 09:18:45 GMT, eml@riverside-machines.com.NOSPAM wrote: >I look forward to the fully-documented traffic light controller design >feature, a subject close to everyone's heart here... > >Evan Tee hee hee....I think I'll skip this one, but thanks for the suggestion. Metastability, on the other hand....... Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: http://www.ednmag.com Contributing Editor, CommVerge Magazine: http://www.commvergemag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 26735
In article <39f7f665.4748475@news.dial.pipex.com>, eml@riverside-machines.com.NOSPAM () wrote: > I > suspect that a lot of FPGA security is like this - the engineer thinks > that it's his hard work that has to be protected, but the real secret > is something completely different Agree 100% -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 26736
Rob Finch wrote: > > I'm trying to use the GSR network in my design but I keep getting the > infamous "there is not a unique net that sets or resets..." error. > My project consists of six modules, a root module that just includes the > other five, and the other five modeuls. > I can compile each of the five modules into it's own project and they work > fine using the GSR network. But when I put them together *poof* I get the > errror message. > Does anyone have any ideas how I can figure out what is causing this ? > I'm using student edition 1.5 software. You've got to make sure the all flops with async resets in your design are connected to the same reset net. Get out the fine-tooth comb. Actually, there should be a report that tells you which flops don't use the global reset. Are you using LogiCORE things? You have to check the box that says "Ignore black boxes for GSR" in the P+R GUI somewhere. (I'm on 3.1i; I think it's been changed since 1.5.) > PS. How do you figure out where inferred latches are ? I spent several hours > breaking source code down and assembling it piecemeal to locate a couple of > inferred latches. There has got to be a better way. (There aren't any > inferred in my design anymore). There should be a report that tells you where latches are inferred. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26737
>ASICs have a considerable NRE, so they make sense when volumes are high enough >to amortize the NRE far enough to make the per unit cost cheaper than an FPGA. >Another place ASIC make sense is in the performance/density corner that FPGAs >can't hit (yet). That corner has gotten progressively smaller every year. Digital-only ASICs (as opposed to mixed analog+digital) have quite low NREs, below $10k for a reasonably straightforward FPGA -> ASIC conversion using a netlist. Last time I looked was 2 years ago and a 10k gate job was US$ 8k (in the UK) from several vendors. The device, in 20k lots, was about $4. And no need for a config PROM. And no "issues" with heavy startup Icc as mentioned in this NG recently; you can get some really nice low power, low voltage technologies. And you can get big benefits in dynamic Icc, say 5x less, because one isn't driving all those large clock nets. You can also do clock gating all over the place which can reduce the dynamic Icc much further still. However while one would always prototype the design in an FPGA first, clock gating is hard to prototype because the FPGA interconnect delays can play havoc with that... Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26738
Any preferences (or gotchas) regarding Mentor/Exemplar/Leonardo/Whatever they call it and Synopsys FPGA Compiler 2? Interested in how well they both support block level (incremental) synthesis as well as Xilinx floorplanner integration. I am going out on a limb and assuming that synthesis results are likely similar. Please let me know if that is a stupid assumption. I am also interested in automatic pipeline balancing. I thought that Synopsys Design Compiler does this, but I don't know that any FPGA tool does (Synplicity does for multiplier's and ROM's, but I want it for any synchronous block). Any other opinions are welcome. I am attempting to eval them both, but with other responsibilities and such ... well, you know how it is :-) Cheers, Gary spivey@rincon.comArticle: 26739
Nope, That's one of the problems with the VIrtex architecture. They tell you to use the "low skew routing resource" ie secondary clock network for this, but I find it is way too slow compared to the speed of designs I can do in the part. The only viable solution I have found is to pipeline the CE's in a distribution tree. Steven Derrien wrote: > > Hello, > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a > non clock signal ( in my case it is a CE signal with a very heavy > fan-out (all DFF CE ports)) > > Steven -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26740
It jsut means that the addresses on both ports are the same, both sides are enabled, and one side has the write enable active. The read data in this case may not be valid. If in the context of your system, that is OK, then you can ignore it (this happens sometimes coming out of reset for example) chsw wrote: > > hello: > when i am doing timing simulator for a project,the follwoing message occures: > "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." > what's meaning?how do i? > Best regrads -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26741
What you are saying is that Xilinx needs a new packaging option that embeds some deadly, heat resistant virus in addition to the DES core - so that nobody could open the chip. Could become a new MIL spec. Kolja > OR, you just don't let the attacker get the box. :) > > Although you COLUD make the stakes higher by embedding your > chip in a large quantity of high explosive (or nerve gas, or something > else similarly nasty), encased in a very fine sensor mesh and covered > in solid plastic, REALLY hard to get at and well, an error on the > attacker's part would be a bit catastrophic. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26742
My apologies for posting in this group I am very eager to let people know about an excellent opportunity. I do not mean to offend and if anybody could direct me to a group that would be suitable it would be much appreciated. Our client a semi-conductor company with location's worldwide. They are looking for ASIC design engineers for their Irvine California location. We are able to relocate people and are able to offer visa sponsorship for non us residents. ASIC Customer Engineer (2 years ASIC experience) Responsibilities: ASIC Customer Engineer will be responsible for supporting customers who are designing ASIC's. This includes consulting with customers to ensure reliability, manufacturability, and testability of their designs. This position involves digital logic design, test vector generation, evaluating the feasibility of customer's circuits and design methodology including HDL coding simulation, synthesis and general customer support. Requirments: · 5 years of ASIC design experience · BSCS or BSEE · Technical understanding of ASIC design flow, including activities such as logic design · Verilog or VHDL coding and the use of typical CAE tools used to support product development · Good interpersonal communication skills for working effectively with customers and tracking customer schedules and issues. · Ability to multitask · Use of UNIX utilities such as Perl, C/C++, and HTML ASIC Customer Engineer (5 years of ASIC experience) Responsibilities: The ASIC Customer Engineer enables successful SIC projects by working in close conjunction with the customer during all phases of the ASIC design process from sales quotation through ASIC netlist construction, layout, tapeout and prototype delivery. In this role, the engineer serves as a consultant to the customer on all aspects of ASIC design. Conduct design reviews to assure that customers design submission meets rigorous criteria for assuring Right-first-time silicon. Architecture and implement the physical design of the ASIC through cell placement/globe route and ensure that the design meets area and timing objectives. Position involves digital logical design, synthesis, static timing analysis, physical design, test insertion/creation, formal verification, power and crosstalk analysis, extensive UNIX scripting and usage of state of the art design flow and methodologies to assure design objectives and schedules are met. Create and communicate schedules, interface to internal organizations and set customer expectation. Requirements: · 2 years of ASIC design experience · BSCS or BSEE · Technical understanding of ASIC design flow, including activities such as logic design · Verilog or VHDL coding and the use of typical CAE tools used to support product development · Ability to multitask · Use of UNIX utilities and programming such as perl, TCL scheme and Python ASIC Development Engineer Mint Technologies delivers architecture, design, verification and backend engineering for industry leading companies. You will be part of a dynamic team that is dedicated to making our clients successful. We have a diverse client base that offers you a chance to work with many different technologies and industries. Candidates will be part of a Mint Technology team that can be involved of all aspects of the ASIC development flow. ASIC design roles comprise the majority of the following: · Architecture and micro-architecture of systems and ASIC's · Writing functional specifications, design of ASIC's, RTL · Synthesis of ASIC's including synthesis scripts · Timing Analysis and Closure, design for Test-Scan, JTAG, ATPG, BIST · Vendor specific test vector creations, etc., and sign -off process for ASIC Vendors ASIC verification roles comprise the majority of the following: · Creation of verification strategies and platforms · Creation of verification environments, behavioral modeling, co-verification, · Creating of testplans and functional verification at both Unit and System Level Requirements: · 3 years of ASIC Design · Strong technical skills and excellent communication skills · Must be a self-starter!! · HDL (Verilog and/or VHDL), C/C++ and Perl knowledge Paul Lyons Atlas Technologies Tel: 562-437-1141 Fax:562-436-8508 -- Paul Lyons Atlas Technologies Tel: 562-437-1141 Fax:562-436-8508Article: 26743
hello: sorry ,the capacity of the dual block ram i ever mentioned is 16x1024--64x256,but i replace it with 16x2048---64x512,it is right,and the phenomena of the warning is not .why? Best regards.Article: 26744
yuryws@my-deja.com wrote: > > In article <39F50553.C9598332@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > > I am missing something here. If you delay the clk by 9 nS and the data > > by 16 nS, with a 6 nS setup time, you will *miss* the timing window > by 1 > > nS. So the tool is correct, no? > > The tool is correct in the first instance. In addistion, if the data > where only to change on each rising edge of the clock, and the data > were to be valid for a duration of a clock period then the tool would > be correct in the second instance as well, however data is only valid > for a short window of time centred around each clock edge. This is the > source of the problems. I am still not getting it. In the second case, what is the tool telling you? I don't know what "8 nS of slack" means. Is that good or bad? To me it looks like you are not meeting the requirements in either the first or the second case and the tool is telling you that. It has been awhile since I have looked at a Xilinx timing report, but I believe it very clearly tells you if you "meet" the timing constraint or not. Then it reports "slack" as the amount by which you beat the constraint. I don't know, but I am pretty sure that the tool does not assume if you specify x nS of setup that you have "period" - x as a hold time. The tool does not consider hold time since that is assumed to be taken care of by the design method and not by "minimum" timing analysis which the tool does not do. But this all depends on how you specify the constraint. > > yuryws@my-deja.com wrote: > > > > > > The problem with using only OFFSET IN BEFORE is that my data is > valid > > > for a fraction of clock period only around each clock edge, so for > > > example say OFFSET IN BEFORE = 6 ns, the tools will find that the > > > following two results are accepatable: > > > > > > For the sake of discussion let the clock period be 60 ns. > > > > > > 1) CLK delayed by 9 ns, Data delayed by 16 ns (the tool will > report 1 > > > ns slack (16-(9+6)), which is OK) > > > 2) CLK delayed by 2 ns, Data delayed by 16 ns (the tool will > report 8 > > > ns slack (16-(2+6)), which is not OK, since my data is invalid in > this > > > region (data is only valid for 6 ns before and after each edge). > > > > > > In addition the tools may have a difficult time meeting the > constraints > > > specified, because the tools does not take advatage of the fact > that the > > > clock edge could be ahead of data by as much as 6 ns. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26745
I can't be sure about the utility in this case, since we are talking about very small geometries, but I took an electron microscope course about 20 some years ago and we could easily detect the charge on a bit line in a live CMOS device. I expect that as the geometries shrink, this gets harder to do as the electric fields overlap a lot in the tight quarters. But we were even able to watch circuits run in real time, just not very fast since your eye can only see so much change. I would expect the lid could be popped off of a chip and monitored in an EM if the board will fit on the stage. Nicholas Weaver wrote: > > >>On Fri, 20 Oct 2000 10:12:50 GMT, kolja@prowokulta.org wrote: > >>>There is - expensive - equipment that can read the content of SRAM > >>>cells. This would even break Xilinx Virtex-II DES approach. > > Fortunatly, the barrier to do this is potentially nearly equal > [1] to probing a battery backed up FPGA, so it is very hard, just not > impossible. Trusted clients are a myth. > > [1] Having not seen the actual implementation, there MAY be holes that > could be exploited. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26746
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Article: 26747¦³¿³½ì¨ìnews¤W¬Ý¬Ý comp.lang.fpga comp.lang.verilog ³o¨Ç³£¬Ohardware¬ÛÃöªº³]p¡C(µwÅé¸ò³nÅ馳®t¶Ü¡H)Article: 26748
rickman wrote: > > I can't be sure about the utility in this case, since we are talking > about very small geometries, but I took an electron microscope course > about 20 some years ago and we could easily detect the charge on a bit > line in a live CMOS device. I expect that as the geometries shrink, this > gets harder to do as the electric fields overlap a lot in the tight > quarters. > > But we were even able to watch circuits run in real time, just not very > fast since your eye can only see so much change. I would expect the lid > could be popped off of a chip and monitored in an EM if the board will > fit on the stage. Does the SEM not have enough energy to disturb things like RAM cells ? With FPGA's having 4 layers of metal (& Up), and LUT arrays, seeing the right info will be challenging enough, ( a long way from single poly/single metal ) but getting enough pattern coverage so you can decide what the logic is in the LUT would be very hard. -jgArticle: 26749
Is it just me, or are the Spartan2/VirtexE parts in short supply? I've checked several distributors, and while they do have *some* parts in stock, more parts are listed as 'ASK' or 'NOT AVAIL.' Yet visiting Xilinx's page, Xilinx would still have you believe the $10 for 100,000k gates is just around the corner. $10 if you can find it?
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