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"Ray Andraka" <ray@andraka.com> wrote in message news:39F4A4B8.EC6B9127@andraka.com... > Unfortunately, I don't think this will help for the multilinx cable. The fine > print says it won't work for digital cameras, usb scanners, or mice with extra > buttons. Sounds like it is pretty much a driver to handle a few generic > devices. If anyone learns anything different let us know. I would agree with that, although if the people at Xilinx take any interest, I imagine it wouldn't actually be too hard to port their Multilinx driver for Windows 98 (which is undoubtedly talking to the USB bus driver, not the USB hardware itself) to work with the NT 4 USB driver from BlueWater Systems, since I believe it provides a very similar (albeit not identical) interface to USB devices. On the other hand... does upgrading to Windows 2000 help? It has native USB support, of course, but I don't know if the Multilinx driver works under it. In theory it should (Microsoft will tell you this...), but in practice some USB drivers have difficulties running the exact same binary under Win98 and Win2K. ---Joel KolstadArticle: 26676
"Frank Z.F Xie" wrote: > Hi, there > > Currently I was running some test case with Xilinx VirtexE device. But I > found the Tco time of it is quite long, for a simple DFF, the Tco is around > 6ns for device XCV100E-8CS144. I used constraint editor to control time, but > no good result. I'm not quite familiar with floorplanner. Does anyone know > how to reduce it, to around 4ns. > > Thanks > > -- > > Zhengfan Xie > frank_xie@writeme.com I assume that this FF is driving an output so (1) Make sure the FF is mapped into an IOB. (2) Set the slew rate to fast [this doesn't apply to all IO standards]. (3) Maybe increase the current drive. For IOB FFs there are a couple of tables in the Virtex-E data sheet that allow you to calculate the max Tco for various IO standards [LVTTL, SSTL2/4, HSTL, etc]. You will need to know or guestimate the capacitive loading on the output.Article: 26677
Also, use the DLL for clock distribution. Rick Filipkiewicz wrote: > > "Frank Z.F Xie" wrote: > > > Hi, there > > > > Currently I was running some test case with Xilinx VirtexE device. But I > > found the Tco time of it is quite long, for a simple DFF, the Tco is around > > 6ns for device XCV100E-8CS144. I used constraint editor to control time, but > > no good result. I'm not quite familiar with floorplanner. Does anyone know > > how to reduce it, to around 4ns. > > > > Thanks > > > > -- > > > > Zhengfan Xie > > frank_xie@writeme.com > > I assume that this FF is driving an output so > > (1) Make sure the FF is mapped into an IOB. > > (2) Set the slew rate to fast [this doesn't apply to all IO standards]. > > (3) Maybe increase the current drive. > > For IOB FFs there are a couple of tables in the Virtex-E data sheet that allow > you to calculate the max Tco for various IO standards [LVTTL, SSTL2/4, HSTL, > etc]. You will need to know or guestimate the capacitive loading on the output. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26678
Thanks for the info David DanArticle: 26679
Folks, For anyone out there who has been looking for an ultra-low-cost evaluation board to get started on Verilog/VHDL, the wait is nearly over.... For about US$25 (estimate) you can get a complete board ready to go. Check it out at www.cmosexod.com (not inappropriate). regards, -joonArticle: 26680
In article <39F50553.C9598332@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > I am missing something here. If you delay the clk by 9 nS and the data > by 16 nS, with a 6 nS setup time, you will *miss* the timing window by 1 > nS. So the tool is correct, no? The tool is correct in the first instance. In addistion, if the data where only to change on each rising edge of the clock, and the data were to be valid for a duration of a clock period then the tool would be correct in the second instance as well, however data is only valid for a short window of time centred around each clock edge. This is the source of the problems. > > yuryws@my-deja.com wrote: > > > > The problem with using only OFFSET IN BEFORE is that my data is valid > > for a fraction of clock period only around each clock edge, so for > > example say OFFSET IN BEFORE = 6 ns, the tools will find that the > > following two results are accepatable: > > > > For the sake of discussion let the clock period be 60 ns. > > > > 1) CLK delayed by 9 ns, Data delayed by 16 ns (the tool will report 1 > > ns slack (16-(9+6)), which is OK) > > 2) CLK delayed by 2 ns, Data delayed by 16 ns (the tool will report 8 > > ns slack (16-(2+6)), which is not OK, since my data is invalid in this > > region (data is only valid for 6 ns before and after each edge). > > > > In addition the tools may have a difficult time meeting the constraints > > specified, because the tools does not take advatage of the fact that the > > clock edge could be ahead of data by as much as 6 ns. > > > > -- Yury > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26681
The clock comes from an external source. Often the clock stops as a means of flow control. Every edge of the clock (almost) signifies a presence of the data to be latched. Would a PLL have trouble locking onto a clock like that? (latance, etc.) -- Yury In article <8t1opo$bb5$1@noao.edu>, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > rickman wrote: > > Using a DLL will fix your timing problems. Opps, I see that you are > > using (or planning to use) a SpartanXL, no DLL. You can use the two sets > > of FFs as you mentioned, but you will need to specify only one of the > > offset constraints. They way they are used, you only need to specify the > > setup time, not the hold. So you should use the OFFSET IN BEFORE > > constraint and the tool should work properly on both clock edges. > > Better yet: use an external PLL clock buffer device that's got 1X and 2X > outputs. Drive the "External Logic" from the 1X clock and the FPGA from > the 2X clock. Pay attention to board layout (make those clock lines, > including the feedback line, the same length) and you should be fine. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26682
In article <8t4r44$4rv$1@pegasus.tiscalinet.it>, "Emanuele Russo" <emanuelerusso@tiscalinet.it> wrote: > I'm a student and I've to synthetize a dual port memory in VHDL, but I've > some problems with BUSes... > ... can anyone help me with same example... > thank you, > > Emanuele Russo > > Do you have access to Xilinx tools? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26683
Hi! I want to know that what is the best method to implement the 2-D DCT/IDCT in FPGAs. According to Xilinx the best technique to implement it is the "Polynomial transform based computation of 2-D DCT/IDCT". Is that true? If yes , where the details of this method can be found? I have two papers over this subject and both of them are more or less the same--equally tedious...or if there is another efficient method anyone likes to mention.. -- Thanx --saqib yaqub-- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26684
Hello all, http://www.ednmag.com/ednmag/reg/2000/10122000/21df2.htm Please post back comments about this story. DanArticle: 26685
I ordered my MultiLinx cable three months ago (paid in advance!) and still haven't received it. -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "Juergen Otterbach" <juergen.otterbach@t-online.de> wrote in message news:39EDF273.89995C28@t-online.de... > Dear XILINX users, > for my evaluation board I want to use the download cable with the USB > port on a PC Client with two USB ports. Therefore I want to enable the > USB interface in NT. Does anybody give me a hint were to find a USB > driver? Does anybody have experience? Or should I do not even think of > it? >Article: 26686
Dan wrote: > Hello all, > > http://www.ednmag.com/ednmag/reg/2000/10122000/21df2.htm > > Please post back comments about this story. > > Dan But still no actual case histories of real design thefts. Maybe, like financial fraud, the companies concerned are too afraid of the bad publicity. Or maybe they don't want anybody to know that their WonderWidget selling at $Y can be got as CloneWidget at $Y/4 if you talk to the right person in your local pub [U.S = bar].Article: 26687
On Fri, 20 Oct 2000 10:12:50 GMT, kolja@prowokulta.org wrote: >So, what is left: >New algorithms invented by you and secret parts of known algorithms, >such as decryption keys. >Especially for the latter paranoid protection could be useful. >But, as Nick pointed out, that's almost impossible to achieve. >There is - expensive - equipment that can read the content of SRAM >cells. This would even break Xilinx Virtex-II DES approach. What do you mean by 'even break Xilinx Virtex-II DES approach'? Sounds like you know something we don't know... EvanArticle: 26688
Does anyone think it is possible to drive DDR (Double Data Rate) bus at 155Mhz from/to a programmable logic device ? In DDR bus the data changes on both clock edges. My application is half-duplex : separate driver and receiver pins. Thanks in advance for your comments, Rotem. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26689
I have been trying to program the XC18V02 xilinx prom via jtag without
any success.
The JTAG programmer WebPACK 3.1WP@.x
Application version D.21 doesn't seem to regnize the part properly.
The part is the XC18v02_pc44 I think there is a mistake in the
associated bsd file
attribute IDCODE_REGISTER of XC1802_pc44: entity is
"0000" & -- version
"0101000000000101" & -- part number
"00001001001" & -- manufacturer's id
"1"; -- required by standard
Article: 26690just look in deja for design security. This has been hashed over many times on the newsgroup. Frankly, I think Brian got alot of his material from the discussions here too, as I recognize a good deal of it. Dan wrote: > > Hello all, > > http://www.ednmag.com/ednmag/reg/2000/10122000/21df2.htm > > Please post back comments about this story. > > Dan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26691
On Wed, 25 Oct 2000 09:49:32 GMT, eml@riverside-machines.com.NOSPAM wrote: >On Fri, 20 Oct 2000 10:12:50 GMT, kolja@prowokulta.org wrote: > >>So, what is left: >>New algorithms invented by you and secret parts of known algorithms, >>such as decryption keys. >>Especially for the latter paranoid protection could be useful. >>But, as Nick pointed out, that's almost impossible to achieve. >>There is - expensive - equipment that can read the content of SRAM >>cells. This would even break Xilinx Virtex-II DES approach. > >What do you mean by 'even break Xilinx Virtex-II DES approach'? Sounds >like you know something we don't know... I just answered my own question by reading the EDN article. According to the article, Virtex-II includes "a hard-wired Triple-DES decryption block, along with two sets of 56-bit key registers and dedicated battery-backup supply-voltage inputs for only those registers, on its upcoming Virtex-II FPGAs". Funny thing is, though, that I was at a seminar two weeks ago, and this wasn't mentioned. I've got 29 pages of slides on Virtex-II, and not one of them mentions a triple-DES block, which isn't the sort of thing you'd accidentally leave out of a presentation. Anyone know any more? EvanArticle: 26692
>Well, "typical of Xilinx" is not a fair statement. >As explained in our letter to customers > >http://www.xilinx.com/products/coolpld/custnotice.htm > >we tried to get continued supply from Philips, but we were not >successful. Short of redesigning all these old parts to match our >foundry, we had to obsolete these parts sometime in 2001. >Of course, this is unpleasant and expensive for many users, and we regret >this development. >But if anybody knows a smarter solution, let me know. That article you refer to is very bland and says almost nothing. If Xilinx takes over a product line, one would tend to assume they would actually make the parts, not buy them in from somebody and print their logo on top. Anyway, I am amazed that you have (apparently) given up on the 22V10 market - at the right price the volumes are very large. Maybe that's the clue - Xilinx would rather sell 1M gate devices at $100 than 100x as many CMOS 22V10s at $1. >Aside from this problem of supply of the older parts, the Xilinx takeover >of the CoolRunner program has been a real success. How? >Philips wanted to get rid of a product line that did not fit their >company, and the ex-Philips, now Xilinx, employees in Albuquerque are >happy to work for a company that is totally focused on programmable >logic, and is putting renewed emphasis on their product line. More double speak! If the bottom line is that reasonably priced CMOS 22V10s are no longer available, I frankly don't give a damn about a "renewed emphasis" on anything!! Fortunately, in my most immediate design I have plenty of power so I can go back to the standard AMD 22V10s. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26693
RS422 swings 0 to +5V only but only IF the ground connection is present all the way through. In a simple direct connection like this seems to be, Vcm would be zero. So the signal could go straight in. > LVD itself does not have the -7V/+12V common mode range of RS422, but >if you look at a RS422 receiver, they way they deliver the wide CMVR, >is to use dropper resistors. This is true for inputs but outputs are a different animal. 99% of blown 422/485 i/face chips have their *outputs* blown, with excessive Vcm. However an FPGA obviously could not implement the differential input. He would just use one half of the 422 signal. For a short cable this will work just fine. > So, if you take the 100mV span on LVD, and a nom 1,5V bias point, >then use a 7:1 divider, you get -9V .. +13.5V common mode range, > > ie, you can trade off sensitivity for common mode range. > > If the camera is local, and unlikely to be unplugged, the FPGA+Divider >solution is practical. > If it is remote, and often de-connected then ESD protection is an >important >issue, and the separate buffers can win Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26694
I think the problem is where you are using it, not the log2 itself. Sounds like you have a loop in a process without a wait statement somewhere. This log function is for generating a constant or psuedo constant for use in things like sizing a std_logic_vector, not to synthesize a log2 circuit. Peter Lang wrote: > > Hi, > I am doing my first steps in VHDL. > I wanted to implement a log2-function using > Xilinx Foundation 3.1i with Synopsis FPGA Express 3.4. > I tried the following source-code, which I found here in the newsgroup. > But the Compiler found an error > > Dpm: Error: Non-static loop or event waits in only some branches detected > > I have no idea whats wrong. > > package MATH is > function log2 ( num : integer) return integer; > end MATH; > > package body MATH is > function log2 ( num : integer) return integer is > variable diviser : integer; -- Divided to form > result > variable acc : integer; -- accumulates > result > begin > diviser := num; > acc := 0; > LogLoop : while (diviser >= 2) loop > diviser := diviser / 2; > acc := acc + 1; > end loop LogLoop; > return acc; > end function log2; > end MATH; -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26695
In article <39F6CB31.8B586084@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >just look in deja for design security. This has been hashed over many times on >the newsgroup. Frankly, I think Brian got alot of his material from the >discussions here too, as I recognize a good deal of it. He says as much. However, the interesting bit is the rumors that Virtex 2 will have a set of battery backupped key registers and encrypted bitfile loading, which potentially makes for a very secure, very copyresistant FPGA without requiring full battery power for the entire FPGA. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 26696
>>On Fri, 20 Oct 2000 10:12:50 GMT, kolja@prowokulta.org wrote: >>>There is - expensive - equipment that can read the content of SRAM >>>cells. This would even break Xilinx Virtex-II DES approach. Fortunatly, the barrier to do this is potentially nearly equal [1] to probing a battery backed up FPGA, so it is very hard, just not impossible. Trusted clients are a myth. [1] Having not seen the actual implementation, there MAY be holes that could be exploited. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 26697
yuryws@my-deja.com wrote: > > The clock comes from an external source. Often the clock stops as a > means of flow control. [snip] Would a PLL have trouble locking > onto a clock like that? (latance, etc.) Yes! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26698
On Wed, 25 Oct 2000 13:59:28 GMT, eml@riverside-machines.com.NOSPAM wrote: >I just answered my own question by reading the EDN article. According >to the article, Virtex-II includes "a hard-wired Triple-DES decryption >block, along with two sets of 56-bit key registers and dedicated >battery-backup supply-voltage inputs for only those registers, on its >upcoming Virtex-II FPGAs". > >Funny thing is, though, that I was at a seminar two weeks ago, and >this wasn't mentioned. I've got 29 pages of slides on Virtex-II, and >not one of them mentions a triple-DES block, which isn't the sort of >thing you'd accidentally leave out of a presentation. > >Anyone know any more? > >Evan First I believe that triple-DES requires 3 keys, each of 56 bits (plus parity), so my guess is that the EDN article should say that the chip holds two sets of three 56-bit keys. As for your slides, my guess is that at the time you received it, the DES stuff was on their NDA list of features. The EDN article now publicly discloses this information. (I searched the Xilinx web site, and could not find any supporting info about this capability.) I spoke to someone at Xilinx about this, and he confirmed that to the extent of the article, what is disclosed is now public, and Brian Dipert did not reveal stuff he shouldn't have under some NDA. Philip Philip Freidin FliptronicsArticle: 26699
In article <8t2evsoh4jbg8guso10o1drhljl391dsum@4ax.com>, Philip Freidin <philip@fliptronics.com> wrote: > First I believe that triple-DES requires 3 keys, each of 56 bits > (plus parity), so my guess is that the EDN article should say that > the chip holds two sets of three 56-bit keys. No, 3DES only uses 2 keys, A and B. The procedure for encrypting a block is E(D(E(data,A),B),A). So you encrypt with key A, decrypt the result with key B, and then reencrypt with key A, so you are going through the DES function 3 times, but with only 2 keys. >As for your slides, my guess is that at the time you received it, the DES >stuff was on their NDA list of features. The EDN article now >publicly discloses this information. I suspect that as well. If so, this will be a very useful feature, although it will be interesting to see how it can be attacked. On the slides, did they have any information on partial reconfigurability on the Virtex 2? -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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