Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
LAZIO PROMISES END TO LONG ISLAND FPGA CRISIS (AP, Syosset, LI, NY, October 26) - In a bid to capture the critical FPGA hiring manager vote, Rick Lazio, Republican contender for the US Senate, vowed to end the Long Island FPGA crisis if elected. Speaking in the Syosset LIRR station to a mostly disinterested group of reporters and ordinary citizens who had missed the last train to New York City, Lazio said that filling FPGA design positions is every bit as important as remaining neutral on his favorite team in this year's World Series. "They are essential people, these FPGA designers, and we need to have more of them. If the number of postings on comp.arch.fpga is any indication, we are pretty much out of these guys, and desperately need a fresh supply. There's no telling what will happen if we don't get them, since I'm not entirely sure what they do." When asked for a reaction, Democratic candidate Hillary Clinton admitted that she doesn't know what FPGA designers do, either. But Mrs. Clinton said that she has a large number of relatives and close friends who are FPGA designers, and will make a point of asking one of them. Mr. Lazio was not available to clarify his plan of action, having left for upstate New York immediately after his announcement to give a talk on the critical shortage of Volvo mechanics in New Rochelle.Article: 26751
In article <39F8E4B6.923DDE4B@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I can't be sure about the utility in this case, since we are talking >about very small geometries, but I took an electron microscope course >about 20 some years ago and we could easily detect the charge on a bit >line in a live CMOS device. I expect that as the geometries shrink, this >gets harder to do as the electric fields overlap a lot in the tight >quarters. > >But we were even able to watch circuits run in real time, just not very >fast since your eye can only see so much change. I would expect the lid >could be popped off of a chip and monitored in an EM if the board will >fit on the stage. I suspect that this could be made more difficult, however, by some layout tricks. Since this is probably in the corner of the die [1] pretty easy to do with only a couple layers of metal, and they are undoubtedly using at least a 5 layer, if not 6 layer metal process, a solid metal layer or two over the encryption core and bitlines should make such probing considerably more difficult to non-invasively probe using an EM. Especially if the two metal planes are set up to detect a short, so that attempts to burrow through the layers to directly probe the configuration bits would prove difficult. And if some power tricks were done to isolate the power supply to make things resistant to power attacks (I think that a 3 capacitor switching system would work well, 1 always charging, one discarging to power the circuit, and one being discharged completly, in alternation, would probably work. Or circuit redesign to be constand power/encryption). Yes, it's not perfect, but the higher the bar can be raised to attack such a system, the closer it becomes to having to read out the whole configuration of a part, instead of just reading out the key. [1] next to whatever loads the configuration. DES is so small in hardware that doing some trick like having a DES configuration loaded onto the reconfigurable logic wouldn't be a significant savings, not to mention the additional design security headaches to verify that, under all conditions, a configuration couldn't be loaded which would access the key registers. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 26752
The wires for configuring by JTAG are totally seperate from those for the SPROM serial mode of configuration. If you want the option to use both methods, make sure your board has pullups & jumpers to switch the state of the mode config pins (M2:0). If you use the new 18xxx series of SPROMs, note that they are also JTAG configurable and their JTAG can be in series with that of the FPGA itself. They can be programmed at the same time or seperately w/ the other in Bypass mode. Nicolas Matringe wrote: > Hello all > I wonder if it's possible to configure an FPGA through the JTAG > interface when a PROM is connected to the device. > Won't this generate a conflict? > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 16 rue du Moulin des Bruyeres > Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE > Fax +33 1 46 67 51 01 http://www.IPricot.com/ -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 26753
Synopsys FPGA Compiler II +: a big improvement over their older versions Synopsys FPGA Compiler II -: some designs cause tool to fatal out (i.e., 'abort 219' errors) Synopsys FPGA Compiler II -: behavioral retiming (pipeline balancing) flat out doesn't work. They claim it will be fixed in next rev, but this begs the question: why did they advertise it so heavily WITHOUT TESTING IT BEFORE DELIVERY TO CUSTOMER ???? Exemplar: no experience. Synplicity Synplify +: Can not find enough good things to say about this tool. Better results and runs 10x faster than Synopsys. HDL Analyst post-synth 'schematic/block diagram' viewer is awesome. I'd sell my firstborn to get more licenses. Synplicity Synplify -: Very minor hiccups. I've sent my bug list to Synplicity, but I haven't been using the tool long enough to know how responsive they will be to my issues. We'll see how good they are when the next version comes out. Anyone want my Synplify bug list email me, and I'll send the PDF. Gary Spivey wrote: > Any preferences (or gotchas) regarding Mentor/Exemplar/Leonardo/Whatever > they call it and Synopsys FPGA Compiler 2? > > Interested in how well they both support block level (incremental) synthesis > as well as Xilinx floorplanner integration. I am going out on a limb and > assuming that synthesis results are likely similar. Please let me know if > that is a stupid assumption. > > I am also interested in automatic pipeline balancing. I thought that > Synopsys Design Compiler does this, but I don't know that any FPGA tool does > (Synplicity does for multiplier's and ROM's, but I want it for any > synchronous block). > > Any other opinions are welcome. I am attempting to eval them both, but with > other responsibilities and such ... well, you know how it is :-) > > Cheers, > Gary > spivey@rincon.com -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 26754
Hi Klaus! That's it. Thank you for your help. Now it works perfectly. Best regards, Franz Hollerer Klaus Falser wrote: > In article <39F57AF3.DACE8CD1@hephy.oeaw.ac.at>, > Franz Hollerer <hollerer@hephy.oeaw.ac.at> wrote: > > Hi, > > > > I have some questions about timing simulation and I hope > > that somebody can help me. > > > > The Xilinx software creates time_sim.vhd and time_sim.sdf. > > I now want to do a timing simulation with Fusion/SpeedWave. > > It principally works. But if I choose time_sim.sdf for further > > timing data, fusion prints a lot of error messages (see below). > > > > Do I really need the .sdf file for a correct timing simulation or is > > the > > time_sim.vhd file enough? > > > > Any hints? > > > > Thanks > > Franz Hollerer > > > > ---------------------------------------------------------------------- > - > > error message > > ---------------------------------------------------------------------- > - > > Starting VITAL SDF Backannotation. > > Processing SDF file: D:\hollerer\vhdl\tcs\export_dir\time_sim.sdf > > Hierarchical Path Prefix: / > > Timing mode: Max > > Hierarchy divider character: / > > Timescale factor: 0.001 ns > > ** Error at SDF file line number 21: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > > ** Error at SDF file line number 22: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > > ** Error at SDF file line number 23: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > : > > : > > : > > and so on > > > > -- > > Institut fuer Hochenergiephysik > > Nikolsdorfer Gasse 18 > > 1050 Wien > > Austria > > > > Tel: (+43-1)5447328/50 > > > > > > Hello, > I think you failed to indicate the Hierarchical Path Prefix for > the sdf-file. > > Your sdf-file describes the timing relative to your synthesized > entity, but during simulation your this entity is not the top level. > During simulation your testbench is the the top level entity (root) > and the synthesized entity is only a subentity. > > Therefore you have to specify the path to the subentity together > with the sdf-file to which it applies. > For instance, if the instance name of your synthesized entity > in the testbench is "DUT", > then your hierarchical path prefix must be "/DUT" > > Hope this helps. > > -- > Klaus Falser > Durst Phototechnik AG > I-39042 Brixen > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Institut fuer Hochenergiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 26755
Hi Uwe! That's very simply. I did'nt have any idea about IntelliFlow up to know. Viewlogic comes with so many programs that may do the same stuff, that it is difficult to use the right. But thx for this hint. Best regards, Franz Hollerer Uwe wrote: > Hallo Franz, > > warum benutzt Du nicht IntelliFlow, der übernimmt i.A. alle Einstellungen > und Parameter. Bei mir funktioniert dieses ganz gut. > > Gruß > Uwe > > "Franz Hollerer" <hollerer@hephy.oeaw.ac.at> schrieb im Newsbeitrag > news:39F57AF3.DACE8CD1@hephy.oeaw.ac.at... > > Hi, > > > > I have some questions about timing simulation and I hope > > that somebody can help me. > > > > The Xilinx software creates time_sim.vhd and time_sim.sdf. > > I now want to do a timing simulation with Fusion/SpeedWave. > > It principally works. But if I choose time_sim.sdf for further > > timing data, fusion prints a lot of error messages (see below). > > > > Do I really need the .sdf file for a correct timing simulation or is > > the > > time_sim.vhd file enough? > > > > Any hints? > > > > Thanks > > Franz Hollerer > > > > ----------------------------------------------------------------------- > > error message > > ----------------------------------------------------------------------- > > Starting VITAL SDF Backannotation. > > Processing SDF file: D:\hollerer\vhdl\tcs\export_dir\time_sim.sdf > > Hierarchical Path Prefix: / > > Timing mode: Max > > Hierarchy divider character: / > > Timescale factor: 0.001 ns > > ** Error at SDF file line number 21: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > > ** Error at SDF file line number 22: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design. > > ** Error at SDF file line number 23: > > For this hierarchical path name in the SDF file: > > '/PRE1_CNT_REG_0_Q' > > : > > : > > : > > and so on > > > > -- > > Institut fuer Hochenergiephysik > > Nikolsdorfer Gasse 18 > > 1050 Wien > > Austria > > > > Tel: (+43-1)5447328/50 > > > > -- Institut fuer Hochenergiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 26756
On Thu, 26 Oct 2000 20:42:53 -0700, Bob Perlman <bobperl@best_no_spam_thanks.com> wrote: >LAZIO PROMISES END TO LONG ISLAND FPGA CRISIS You are a funny man. Thanks for making this fpga designer laugh. Muzaffer http://www.dspia.comArticle: 26757
Bob Perlman <bobperl@best_no_spam_thanks.com> writes: > LAZIO PROMISES END TO LONG ISLAND FPGA CRISIS > > (AP, Syosset, LI, NY, October 26) - In a bid to capture the critical > FPGA hiring manager vote, Rick Lazio, Republican contender for the US > Senate, vowed to end the Long Island FPGA crisis if elected. Here I was thinking about italian football and its conection to US FPGA markets... Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 26758
"Magnus Homann" <d0asta@licia.dtek.chalmers.se> ha scritto nel messaggio news:ltzojqr5vv.fsf@licia.dtek.chalmers.se... > Bob Perlman <bobperl@best_no_spam_thanks.com> writes: > > > LAZIO PROMISES END TO LONG ISLAND FPGA CRISIS > > > > (AP, Syosset, LI, NY, October 26) - In a bid to capture the critical > > FPGA hiring manager vote, Rick Lazio, Republican contender for the US > > Senate, vowed to end the Long Island FPGA crisis if elected. > > Here I was thinking about italian football and its conection to US > FPGA markets... > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se Me too! But I'm italian... Renzo VenturiArticle: 26759
z80@ds2.com (Peter) writes:
> Digital-only ASICs (as opposed to mixed analog+digital) have quite low
> NREs, below $10k for a reasonably straightforward FPGA -> ASIC
I've done digital ASICs with NRE costs in the $100k range. It depends
on the vendor, technology, size, megacells etc.
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 26760Xilinx Alliance 2.1i (I am using the Unix version, but I expect the PC version is the same) gives you the option of using an earlier version of your design as the floorplan for a new version. I have never been sure exactly how this works, or how it is achieved, but the end result is that once you have got a good placement new versions (so long as the changes are relatively minor) tend to have similar placement and similar timings. As far as I can see 3.1i no longer has this option: previous versions are no longer listed in the 'floorplan' selection box. As a result even very minor changes to my design can have serious effects on the overall timing, as the placement is done from scratch. Of course I *could* do the floorplanning myself, but this means learning how to use the tool. How can I use an earlier version as a 'guide' to the placement of a new version, as I could with 2.1i (this is a Virtex design, so I can't use a guide file as such) ? Richard. http://www.rtrussell.co.uk/Article: 26761
Ray Andraka wrote: > > Nope, That's one of the problems with the VIrtex architecture. They tell you > to use the "low skew routing resource" ie secondary clock network for this, but > I find it is way too slow compared to the speed of designs I can do in the > part. The only viable solution I have found is to pipeline the CE's in a > distribution tree. Then i guess it wastes a lot of the avilable rtoung ressources (espacially if you have many flip flop/srl16 as it is my case). What about a gated clock then (I know it is supposed to be a "bad" practice in regards of the clock skew) but I don't know how limitating it might be in an FPGA... Thanks Steven > > Steven Derrien wrote: > > > > Hello, > > > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a > > non clock signal ( in my case it is a CE signal with a very heavy > > fan-out (all DFF CE ports)) > > > > Steven > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 26762
>> Digital-only ASICs (as opposed to mixed analog+digital) have quite low >> NREs, below $10k for a reasonably straightforward FPGA -> ASIC > >I've done digital ASICs with NRE costs in the $100k range. It depends >on the vendor, technology, size, megacells etc. Sure, with an on-chip Z80-lookalike and 300k gates :) But the equivalent FPGA would be a massive device, and very very expensive. In only 10k + volume the ASIC would be a very good deal despite the NRE. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26763
On Fri, 27 Oct 2000 12:02:50 +0200, "Renzo Venturi" <staff@cibernet.it> wrote: > >"Magnus Homann" <d0asta@licia.dtek.chalmers.se> ha scritto nel messaggio >news:ltzojqr5vv.fsf@licia.dtek.chalmers.se... >> Bob Perlman <bobperl@best_no_spam_thanks.com> writes: >> >> > LAZIO PROMISES END TO LONG ISLAND FPGA CRISIS >> > >> > (AP, Syosset, LI, NY, October 26) - In a bid to capture the critical >> > FPGA hiring manager vote, Rick Lazio, Republican contender for the US >> > Senate, vowed to end the Long Island FPGA crisis if elected. :-) This guy needs a faster machine for place/route jobs! >> Here I was thinking about italian football and its conection to US >> FPGA markets... >> >> Homann >> -- >> Magnus Homann, M.Sc. CS & E >> d0asta@dtek.chalmers.se > >Me too! But I'm italian... If I mention that the Sturm Graz goalkeeper's name is Schicklgruber, will that bring this thread to an end? - BrianArticle: 26764
SUre you can. Open the floorplanner on the old design, do a replace all with placement and save it. That makes a floorplan file from the automatic place and route solution. Then, when you start with a new design, select your saved floorplan as the floorplan file for the new design. As long as hierarchical names are not changed, it will work fine in 3.1 news@rtrussell.co.uk wrote: > > Xilinx Alliance 2.1i (I am using the Unix version, > but I expect the PC version is the same) gives you > the option of using an earlier version of your > design as the floorplan for a new version. I have > never been sure exactly how this works, or how it > is achieved, but the end result is that once you > have got a good placement new versions (so long as > the changes are relatively minor) tend to have > similar placement and similar timings. > > As far as I can see 3.1i no longer has this option: > previous versions are no longer listed in the > 'floorplan' selection box. As a result even very > minor changes to my design can have serious effects > on the overall timing, as the placement is done > from scratch. > > Of course I *could* do the floorplanning myself, > but this means learning how to use the tool. How > can I use an earlier version as a 'guide' to the > placement of a new version, as I could with 2.1i > (this is a Virtex design, so I can't use a guide > file as such) ? > > Richard. > http://www.rtrussell.co.uk/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26765
Don't do it. Gating means you don't have the low skew, and even worse, by gating you are no longer on the low skew clock network. That's a disaster waiting to happen. Steven Derrien wrote: > > Ray Andraka wrote: > > > > Nope, That's one of the problems with the VIrtex architecture. They tell you > > to use the "low skew routing resource" ie secondary clock network for this, but > > I find it is way too slow compared to the speed of designs I can do in the > > part. The only viable solution I have found is to pipeline the CE's in a > > distribution tree. > > Then i guess it wastes a lot of the avilable rtoung ressources > (espacially if you have many flip flop/srl16 as it is my case). What > about a gated clock then (I know it is supposed to be a "bad" practice > in regards of the clock skew) but I don't know how limitating it might > be in an FPGA... > > Thanks > Steven > > > > > Steven Derrien wrote: > > > > > > Hello, > > > > > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a > > > non clock signal ( in my case it is a CE signal with a very heavy > > > fan-out (all DFF CE ports)) > > > > > > Steven > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26766
Barry Schneider wrote: > > I am presently working at a ASIC consulting company and we have a huge > backlog of > work. We need help and will pay well. We have a great office and have > very flexible hours. We are looking for Verilog and/or VHDL experience. > Synthesis and/or Mixed Signal a plus. If you are interested in a Good Job > e-mail me at barry61s@optonline.com Waitaminit. "Flexible hours"? I guess that means, "arrive at dawn, leave sometime before 9 pm." "Verilog and/or VHDL experience"? Which one? Does that mean I get to use VHDL, even if every other engineer in the place is a Verilogger? "Synthesis and/or Mixed Signal a plus"? Seems to me that an ASIC position would REQUIRE synthesis experience. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26767
Atlas wrote: > > My apologies for posting in this group I am very eager to let people know > about an excellent opportunity. I do not mean to offend and if anybody could > direct me to a group that would be suitable it would be much appreciated. I'm not offended. I'm both annoyed and amused. > Our client a semi-conductor company with location's worldwide. Are the locations possesive? Watch that apostrophe. I also didn't realize that "semiconductor" was hyphenated. > ASIC Customer Engineer (2 years ASIC experience) > Responsibilities: [snip] > Requirments: > · 5 years of ASIC design experience Now, waitaminit. The Job Title above says, "ASIC Customer Engineer (2 years ASIC experience)," yet the first requirement is "5 years of ASIC design experience." Which is it? Make up your mind. > ASIC Customer Engineer (5 years of ASIC experience) > Responsibilities: [snip] > Requirements: > · 2 years of ASIC design experience Now, waitaminit. The Job Title above says, "ASIC Customer Engineer (5 years of ASIC experience)," the the first requirement is "2 years of ASIC design experience." Which is it? Make up your mind. -- ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26768
rickman wrote: > I am still not getting it. In the second case, what is the tool telling > you? I don't know what "8 nS of slack" means. Is that good or bad? To me > it looks like you are not meeting the requirements in either the first > or the second case and the tool is telling you that. It has been awhile > since I have looked at a Xilinx timing report, but I believe it very > clearly tells you if you "meet" the timing constraint or not. Then it > reports "slack" as the amount by which you beat the constraint. You're right -- "slack" (when not referring to the Church of the Sub-Genius") means how much you've beaten your constraint by. > I don't know, but I am pretty sure that the tool does not assume if you > specify x nS of setup that you have "period" - x as a hold time. The > tool does not consider hold time since that is assumed to be taken care > of by the design method and not by "minimum" timing analysis which the > tool does not do. If you don't specify an OFFSET constraint on the i/o, it simply assumes the period constraint applies. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 26769
eml@riverside-machines.com.NOSPAM wrote: > Funny thing is, though, that I was at a seminar two weeks ago, and > this wasn't mentioned. I've got 29 pages of slides on Virtex-II, and > not one of them mentions a triple-DES block, which isn't the sort of > thing you'd accidentally leave out of a presentation. > It wasn't accidental, it was deliberate. And there are other "goodies" that have not yet been divulged (publicly). Give us a some time to file all the patents, orchestrate the product introduction, and, last not least, characterize the silicon. Virtex-II has many novel and exciting features ! Peter AlfkeArticle: 26770
The other Peter wrote: > - Xilinx would rather sell 1M gate devices at $100 than 100x > as many CMOS 22V10s at $1. Well, wouldn't everybody, given half a chance ? Even NSC tried to get out of the jelly-bean business. > >Philips wanted to get rid of a product line that did not fit their > >company, and the ex-Philips, now Xilinx, employees in Albuquerque are > >happy to work for a company that is totally focused on programmable > >logic, and is putting renewed emphasis on their product line. > > More double speak! I thought I was using simple and straightforward language. > If the bottom line is that reasonably priced CMOS > 22V10s are no longer available, I frankly don't give a damn about a > "renewed emphasis" on anything!! The 22V10 was invented at AMD ( not MMI ) in 1980 ( I worked there at that time ). The design is thus 20 years old. We can today pack far more functionality, sophistication, and performance into a small piece of silicon. We would prefer you to migrate your design to integrate more of the total functionality into a CoolRunner or an FPGA. Why should we first break our wafer into thousands almost invisible specks of silicon, put each of them in a 24-pin package, so that you then reassemble them on an expensive pc-board? Nobody benefits from that. Whoever sells such tiny integrated circuits is not in the silicon business, but rather in the plastics, leadframe, handling, marking, and shipping business, where it is extremely difficult to reduce cost and remain profitable. Moore's law does not apply to a 22V10. Peter AlfkeArticle: 26771
The tool looks at the period constraint to determine when the data changes. It assumes that the data changes only once per clock period and is valid between the changes (which is not applicable to my case). Not to mention that i can not specify PERIOD constraint required for OFFSET IN specification, since I only have one level of registers (see the root of the discussion). -- Yury Wolf In article <39F8E322.7936D29A@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > yuryws@my-deja.com wrote: > > > > In article <39F50553.C9598332@yahoo.com>, > > rickman <spamgoeshere4@yahoo.com> wrote: > > > I am missing something here. If you delay the clk by 9 nS and the data > > > by 16 nS, with a 6 nS setup time, you will *miss* the timing window > > by 1 > > > nS. So the tool is correct, no? > > > > The tool is correct in the first instance. In addistion, if the data > > where only to change on each rising edge of the clock, and the data > > were to be valid for a duration of a clock period then the tool would > > be correct in the second instance as well, however data is only valid > > for a short window of time centred around each clock edge. This is the > > source of the problems. > > I am still not getting it. In the second case, what is the tool telling > you? I don't know what "8 nS of slack" means. Is that good or bad? To me > it looks like you are not meeting the requirements in either the first > or the second case and the tool is telling you that. It has been awhile > since I have looked at a Xilinx timing report, but I believe it very > clearly tells you if you "meet" the timing constraint or not. Then it > reports "slack" as the amount by which you beat the constraint. > > I don't know, but I am pretty sure that the tool does not assume if you > specify x nS of setup that you have "period" - x as a hold time. The > tool does not consider hold time since that is assumed to be taken care > of by the design method and not by "minimum" timing analysis which the > tool does not do. > > But this all depends on how you specify the constraint. > > > > yuryws@my-deja.com wrote: > > > > > > > > The problem with using only OFFSET IN BEFORE is that my data is > > valid > > > > for a fraction of clock period only around each clock edge, so for > > > > example say OFFSET IN BEFORE = 6 ns, the tools will find that the > > > > following two results are accepatable: > > > > > > > > For the sake of discussion let the clock period be 60 ns. > > > > > > > > 1) CLK delayed by 9 ns, Data delayed by 16 ns (the tool will > > report 1 > > > > ns slack (16-(9+6)), which is OK) > > > > 2) CLK delayed by 2 ns, Data delayed by 16 ns (the tool will > > report 8 > > > > ns slack (16-(2+6)), which is not OK, since my data is invalid in > > this > > > > region (data is only valid for 6 ns before and after each edge). > > > > > > > > In addition the tools may have a difficult time meeting the > > constraints > > > > specified, because the tools does not take advatage of the fact > > that the > > > > clock edge could be ahead of data by as much as 6 ns. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26772
hello: when i am doing timing simulator for a project,the follwoing message occures: "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." the capacity of the dual block ram i mentioned is 16x1024--64x256,but i replace it with 16x2048---64x512,it is right,and the phenomena of the warning is not .why? Best regards.Article: 26773
This is a multi-part message in MIME format. --------------996CBBD53A0AFB4A69661037 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rotem, You've probably already done this, but just in case, you might want to go to Xilinx's web site and download the application note XAPP200: "Synthesizable 1.6 GBytes/s DDR SDRAM Controller". (www.xilinx.com, click on "Products", then "Application Notes", then "Virtex"). This was written for the Virtex and Spartan-II families targeting 100MHz DDR SDRAM, and it could be potentially implimented with even higher performance in the Virtex-E family (though I'm not sure of the actual performance achievable, and 155 will be aggressive...). Recently we've added both VHDL and Verilog reference designs that you can download as well (with links right next to the one for the app note). Hope this helps, -Scott S. gazit@my-deja.com wrote: > Does anyone think it is possible to drive DDR (Double Data Rate) bus at > 155Mhz from/to a programmable logic device ? > In DDR bus the data changes on both clock edges. > My application is half-duplex : separate driver and receiver pins. > > Thanks in advance for your comments, > Rotem. > > Sent via Deja.com http://www.deja.com/ > Before you buy. --------------996CBBD53A0AFB4A69661037 Content-Type: text/x-vcard; charset=us-ascii; name="scott.schlachter.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Scott Schlachter Content-Disposition: attachment; filename="scott.schlachter.vcf" begin:vcard n:Schlachter;Scott tel;work:408-879-6876 x-mozilla-html:TRUE url:www.xilinx.com org:Xilinx;General Products Division adr:;;2100 Logic Drive;San Jose;CA;95124-3400;USA version:2.1 email;internet:scott.schlachter@xilinx.com title:Systems Engineer fn:Scott Schlachter end:vcard --------------996CBBD53A0AFB4A69661037--Article: 26774
hello: when i am doing timing simulator(using the reference design xapp205.zip :fifoctlr_ccmw1.v/fifoctlr_ccmw2.v) for a project,the follwoing message occures: "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." the capacity of the dual block ram i mentioned is 16x1024--64x256,but i replace it with 16x2048---64x512,it is right,and the phenomena of the warning is not . why? Best regards.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z