Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
The headhunter game: Object of the game: When a headhunter posts a job, the first person to find the name of the company wins 10 Quatloos. This one is easy: Acorn-Networks http://www.acorn-networks.com brian@gatesource.com wrote: > (Project Leader, Architecture Modeling) > > I'm a headhunter who specializes in Engineering, > ASIC, ATM and related fields. > ... > My client is a privately held company, specializes in the design and > manufacturing of high-performance CMOS Application Specific > Integrated Circuits (ASIC) for data communication network > equipments. The company chip sets target ATM, Frame Relay and > IP applications in > ... > traffic scheduling and shaping, and high-performance low-power circuit > design techniques, serving as a basis for Acorn Networks' baseline > communications processor architecture for OC-48c wirespeed operation, > and readily scalable to OC-192c and beyond. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26276
Jamie Lokier writes: > I'm not sure what advantage Synplicity have over the rest of us or why > they need one. All I can report is that the Altera FAE said he was sure > Synplicity had a team working in-house at Xilinx, to access information > the rest of us don't have. Sorry, I meant "in-house at Altera". -- JamieArticle: 26277
Hello, I have the errors during timing sim: setup( posedge I:40599307742 ps, negedge CLK &&& in_clk_enable:40599307983 ps, 397 ps ); What does it mean and what should I do to eliminate the error? With regards Tomasz Brychcy Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26278
In article <%asE5.2190$Np2.275948@dfiatx1-snr1.gtei.net>, Jan Gray <jsgray@acm.org> wrote: >"Anurag Tiwari" <atiwari@cs.wright.edu> wrote >> does anybody know where can I find the VHDL model of Motorola 68000 >> processor for educational use? > >I don't. But here are two sites describing commercial ones. > >Sierra Circuit Design >http://www.teleport.com/~scd/avail_ip.htm > >Digital Core Designs D68000 >http://www.dcd.com.pl/english/d68000.htm > >Perhaps Motorola has something. They should. > >Please let us know if something turns up. > >Jan Gray, Gray Research LLC >FPGA CPU News: www.fpgacpu.org VLSI Concepts also has a commercial product http://www.vlsi-concepts.com/V68000.htmlArticle: 26279
rk wrote: > > Andy Peters wrote: > > > As an example, I block cookies from almost all "consumer" sites (and if > > they require registration, I leave), but I imagine that semiconductor > > companies aren't looking to harvest your e-mail address for spammers, so > > it's not as big a deal as you make it out to be. > > I tend to block all cookies but some sites won't let you in and do > things until you turn it on or give certain information. > > Having an unsolicited phone call from a local sales rep who asks a > billion questions and won't get off the phone is a pain and, in my > opinion, a misuse of the information - and it does happen. If I wanted > to talk to a salecritter I would have called up a salescritter. The > spammers are a pain but I don't have to hang up on people. In my > opinion, looking at something on a www site and having that being > followed up by a sales call is more than a minor pain. Not a big deal > but a medium deal. Rich, Two things: 1) They don't get much info from cookies. Go through the anonymizer and they won't get your IP address. 2) Give false info when you fill out the form. It's not YOUR problem that their database gets degraded! And maybe they'll learn a lesson, or three. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26280
Ray Andraka wrote: > > Perhaps it is a disservice calling it PROGRAMMABLE logic. Seems to evoke > thoughts of cpus to the uninitiated. I suppose it doesn't help by spreading the > gospel that FPGAs can significantly outperform a CPU for a given task. Ray, "configurable logic"? New acronym: FCGA. Start spreadin' the news. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26281
Jamie Lokier wrote: > > Andy Peters writes: > >> But these are those who may make FPGAs their next (or after next) > >> job, when they get fed up with writing yet another web application. > > > Stop right there. You're thinking that a software person can design > > hardware? Sorry. Just because VHDL is a "programming language," it > > doesn't mean that a person who writes VHDL is a good hardware designer. > > There's a WHOLE LOT MORE to FPGA design -- and hardware design in > > general -- than just writing code. > > Now you'll have to trust me. I _know_ how fiddly FPGA programming can > be particularly with high speeds/multiple clocks/crappy I/O > requirements. Really, I program these things daily and have been doing > so for the last 2.5 years. My programs are part VHDL, part Handel-C. > > With a decent board design (all synchronous interfaces, registers in I/O > cells for deterministic timing), plenty of timing headroom (pick a > _fast_ FPGA then say run it at 25-50MHz), plenty of space (the big > chips), and a decent front end tool you'd be surprised. > This is not the same as "hardware design". There is no tricky I/O to > speak of. One clock domain, usually. Timing is not a problem -- the > FPGA is fast. Sure it's an expensive FPGA for the problem, but it's > cheaper than paying a hardware designer and faster when you want to > keep changing the problem. Some of us (we call ourselves "hardware designers," or perhaps even "electrical engineers") actually *do* have to deal with the tricky I/Os, and crossing clock domains, and, oh, by the way, get the thing to work in the $15 FPGA, rather than the $150 one. Throwing expensive hardware at a problem clearly IS a solution, but most customers are not willing to pay that price. BTW: I enjoy the challenge of getting a high-speed board working. Of course, it's a game you shouldn't be playing without the proper (read: expensive) tools (both hardware and software). > These folks have _no clue_ where the AND gates, OR gates and registers > are placed on the FPGA. To these folks, synthesis really is a mystery > black box. I'm not kidding. They don't even know what language > constructs will consume how much resource on the FPGA. Fortunately, > until they hit the limits, they don't need to. The problem is that they're going to hit those limits sooner than you expect. The scientists I work for are ALWAYS hitting the limits. I say it'll run at X speed, they want Y. Always. As predictable as the sun rising. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26282
I am currently having trouble with a very simple VHDL/Schematic design on M4A 32/32. Basically I have 8 bidirectional I/O pins... The outputs are connected to a register - the inputs are connected to another macro. For my understanding both the register and the I/Os should fit into 8 macrocells. But instead the synthesized design wastes 8 macrocells only on the I/Os and another 8 for the register. Currently I am using VHDL for most of the design and the schematic for the I/Os and routing between the vhdl block. Is it possible to use VHDL for the entire deisgn with ispDesignEXPERT ? And is it possible to avoid wasting 8 macrocells for I/Os only ? tyiaArticle: 26283
A quick search on Altavista for idempotent and BIST came up with these two good links: http://www.amis.com/datasheets/2page/memory_bist.html http://www.eecs.harvard.edu/cs245/papers/Davidb.html Idempotent Coupling Faults -> transition on cell A causes fixed value on cell B Not sure what a k-coupling fault is though.... "Patrick Schulz" <schulz@rumms.uni-mannheim.de> wrote in message news:39E1D3B7.15759446@rumms.uni-mannheim.de... > Hi there, > > sorry for being maybe off-topic to FPGAs, but there is a good chance for > an answer in this group as far as I prize the contents of the posted > messages. > I posted this message already to comp.arch. Unfortunately without > response. > > Does anyone know a good online source for information about RAM-BIST > algorithms and their impact on the different fault classes? > What I want to know is for example what k-coupling faults or linked > idempotent coupling faults are. > > Any help appreciated. > > Patrick > -- > Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) > University of Mannheim - Dep. of Computer Architecture > 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de > Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 26284
On 10 Oct 2000 09:49:34 +0900, Kent Orthner <korthner@hotmail.nospam.com> wrote: >Andy Peters <"apeters <"@> n o a o [.] e d u> writes: >> Stop right there. You're thinking that a software person can design >> hardware? Sorry. Just because VHDL is a "programming language," it >> doesn't mean that a person who writes VHDL is a good hardware designer. > >If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware >Description Language". the purpose of VHDL is not to program anything; you're >not telling some CPU what to do, you're describing a hardware construct. To be pedantic, a VHDL compiler takes a program written in the source language, VHDL, and converts into an equivalent program in the target language, which is probably some processor's assembler. That's the definition of a compiler (wow! the 2nd time I've quoted p1 of the Dragon book in a NG). VHDL is different from the languages most programmers know about because it's concurrent, and because it knows about time. The resulting object code needs different runtime support from 'standard' languages to handle concurrency and time; this runtime support is the simulator. However, you (or any competent 'software' programmer) could write any general-purpose application in VHDL, and some people do. One thing you can do with VHDL is describe electronic systems, and a completely different compiler (the synthesiser) then carries out some very different processing on your code, producing a completely different output. Any competent programmer can write VHDL, but only a competent engineer could write a VHDL program that could successfully be turned into good hardware (today, anyway). Back on topic: There's so much 'free' software around because the people who use interesting software tend to be the people who have the inclination to, and are capable of, writing interesting software. But most of the people who use HDLs and back-end tools aren't programmers, and would have no interest in writing or contributing to these tools. So, we've got a very small user base to start with, and only a fraction of those people have the ability or the inclination to write the required tools - doesn't sound good... EvanArticle: 26285
eml writes: > There's so much 'free' software around because the people who use > interesting software tend to be the people who have the inclination > to, and are capable of, writing interesting software. But most of the > people who use HDLs and back-end tools aren't programmers, and would > have no interest in writing or contributing to these tools. So, we've > got a very small user base to start with, and only a fraction of those > people have the ability or the inclination to write the required tools > - doesn't sound good... Indeed. We have to bootstrap the process to get to the stage where people with common computing knowledge are able to use FPGA tools, and the time's not right for that yet. -- JamieArticle: 26286
I've just made a number of additions and other updates to my online
Embedded Systems Bibliography that may be of interest to this group:
http://www.netrino.com/Publications/Bibliography/
This is an online version of the Bibliography from my book "Programming
Embedded Systems in C and C++" (O'Reilly and Associates, 1999). But as
you'll see, quite a few new resources have appeared since I handed the
text off to the publisher just two years ago.
I would very much like to hear your constructive feedback. Are there
any other good resources (books, magazines, conferences, websites, or
newsgroups) that I've left out? If you have suggestions, please send
them to <mailto:webmaster@netrino.com>.
I have put a lot of work into writing the book and creating, hosting,
and maintaining this online resource. I believe that they are valuable
contributions to the community of embedded systems hardware and software
designers.
Sincerely,
Michael Barr
Article: 26287rickman <spamgoeshere4@yahoo.com> writes: > Neil Franklin wrote: > > > Oh, by the way, Xilinx has announced that they are releasing a set of > > > free tools later this month... > > > > Free as in free beer [1] or as on free talk [2]? > > > > [1] no financial cost to get it > > [2] sorce available to dissect and compile > > What exactly do you do with FPGAs? Emulate historical CPUs. PDPs for the beginning. > Are you currently using any of the > low cost tools available? As said: complete newbie to FPGAs, still trying to comprehend the field from not very friendly vendor web sites. A nice "Howto" in the Linux tradition would be really nice. Momental state of investigation seems to be: no Linux tools. > What background do you have with digital hardware? EE BSc degree 11 years ago. TTL/74(LS)xx and 8051 level stuff with wire wrapping. Since then worked in software and sysadmin, so a bit rusted. > Xilinx > may read this newsgroup, but I don't think these types of posts make > much of a dent. What I fear to be the case. They are after all tech, and managment seems to ignore tech in every firm I know. > toolset under Linux and we still don't have that yet. People even run > the tools using WINE, but still no formal support from Xilinx. I suppose I will have to do that then. Or get the tools for Sun (if they are also in the free (beer) license). In what size are, say, 20x20 to 32x32 CLB parts netlists and bitstreams as files (my Sun access is over modem and metered telephone line). rickman <spamgoeshere4@yahoo.com> wrote in <39E0F8B0.651932C1@yahoo.com> > > Neil Franklin wrote: > > > > > rickman <spamgoeshere4@yahoo.com> writes: > > > > > intermediate format is EDIF > > > > What is that? I have not seen that mentioned yet. > > EDIF is a standard file format for describing chip/board designs. The > format is limited to components and interconnects, to the best of my > knowledge. > vendors. In a nutshell, you have two main parts, the front end and the > back end. The front end is used to capture a design either in schematic > form or in an HDL. A tool is used to generate FFs and gates in the > intermediate format, either a vendor specific format such as XNF > (Xilinx) or EDIF. > > The back end tools accept the gate level design and figure out how to > put that into the vendor's FPGA. This is by definition, vendor specific. So generating EDIF or XNF ASCII files by some means and then compiling them to bitstreams on a Sun or WINE is all the tools I need? > BTW, a tool like this will probably be used for many different chips > including CPLDs. I beleive many of those have published formats for the > programming data. Unfortunately they have too few FFs for emulating CPU register sets (exeption seems to be Alteras MAX9000, but is that info available?). > > > So where are all the open source VHDL compilers? > > > > Lack of people who know they can be made? Need to have the vendors > > back end, so why not just use their VHDL compiler? > > You tell me. Why do you want open source tools? So I can run them on this box here, which implies being able to compile them, as the vendors don't seem to be offering them for it. That is why I asked about if it was free beer or speach. I need the second for this. > Are you saying that an > open source compiler is no good without an open souce back end? If you have no back end, the front end is no use. IIf I have change my setup (install WINE, use remote Sun) to use a vendors back end, I can just as good use their front end, so why then spend time making an own front end. At least that was my thought 2 days ago. Of course avoiding front end cost may make such a development still worth it. > > > If GPL'd tools are so good, why aren't there more of them in the FPGA > > > world? > > > > Lack of the info needed to make the stuff? > > We are going in circles now. All the info you need to make an open > source compiler is in the VHDL LRM. That I now understand, thanks to our post. > That is the place to start > regardless of the status of the back end tools. OK, if doing front end only development. > An open source back end > is of no value with out the front end. The vendor's back end tools are > free (beer) or nearly so. The front end tools can be very expensive at > $5,000 and up! That's a lot of beer!!! Actually after getting the point that the front ends are just VHDL or Verilog ASCII to EDIT of XNL ASCII, I may just look into what direct working with EDIF or XNL is like, or generating them by some own means. And then just compiling the bitstreams with vendor tools. Do I get this right tht VHDL : EDIF = C : Assembler, sort of? Thanks for the info. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26288
You are very funny for an engineer. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:39E05005.907CE39C@algor.co.uk... > > > Bob Perlman wrote: > > > Hi - > > > > I just have to know--what is Long Island Verilog? Is it to Verilog > > what Long Island iced tea is to iced tea, i.e., vaguely similar in > > appearance but more intoxicating? Is there a reference manual ? > > Reference manual becomes progressively more blurred as the code is > written. >Article: 26289
Oops, I caused a bit of confusion here. Kent Orthner <korthner@hotmail.nospam.com> writes: > krw@attglobal.net (Keith R. Williams) writes: > > > Andy Peters <"apeters <"@> n o a o [.] e d u> writes: > > > > Stop right there. You're thinking that a software person can design > > > > hardware? Sorry. Just because VHDL is a "programming language," it > > > > doesn't mean that a person who writes VHDL is a good hardware designer. I suppose I forgot to mention, that I am an (ex-) hardware person. I do have a few 74(LS)xx and 8051 style designs behind me. I am only new to FPGAs, not to hardware. > > On Tue, 10 Oct 2000 00:49:34, Kent Orthner > > > If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware > > > Description Language". the purpose of VHDL is not to program anything; you're > > > not telling some CPU what to do, you're describing a hardware construct. And programming is? Telling the hardware what to do. CLB1 take from ... > > Well, it is a programming language. The intention is certainly > > to abstract hardware, but it is a programming language. And like any other programming language uses textual symbols to describe which operations a piece of programmable hardware should do. And then a compiler makes bits from it that are fed to the hardware. I suppose that P in F>P<GA and C>P<LD does stand for programmable :-). > > interesting thing about VHDL and Verilog (remember I'm a relative > > newbie here) is the concurrancy. Things one learns in Normal hardware feature. Can also be found (and screwed up) in 74(LS)xx. > I absolutely agree with you (And Andy). "Programming" and "FPGA/ASIC/Hardware > design" are completely different. One consists of a series of steps for a > CPU (A program!), and the other describes how hardware should work. And both consist of taking a task, decomposing it into structural elements of the target systen (instructions for CPUs, connects for FPGAs) and expressing them in code, the (source) program. The elements may be different, but the process is the same, once one knows the elements behaviour and gotchas. And that electronics is parallel is well known. As for specific FPGA models gotchas, they have to be learned like specific CPU models ones. > > Also, you forget the fact that Engineers have things like timings > > to meet, and the I/O is not a monitor. > > <laughing> I only wish I could forget that. It would make my life > a *lot* easier if I didn't have to worry about timing constraints! Timing problems also exist on 74(LS)xx. And a 8051 often doesn't have a monitor either, particularly if you are the one writing the 7-seg LED driver and keypad scanner. And like anything else: begin small, 1 clock, all FFs clocked from it, slow enough so all inputs are ready. For 1-10MHz designs that should not be too difficult. The vendors are talking of 100MHz, so with factor 10 distance from that life should not be too difficult. > > Hmm, VHDL doesn't seem to me to have any of the above atributes. > > Sure, you can code hardware in VHDL as if it's a schematic (i.e. > > a markup language), but trust me. you soon learn that isn't the > > way to go. Could you expand on this? What is the problem? What the better method? > > > > > Anyone who can learn C can learn VHDL. > > > > > > > > ARRRGH! > > > > > <shrug> You're probably right there. But anybody that can learn C can > > > learn electronics, too. And spanish. No need to learn, already done that (electronics, not spanish) 15 years ago. > > > Yup. FPGAs are *just like* CPU's. 'cept they're not 'central' and they > > > don't 'process'. They *are* units, though. In what respect are they not central (when sitting between some I/O and memory and emulating an historic CPU (which is what I am intending to design)). And they certainly process: logical signals (0 or 1) are taken (from I pins), combined (in LUTs), stored (in FFs) and output (to O pins). > > > Saying an FPGA is like a CPU > > > is the same as taking a whole pile of 74HCxx series chips in your left > > > hand and calling *it* a CPU. Or pieces of Lego! Until you *make* > > > something with it, it's still nothing. > > Oops. i forgot the <Sarcasm> </Sarcasm> delimiters. My bad. They weren't needed. Them 74HCxxs (you use newer chips than I) can become a CPU if wired right. Just that I have decided that I would like to try something new and programm up CLBs instead of wiring up TTLs. > > I think it's rather arrogant for a "C programmer" to think they > > understand hardware. For clarification: A intended that statement as bitstreams : VHDL/Verilog eqiv binary instructions : C programs It seems to have been misunderstood. Did make a few interesting to read posts though :-). > "C programmers" don't need to know about > > concurrancy, and if you did you would sh!t. ...and that's only > > the start of your problems. > > I'm not a C programmer. Once again, I think this rant was aimed > at someone else! At me. But it missed, in multiple respects. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26290
Kent Orthner <korthner@hotmail.nospam.com> writes: > If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware > Description Language". the purpose of VHDL is not to program anything; you're > not telling some CPU what to do, you're describing a hardware construct. Well, I write some Verilog thingy, I run it through a compiler, it generates some object code on my machine and I can execute it. If I want, I can write some C and some Verilog and link them together. As much a programming language as any. Postscript is intended to be used for describing printable pages but it is a programming language all right. > Yup. FPGAs are *just like* CPU's. 'cept they're not 'central' and they > don't 'process'. They *are* units, though. Saying an FPGA is like a CPU > is the same as taking a whole pile of 74HCxx series chips in your left > hand and calling *it* a CPU. Or pieces of Lego! Until you *make* > something with it, it's still nothing. Let's have 65 thousand identical logic blocks, with some storage capability in each. They have several inputs and several outputs. Each of them can be configured as in how to derive the output from the input. Sprinkle them with an interconnect structure, actually a dynamically changable one. Then let's call it the Thinking Machine, a measly toy for those software types who can't comprehend temporally parallel operation of FPGAs. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 26291
> Rich, > > Two things: > > 1) They don't get much info from cookies. Go through the anonymizer and > they won't get your IP address. > > 2) Give false info when you fill out the form. It's not YOUR problem > that their database gets degraded! And maybe they'll learn a lesson, or > three. OK, I am computer illiterate. Where would I find an anonymizer and how do I get one? I note that while I'm typing here, my computer is underattack. I am safe, I think, thanks to the firewall I put up. Giving out false information is a pain in the butt, too. I don't mind if a form pops up but there shouldn't be mandatory fields. It's a pain. It's a pain! IT'S A PAIN! YOU VENDORS HEAR THIS? TELL YOUR SALESCRITTERS TO LEAVE US ALONE. ESPECIALLY WHEN THEY DON'T EVEN READ THE DATA SHEET!!!! I DON'T NEED TO BE QUIZZED ON WHAT PROJECT I AM WORKING ON, WHEN I AM GOING TO BUY PARTS, AND HOW MANY I AM GOING TO BUY. Now I shall eat dessert. :-) rkArticle: 26292
Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk> writes: > >> (Linux people would jump up and down for a GPL'd tool) > > > You can bet your life on that. > > Well would they pay anything? Get me a big enough wad of cash and I'll > personally put together a team of people and lead the project until it's > a good set of tools. Well, advertise your willingness on the 'net. I think you could find small companies willing to pay for such a tool. You couldn't get much money from any one of them, but if there are enough takers, you could have a reasonable amount in your disposal. I can also imagine that the Linux people who have to struggle with Windows to do HW design would chip in too. > >> There's a drwaback as well: free tools usually come with no > >> glossy docs and idiot proof GUI frontends with buttons to mail > >> to customer support. > > I disagree. > > I find the GCC manual very helpful. I.e. it does come with a glossy > doc. It doesn't teach C, but then you have lots of books for that if > you need one. > [ .. ] Well, I did not say "no docs", I said "no glossy docs". I like the docs of gcc et al. However, you have to create the docs yourself (last time I downloaded g<anything> I had to traverse into a docs directory type make postscript then print it and bind it myself), you don't get a shiny book, not even a colourful searchable PDF file (info is not for the faint harted). I don't mind (I'm most happy with a detailed man page) but a lot of people do. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 26293
Andy Peters wrote: > Phil Hays wrote: > > > 2) -Pro produces better results than the regular Synplify. > > Just curious: How so? Well, not by any of the advertised differences between the products. I did the direct comparison in quality of results quite a while ago. I currently have access to both regular Synplify at one place and with Amplify at another, and I should only use public sources between them. I tried the freeware HC11 core: http://www.gmvhdl.com/hc11core.html and ran into some unrelated issues. What I remember for the earlier comparison was that Synplify -Pro did a better job dealing with logic around IOB FFs, and the clock rate of the design was higher. I'm still going to try to get a recent comparison. -- Phil HaysArticle: 26294
I'm trying to implement modular exponentiation on an FPGA (specifically
targetting a Xilinx Virtex V300) as part of a hardware implementation of
a public-key encryption system. I'm trying to find an area efficient
implementation of modular exponentiation. I've come across several
algorithms which should help make my design more efficient, including the
square-and-multiply and Montgomery's multiplication algorithms.
While both methods seem fairly straight-forward, there are some parts
which aren't too clear to me. This may be because I lack a background in
modular arithmetic.
The thing that I need help with right now is the algorithm for Montgomery
reduction of an integer. The algorithm I've found is:
Given a prime M, and a radix R > M, m = bit-length of M
MRED(T), T < RM, R=2^m, gcd(M,R) = 1
U = TM' mod R
t = (T + UM) / R
IF t >= M RETURN t - M
ELSE RETURN t
t = TR' mod M
One of the conditions for the reduction is that:
RR' - MM' = 1
What I want to know is, where does M' and R' come from? (i.e. How do I
calculate M' and R'?) I've also noticed that some papers use R' while
others use the notation R^-1. Is there a difference?
I've tried looking at the Montgomery's paper, "Modular Multiplication
without Trial Division" as well as other papers on Montgomery
multiplication, but I haven't found anything particularly helpful.
Also, is the use of Montgomery multiplication and the square and multiply
algorithm the best (resource-wise) approach to use when attempting to
implement modular exponentiation in hardware?
If anyone could provide with some help on this, I would really appreciate
it. Seeing someone's VHDL implementation would be nice, but I really want
a good grasp of the fundamentals rather than just to copy code. If anyone
could recommend any good resources (books, websites, papers, etc) on this
stuff, that would be a great help.
If you could e-mail any responses to me that would be terrific. Thanks in
advance.
-Steve
su@wiliki.eng.hawaii.edu
Article: 26295Try the following paper. It has some implementation details too. http://www.computer.org/tc/tc2000/t0170abs.htm Muzaffer www.dspia.comArticle: 26296
On Tue, 10 Oct 2000 18:02:59 -0400, "Barry Schneider" <barrys@intrinsix.com> wrote: >You are very funny for an engineer. And you are exceedingly handsome for a headhunter. Bob Perlman >"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message >news:39E05005.907CE39C@algor.co.uk... >> >> >> Bob Perlman wrote: >> >> > Hi - >> > >> > I just have to know--what is Long Island Verilog? Is it to Verilog >> > what Long Island iced tea is to iced tea, i.e., vaguely similar in >> > appearance but more intoxicating? Is there a reference manual ? >> >> Reference manual becomes progressively more blurred as the code is >> written. >> >Article: 26297
Or get the people using FPGAs to the stage where they can find and use 'common computing knowledge', much more possible IMHO. After all, before microprocessors became common, hardware computation was the only way. Jamie Lokier wrote: > > eml writes: > > There's so much 'free' software around because the people who use > > interesting software tend to be the people who have the inclination > > to, and are capable of, writing interesting software. But most of the > > people who use HDLs and back-end tools aren't programmers, and would > > have no interest in writing or contributing to these tools. So, we've > > got a very small user base to start with, and only a fraction of those > > people have the ability or the inclination to write the required tools > > - doesn't sound good... > > Indeed. We have to bootstrap the process to get to the stage where > people with common computing knowledge are able to use FPGA tools, and > the time's not right for that yet. > > -- Jamie -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26298
Zoltan Kocsi wrote: > > Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk> writes: > > > >> (Linux people would jump up and down for a GPL'd tool) > > > > > You can bet your life on that. > > > > Well would they pay anything? Get me a big enough wad of cash and I'll > > personally put together a team of people and lead the project until it's > > a good set of tools. > > Well, advertise your willingness on the 'net. I think you could > find small companies willing to pay for such a tool. You couldn't > get much money from any one of them, but if there are enough > takers, you could have a reasonable amount in your disposal. > I can also imagine that the Linux people who have to > struggle with Windows to do HW design would chip in too. As long as you are writing software for FPGAs, you can really make a name for yourself and maybe a buck or million by developing a true set of tools to support the design and configuration of partially configurable chips. One of my applications uses four small chips because we need to load three of them depending on the hardware attached. Sort of a plug-n-play thing. If we could do the same thing within a single chip, it would save me a lot of board space and likely a few bucks on the chip(s). Many vendors support partial reconfiguration in the hardware, but no one that I am aware of supports it in the development software. It doesn't seem like a hard thing to do. It just isn't done. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26299
hi at all anyone use palasm???
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z