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I'm using TI's 5402, and for it the timing is a little tricky; it's quasi-synchronous. Okay, it's synchronous to its clock, but there is some variation (process,temperature) relative to the clock. For an old version of the data sheet, t-hold(D) for IOSTRBH was specified as +/- 3 ns. Put another way, DON'T USE IT AS A CLOCK FOR THE DATA! Same idea for using MSTRB, which I am using (though the timing relationships are different.) I use the clock from the DSP and sample the control signals, and determine my internal write time X clock periods in; that way I easily meet set-up requirements, and I can guarantee >0 ns hold. (I think X was 3-4, but the actual value detemined would be a trade-offs between speed requirements and device/system cost.) Jason T. Wright Cygnion Corp. On Wed, 12 Jul 2000 10:31:26 -0500, Matt Gavin <mtgavin@collins.rockwell.com> wrote: >Bob, > >thanks much for your comments. I will check the scope/probe I am using, >but I suspect it isn't close to 1GHz. > >In reference to your question about signals that condition the >toggle flop: The only inputs to the flop are its own output, and signals >which are synchronous to the clock (which I do have on a global buffer). >These signals all are setup early since I am using numerous wait states. >So there should be no metastability issues due to asynchronous inputs >toggling just when the clock rises. > >Actually, the clock is a "strobe" which asserts for a bus cycle to my FPGA >(IOSTRBF from the TI C54 DSP). >Its rising edge clocks in data, address and control signals which stay >asserted >for a clock cycle after the strobe rises. >These (address and control) are decoded to toggle the flop input >when a read is done to a specific address. > >FYI, I looked at the original gates in the Xilinx FPGA Editor (nice tool, >BTW) >and there are two muxes and a LUT in the feedback path that >seems to be failing. (so there is at least SOME delay there.) > >Thanks, > > Matt > > Jason T. Wright Cygnion CorpArticle: 23876
Has anyone written some simple code in VHDL to implement a UART (serial port) by bit pinging for the Virtex ?Article: 23877
Ottwald Holler wrote > I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to > realize some ideas with this fpgas. The only one problem is that the > current versions of xilinx software doesnt support the xc2018. > I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) > or XACT6 (Windows) to buy! > Anybody on the forum who could help me? > Thanks a lot for thinkig about! > Well, friends, thanks a lot for Your ideas I should use newer chips. But that wasn't the question. I'm still looking forward for an announcement from anyone who could sale me a working version of a development system that can program the identified IC's, too! I still accepted that present xilinx software system cannot hold it on duty, but maybe anyone vendor or freak may have an old version in his archive and he will sale me for a kind price! Please let me know Your help. Thank You Ottwald J.HollerArticle: 23878
We know that this is not the question. But it is very unlikely that you will get anyone to sell you their software. If they still have it, they will have been keeping it because they need to support an old design. If they don't need to keep it for this, then it is very unlikely that they will still have it around since this software has not been distributed for over two years! Can you explain why you want to work with these old chips rather than to get new ones? Ottwald Holler wrote: > > Ottwald Holler wrote > > > I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to > > realize some ideas with this fpgas. The only one problem is that the > > current versions of xilinx software doesnt support the xc2018. > > I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) > > or XACT6 (Windows) to buy! > > Anybody on the forum who could help me? > > Thanks a lot for thinkig about! > > > > Well, friends, thanks a lot for Your ideas I should use newer chips. But > that wasn't the question. I'm still looking forward for an announcement from > anyone who could sale me a working version of a development system that can > program the identified IC's, too! I still accepted that present xilinx > software system cannot hold it on duty, but maybe anyone vendor or freak may > have an old version in his archive and he will sale me for a kind price! > > Please let me know Your help. Thank You > Ottwald J.Holler -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23879
I will be ordering AVNET's Virtex Dev Board next week. I will be retargeting a design from four Altera Flex10K100's to the one XCV300. I will tell you how it works out when I get it. Fred Best ASIC/FPGA Design Lead MeshNetworks, Inc. ----------------------------------------------------------- Got questions? Get answers over the phone at Keen.com. Up to 100 minutes free! http://www.keen.comArticle: 23880
Greetings, I'm looking at FPGAs with Dual Port RAM for an instrumentation project. I want to continuosly record data from a Flash ADC and later read a subset of that data aftera trigger arrives. I need about 2500 bytes or 20,000 bits of dual port RAM, a write address counter, some small FIFOs, an adder to calculate the read address, and a small amount of other logic. More information on my application is available at: http://dustbunny.physics.indiana.edu/~paul/hallDrd/ It looks like my best bets are the Altera ACEX series (EP1K30) or the Xilinx Spartan II (XC2S30). I wonder if anyone out in usenet land has experience with either or both of these parts? Any advice or warnings? Likes or dislikes about the Altera or Xilinx tools? Compatibility with Mentor? Other considerations? Any other devices I should consider? TIA! Paul SmithArticle: 23881
Hi to all, We had a Ballynuey 2 Virtex(XCV800) PCI Card. We got the example vhdl source code and .bit file. The .bit files run well, but we can't compile the vhdl example code because it uses LogiBlox components, while Virtex doesn't support any components generated by LogiBlox. How did Nallatech generate the .bit file from these source codes? Ahmad.Article: 23882
Take the worst story you ever heard, then assume the reality is at least twice, may be up to five times as bad. I love this place, but the housing situation has gone past the insane level :-( Don Husby wrote: > This is way off topic. > > I'm thinking it's time to leave my cushy science job in Chicago > and move to the West Coast. The scariest aspect of this is the > nightmare stories I've heard about the difficulties of finding > a place to live in Silicon Valley and the Bay area. > Is it really that bad? > Are there areas that are better/worse than others? > Will I be spending hours per day in my car trying to get to work? > > -- > Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630-840-3668 > Batavia, IL 60510 Fax: 630-840-5406 -- // richard http://www.imagecraft.comArticle: 23883
Thanks in advance! Anyone know of a VHDL description for an i2c slave device (7 or 10 bit addressing)? Arthur RossArticle: 23884
In article <8kh517$lce@src-news.pa.dec.com>, murray@pa.dec.com (Hal Murray) wrote: > I'm happy with compressed files - it's the exe part that I don't like. > First, it won't run on my machine. Second, even if it did, I would > have to trust it. Why should I make that leap? It might contain a > virus > or trojan. Or it might just install some junk that I don't want on > my machine. Most unzip programs will work on self-extracting .exe files. Even on a PC you don't need to run the .exe if you don't want to. -- Steve Rencontre http://www.rsn-tech.demon.co.uk //#include <disclaimer.h>Article: 23885
Thanks. I'd already downloaded the software and viewed the examples. I just couldnt get them to work when I imported them into my design... Until I realised I had not correctly placed the carry-in to the ripple adder. It's working now! Stefan Ludwig (stefanludwig@my-deja.com) wrote: : In article <8k0p4h$g1b$1@seagoon.newcastle.edu.au>, : mwojko@hartley.newcastle.edu.au (Mathew Wojko) wrote: : > Has anyone successfully implemented carry ripple adders (using the : > fast carry logic) on the XC4000 series of devices? I know that you : have : > to be very specific with the code that you write - by specifying and : > mapping the carry functions and signals to specific parts of the CLB. : > At the moment, I just cannot get it work and have spent a fair : > amount of time on it. : Look at the intrperf sample in the Samples of the PamDC distribution : (which you can download from Compaq). : /pam/src/Samples/intrperf/design/src/Design.cxx : template<int N> class LdCounter : I'm not posting anything because the code is subject to the license : agreement. Go to : http://www.research.digital.com/SRC/pamette/Software.html : to download the PamDC software. : Stefan : Sent via Deja.com http://www.deja.com/ : Before you buy. -- Mathew Wojko PhD Candidate - Reconfigurable Computing and FPGAs University of Newcastle, University Drive, Callahan 2308 NSW Australia. Ph: +61 2 49216156 Fax: +61 2 49216993 WWW: http://murray.newcastle.edu.au/users/postgrads/mwojko/home.html Email: mwojko@ee.newcastle.edu.au ---------------------------------------------------- "Anyone can do any amount of work, provided it isn't the work he is supposed to be doing at the moment." - Robert BenchleyArticle: 23886
In article <8klbmj$fp6$1@flotsam.uits.indiana.edu>, paul@xanadu.physics.indiana.edu (Paul Smith) wrote: > Greetings, > > I'm looking at FPGAs with Dual Port RAM for an instrumentation project. I > want to continuosly record data from a Flash ADC and later read a subset of > that data aftera trigger arrives. I need about 2500 bytes or 20,000 bits of > dual port RAM, a write address counter, some small FIFOs, an adder to > calculate the read address, and a small amount of other logic. > > More information on my application is available at: > > http://dustbunny.physics.indiana.edu/~paul/hallDrd/ > > It looks like my best bets are the Altera ACEX series (EP1K30) or the Xilinx > Spartan II (XC2S30). > > I wonder if anyone out in usenet land has experience with either or both of > these parts? Any advice or warnings? Likes or dislikes about the Altera or > Xilinx tools? Compatibility with Mentor? Other considerations? Any other > devices I should consider? > > TIA! > > Paul Smith > > I think it would be easier to look after a Cypress or ITD DualPort RAM, and keep this part extarnally. -- KLARO Expect the worst, only then will you be favourably surpriced Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23887
Check out Xilinx app note 333 at: http://www.xilinx.com/xapp/xapp333.pdf They have free VHDL code available for that app note. Tobias Arthur F. Ross <Fognozzle@worldnet.att.net> schrieb in im Newsbeitrag: rStb5.2019$tI4.108026@bgtnsc05-news.ops.worldnet.att.net... > Thanks in advance! > > Anyone know of a VHDL description for an i2c slave device (7 or 10 bit > addressing)? > > Arthur Ross > >Article: 23888
Where to find examples IDE in VHDL.Article: 23889
hi, rickman wrote: > > Yes, I am with you. But this implies a lot of test vectors which should be > > verified. > > Can you explain how you would verify the test vectors? How do you > introduce your simulated faults and what type of faults do you simulate? To be honest, I have no concrete idea. I am a newcomer. I only have a rough idea what I want do. So I started this discussion to see what professionals do. -- Institut fuer Hochenegiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 23890
fred_best wrote:
> I will be ordering AVNET's Virtex Dev Board next
> week. I will be retargeting a design from four Altera
> Flex10K100's to the one XCV300.
> I will tell you how it works out when I get it.
Great! Do you use your own PCI interface? Our do you plan
to use the logiCORE PCI from Xilinx?
One Avnet salesman told me, that the board with the larger
XCV800 is also now available, with 20 boards on stock in the US.
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 23891In article <8k4add$knj$1@supernews.com>, "Mike H." <mikeh@spamless.imageproc.com> wrote: > > Nial Stewart <nials@sqf.hp.com> wrote in message news:3965A475.BC87B26A@sqf.hp.com... > > > > So they _are_ shipping it free? I was going to download it in > > work and blow a CD rom to take it home :-). > > > > What sort of limitations do these versions of the synthesis > > tools have? Are they just locked to Altera devices? > > Certainly the tools are locked to Altera parts only. > I can't comment about the limitations of the software, since > we normally use Synplicity rather than FPGA Express > or Leonardo and I'm not very familiar with the "full" version > of these tools. > > The software arrived via CDROM in the mail. Mine materialised a couple of weeks ago. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23892
I haven't used Spartan but I assume its the same as Virtex SelectMap. An abort is triggered when you change from a write to a read when the you haven't completed all the writing you told the the device would occur. Same when reading. You then have to resync and start again. Bill "rickman" <spamgoeshere4@yahoo.com> wrote in message news:396E1143.F8CB2AA9@yahoo.com... > 100 mS seems to be correct if you are using the serial programming > modes, but check out pages 17-20 in the SpartanII data sheet. The slave > parallel mode is much faster at 50 MHz CCLK with no waiting and 8 bits > being writen per CCLK edge! This will load your XC2S150 in as little as > 2.5 mS if your configuration logic can keep up. > > The only question I have in using this mode is whether the CS and WRITE > signals may be deasserted between CCLK edges. They make it clear that > you can cause a programming abort by not doing this properly, I don't > think they make it clear as to what the required procedure is. > > I copied this from the new, *unlocked* Spartan II datasheet! > > "For the present example, the user holds WRITE and CS > Low throughout the sequence of write operations. Note that > when CS is asserted on successive CCLKs, WRITE must > remain either asserted or de-asserted. Otherwise an abort > will be initiated, as in the next section." > > I assume that they are saying if you clock CCLK with CS asserted, you > had better not do a READ as opposed to a WRITE??? Or are they saying > that you have to keep CS and WRITE asserted at all times once you start > to program the chip? > > I had this exact same confusion with the way a similar mode in the > Lucent FPGAs was described. > > I am also not clear about the use of the term "packets" on pages 18-19. > > "When using the Slave Parallel Mode, write operations send > packets of byte-wide configuration data into the FPGA." > > In the abort section, they say you have to resync after an abort using a > "new synchronization word" before sending new packets. What does this > mean? What are packets? I don't plan to abort configuration loading, but > I would like to understand this. > > > > Gary Watson wrote: > > > > By my reckoning, a XC2S150 part from Xilinx has about a million bits of > > configuration data, and the Xilinx serial proms support a 10 MHz bit rate. > > Does that mean that it takes about 100ms to have valid outputs after power > > up? That would be OK for my application, but if it took much more than that > > I could run into some problems... > > > > -- > > > > Gary Watson > > gary@nexsan.sex (Change dot sex to dot com to reply!!!) > > Nexsan Technologies Ltd. > > Derby DE21 7BF ENGLAND > > http://www.nexsan.com > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23893
UNIVERSITY OF ABERDEEN CENTRE FOR ENVIRONMENTAL & INDUSTRIAL IMAGING This multi-disciplinary research centre represents expertise in such areas as computational image analysis, pattern recognition, holography and instrumentation. There is experience in a wide range of imaging modalities and application areas, and an extensive network of links with industry. The work is supported by state of the art computational and imaging equipment. RESEARCH STUDENTSHIP Applications are invited from UK/EU nationals for a three year PhD Studentship. The student will work on aspects of the representation of image information, with an emphasis on multiscale techniques and compression. The immediate application area will be in the imaging of deepsea marine life. Project supervision will be joint between the Departments of Engineering and Zoology. The techniques developed will have relevance to other environmental and industrial applications of interest to the Centre. The work will provide experience in computational imaging, compression techniques, and embedded systems engineering. The funding of the studentship covers UK/EU tuition fees and a maintenance grant equivalent to standard Research Council rates (UKP 6800 for 2000-01). Applicants should have a good first degree (equivalent of UK 1st class or upper second) in computational, physical, engineering or mathematical science. Informal enquiries may be directed to Dr Alastair Allen, telephone: +44 1224 272501, fax: +44 1224 272497, e-mail: a.allen@abdn.ac.uk Application forms: Postgraduate Office, Department of Engineering, Fraser Noble Building, University of Aberdeen, Aberdeen, AB24 3UE, UK. Tel: +44 1224 272513. Fax: +44 1224 273895. Email: pgoffice@eng.abdn.ac.ukArticle: 23894
I have some questions in my work. The first question is FFT core in TMS mode can not work continuous,after starting the core, the result is right at the odd frame and is wrong at the even frame.
The second question is when I use the timing constraint I find the period of "MWR" is very long,so I can not improve the performance.How can I get faster clk frequency.
I hope somebody can help me.
Article: 23895
Hi,
I am new to FPGA's and want to learn how to use them. This includes
designing, simulation and implementation. Can anyone tell me of a good
introduction/tutorial on the topic, (on-line if possible).
Cheers,
Nick
Article: 23896This is a multi-part message in MIME format. --------------11471270F1117DEA5F47F1FB Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > I am new to FPGA's and want to learn how to use them. This includes > designing, simulation and implementation. Can anyone tell me of a good > introduction/tutorial on the topic, (on-line if possible). For general-purpose introductory material to FPGAs, your first stop should be http://www.optimagic.com. The site has lots of pointers to online material, software, and a list of board manufacturers. You can get a complete XILINX FPGA development package from XESS that includes a tutorial textbook, development software, and an FPGA development board for $209. You can find more info at http://www.xess.com/prod009.html. You can get an Atmel FPGA development package from Kanda that includes the Atmel development software and an FPGA development board for around $156. They will sell you a tutorial book for another $34. You can find more info at http://www.kanda.com. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || --------------11471270F1117DEA5F47F1FB Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;Dave tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;-16464 fn:Dave Vanden Bout end:vcard --------------11471270F1117DEA5F47F1FB--Article: 23897
Hi all, i use synopsys Behavioral Compiler and FPGA Compiler and have just changed the synopsys version from 1999.10 to 2000.05/06. The problem is that the Virtex BlockRam is not connencted correctly to control-logic any more. For example the clock (of the blockRam): After BehavioralCompiler-Schedule anything is still well connected, but in the post-compile schematic the clock of the blockRam is now gated, what is definitely wrong. (in 1999.10 it has been directly connected to global clock-net) For example EN and WE: Those ports are also driven in a very strange way. It seems that they are connected to the highest bit of an address-counter. The strange thing about it is I have changed nothing in the sources in spite of the version numbers. Any Ideas? Thanks MarkArticle: 23898
This is a periodic posting to let readers of these newsgroups know
about several online resources that may be relevant:
[1] Embedded Systems Glossary
http://www.netrino.com/Publications/Glossary/
[2] Embedded Systems Bibliography
http://www.netrino.com/Publications/Bibliography/
These are online versions of the Glossary and Bibliography from my
book, "Programming Embedded Systems in C and C++" (O'Reilly and
Associates, ISBN 1-56592-354-5).
It is my intention to make occasional changes and updates to these
online versions. I would very much like to hear your constructive
feedback. Please send your suggestions to <webmaster@netrino.com>.
I have put a lot of work into writing the book and creating and
maintaining these online resources. I hope that they will be a
valuable contribution to the community of embedded systems hard-
ware and software designers.
Sincerely,
Michael Barr
Article: 23899
hi,
I have a designed bus mastering for our board which runs at a speed
of 60Mhz.
Now I have no idea of how to increase my speed. I would like to know what
does timing analysis mean in a design and how could we increase it.
I have some idea on timespec when you define a particular delay between
two signals to be some value and the mapping algorithm tries to place it
in sych way that I get this timing.
Is there any other way that I could increase my speed.
Thanks
Sreedhar
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