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Hi, Is there someone in germany which has already the new Foundation 3.1i ? Maybe some of you know when Xilinx starts the delivery. Thank You, MichaelArticle: 24001
Your problem is going to be that the jedec format does not preserve any of the structure of the design. You just get lots of logic. One way is to dis-assemble the jedec using a tool such as that provided as part of MACHXL (ex vantis). I have no idea whether their present tool will still do it. You would then have to just change the syntax and add PROCESS's to infer the d types etc. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24002
Hi, Well, perhaps late September: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html Laurel, Maryland Have fun, Richard B. Katz National Aeronautics and Space Administration ================================================= EKC wrote: > > Does anyone know whether or not there are any PLD-related conferences > scheduled to take place in the US before mid-September? If so, which ones? > > Thanks, > > EKCArticle: 24003
Hello. I´m supposed to build an IRIG-B decoder and PPS generator using some Altera device. I think that´s not a huge problem, but I would appreciate some help. I´ll write the code in AHDL (I don´t know VHDL or else). The real problem is: I need to use this code (IRIG) to adjust an oscillator, that is, keep accurate time despite the oscillator´s imprecisions. This accurate time will be used to generate start of conversion pulses to ADCs, and all ADCs must convert at the same time. The pulse will be transmitted via RS485 bus. Any suggestions? Thank you. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24004
"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote: > I would recommend Tucson, but then again, I'm from New Jersey. And the > typical silicon valley shack cost three times what I paid for a 2000 sq ft > home with cactus. I neglected to mention that my choice is strongly influenced by my addiction to windsurfing. An ideal place has strong, predictable wind, good waves, and a warm climate. The Bay area is pretty good, as is Portland, Oregon and Maui. Tuscon, New England, and Zimbabwe are right out. (I know I'll get some arguments from New England windsurfers, but their conditions aren't really any better than Chicago's. I'd consider the N.C. Outer Banks if there was any high tech industry there.) -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 24005
it will reach europe by the end of August, so go for holidays.... In article <3976AB04.B0A9558A@iis.fhg.de>, Michael Schmid <mlschmid@iis.fhg.de> wrote: > > > Hi, > > Is there someone in germany which has > already the new Foundation 3.1i ? Maybe > some of you know when Xilinx starts the > delivery. > > Thank You, > > Michael > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24006
Robert Carney <bobcarney@worldnet.att.net> wrote:
> Just read your DAC report, John, and it was great. The
> amount of detail and the "unabridged" nature of the opinions
> expressed made it the best DAC report I've ever read.
> Now I'm concerned that you might get sucked into a chief
> editor's job at one of the industry mags. Keep up the good
> work.
Thanks, Robert, for the thanks. It was a hell of a lot of work
to put that beastie together. And thanks for noticing the
unabridged style. I chose that because I'm the type who usually
hates summary overviews with no detail backing it up. (I guess
that trait comes from designing chips -- you always find yourself
digging deep into the details as part of the design process.)
I haven't thought of being an editor. Actually I've been thinking
more about what next type of project to get involved in. I'm
based in Boston and am juggling if I should: 1) do more of my
usual synthesis/Verilog/VHDL/test consulting, or 2) take the
time to learn backend tools (Synopsys PhysOpt / Avanti / Cadence )
more, or 3) learn the higher level verification software ( Vera,
Specman, Chronology).
I'm sort of at a consulting career crossroads now...
- John Cooley
the ESNUG guy
P.S. Yesterday Goering posted a summary of that DAC'00 Trip Report
at http://www.eetimes.com/story/design/OEG20000718S0048 (for
those who do like summaries.)
============================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 11,000+ other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
Article: 24007Hi John, It is an interesting write up. It gives a second chance for those who missed the DAC(like me!). Actually it is much more than a report(setting it apart from the conventional canned types), the (real)users opinion(s) are really invaluable, especially for the prospective CAD/CAE groups looking forward to adding more steam into their existing arsenal of CAD tools to meet/exceed the demands of an increasingly large/complex designs(resulting out of SOC trend) in an aggressively competitive market. The unbiased report really helps, to evaluate the truthfulness in Vendors claims. /* GOOD WORK, GREAT JOB, WELL DONE. */ -Raman John Cooley wrote: > I just wanted to give ya'll a heads up that the massive 104 page DAC'00 Trip > Report is up on http://www.DeepChip.com for viewing. It's a collective > report based on 113 survey responses and/or individual DAC trip reports (it > consists of quotes from those 113 engineers.) Enjoy. > > - John Cooley > > ----------------------------------------------------------------------------- > __)) "Glass ceilings? Name ANY ex-goat farmer who's made management!" > /_ oo > (_ \ Holliston Poor Farm - John Cooley > %// \" Holliston, MA 01746-6222 part time Sheep & ex-Goat Farmer > %%% $ jcooley@world.std.com full time contract ASIC & FPGA DesignerArticle: 24008
It's important to wire the TDI & TDO pins together on the PCI connector at least, but thats all I do with them. (I don't think these do anything useful in a pc anyway) No problem connecting the Spartan2 jtag pins to anything else on the board you want - we use a download/test connector that loops around all the jtag chips on the card. MikeJ@freeuk<REMOVE>.com Muzaffer Kal <muzaffer@kal.st> wrote in message news:f181ns0o0vbed5br8p4sgtoin4ssps2q1s@4ax.com... > hi, > how should one connect JTAG pins on a spartan II which is connected to > PCI ? If one chains spartanII to PCI TDI/TDO, can it be programmed > using the jtag header ? (I think the answer to this is no). Also are > there any problems with chaining a spartanII part to other jtag chips > on the same pci board ? > I'd appreciate any suggestions on how to connect jtag pins on a pci > board with spartanII and other jtag chips. > > thanks >Article: 24009
The 2.1i Xilinx Student Edition will be available for the start of the Fall semester You should be able to order it from www.amazon.com or www.xess.com by mid August. Pratip Mukherjee wrote: > Does any body know when will the new version of Xilinx Student Edition with > Foundation 2.x be out? Since coming to know that there will be a new version > shortly, I am holding on from buying the new version for about two months now. > The wait is killing me. > > Pratip Mukherjee -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 24010
erika_uk@my-deja.com wrote: > > it will reach europe by the end of August, so go for holidays.... > > In article <3976AB04.B0A9558A@iis.fhg.de>, > Michael Schmid <mlschmid@iis.fhg.de> wrote: > > > > > > Hi, > > > > Is there someone in germany which has > > already the new Foundation 3.1i ? Maybe > > some of you know when Xilinx starts the > > delivery. > > > > Thank You, > > > > Michael > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. Thank You.Article: 24011
>Is there someone in germany which has >already the new Foundation 3.1i ? Maybe >some of you know when Xilinx starts the >delivery. Last I heard, Foundation will ship in the UK at the end of July, and I guess Germany will be the same. If you're desperate, your disti will have a copy, and you may be able to borrow it if you ask nicely. EvanArticle: 24012
Nallatech have developed various designs on the Virtex from its launch, however, Coregen didn't have full support for distributed memory cores from the start for Virtex, only support for BlockRAM. Xilinx recommended that if SelectRAM was required Logiblox could be used targetting a 4000 series device and remembering to disable RPMs. However, Coregen now supports distributed memory (SelectRAM)for Virtex and so if you want you can substitute Logiblox components with your own Coregen component. If you need any assistance contact the support line at support@nallatech.com and they'll be able to help you out Thanks, Paul Dunn Design Engineer Nallatech Ltd. > -----Original Message----- > From: news@boss.cs.ohiou.edu (News Admin) > [mailto:news@boss.cs.ohiou.edu]On Behalf Of A. Alsolaim > Posted At: 13 July 2000 23:41 > Posted To: fpga > Conversation: HELP!! Nallatech Virtex Board. > Subject: HELP!! Nallatech Virtex Board. > > > Hi to all, > > We had a Ballynuey 2 Virtex(XCV800) PCI Card. We got the > example vhdl source code and .bit file. The .bit files run > well, but we can't compile the vhdl example code because it > uses LogiBlox components, while Virtex doesn't support any > components generated by LogiBlox. > > How did Nallatech generate the .bit file from these source > codes? > > Ahmad. > >Article: 24013
After slagging Altera off for false promises about the downloadable versions of the synthesis tools I should be fair and point out that they seem to be available now. Nial.Article: 24014
I am doing a real time sim with the back annotated Verilog and SDF file. I have a flag which crosses clock domains which at some point changes within the setup time of a flop in the other domain. This is not really a concern because it is treated with a metstability flop- but unfortunately it sets all the internal signals to X- this of course screws up the state machine on the other side- and the sim is hosed. Is there a way to keep the value valid when this happens? Can you back annotate is as such or is there a switch in NC-Verilog? Thanks, Mike ScottArticle: 24015
A bit off topic for here Iknow, but maybe someone has seen this before... We are having some very odd problems with AMD85C30 serial comms controler chip. Basically, using the thing as a 1200 baud UART receiver (with IEC870 protocol) the device seems to lock up with half a character in the receive buffer. The trigger seems to be a burst of pulses as the receive modem comes out of receive. The pulses can look like a valid null byte or a break, depending on width (8-10ms), followed by one or more short pulses (may or may not be less than a bit in width). When the 0x68 byte that signals start of an IEC frame comes along (maybe tens of milliseconds later) the UART seems to be stuck with half a byte up the chute. The byte is received as something like 0xA0 with framing/parity errors. The rest of the packet is received fine. Has anyone come across anything like this with this device? If possible please reply to danielm@microsol.ie as I am writing this from home. Thanks in advance for all suggestions. This one is breaking our b*lls. Daniel McBreartyArticle: 24016
Hi, Hello! We have an interesting problem, 17 clocks that are not synchronized. We are going to prototype an 8 port Ethernet (10 Mbit) switch in a Virtex 1000. There's one tx-clock and one rx-clock for each interface and there is a global clock which we will set to 10Mhz. The tx are rx clocks are 2.5 MHz. The reason why the global clock will only be at 10 MHz is simply because we want to make the design more challenging, since a low clock rate makes the queing and buffering handling more difficult. I should say that I work at a university, so we are allowed to make things more difficult than they really are ;) Anyway our first problem is to synch the data from the 8 ports to the global clock. Since we have 17 clocks we are out of global clock routing. My first idea would be to have 16 16-bit deep asynch fifos implemented in CLBs. Each port would have one rx fifo and one tx fifo and the fifos should be placed as close to the port as possible. The fifo would be based on Peter Alfkes appnote (XAPP051 I believe). However the problem here, as I see it, is to make sure that the skew between the port data rx and tx clocks are minimal. Any comments about the suggested solution? Some other approach that migth be better? I have never worked with a Virtex device before. Previous work has been with the XC4000 and these have different clock distributing resources compared the Virtex series. Jonas Thor NoSpamthor@sm.luth.seNoSpam - remove the obvious when replying Lulea University of Technology SwedenArticle: 24017
Do you really need the 17 clocks - cannot all 8 tx-clocks be the same? Andy Jonas Thor wrote: > > Hi, > > Hello! > > We have an interesting problem, 17 clocks that are not synchronized. > We are going to prototype an 8 port Ethernet (10 Mbit) switch in a > Virtex 1000. There's one tx-clock and one rx-clock for each interface > and there is a global clock which we will set to 10Mhz. The tx are rx > clocks are 2.5 MHz. The reason why the global clock will only be at 10 > MHz is simply because we want to make the design more challenging, > since a low clock rate makes the queing and buffering handling more > difficult. I should say that I work at a university, so we are allowed > to make things more difficult than they really are ;) > > Anyway our first problem is to synch the data from the 8 ports to the > global clock. Since we have 17 clocks we are out of global clock > routing. My first idea would be to have 16 16-bit deep asynch fifos > implemented in CLBs. Each port would have one rx fifo and one tx fifo > and the fifos should be placed as close to the port as possible. The > fifo would be based on Peter Alfkes appnote (XAPP051 I believe). > > However the problem here, as I see it, is to make sure that the skew > between the port data rx and tx clocks are minimal. > > Any comments about the suggested solution? Some other approach that > migth be better? I have never worked with a Virtex device before. > Previous work has been with the XC4000 and these have different clock > distributing resources compared the Virtex series. > > Jonas Thor > NoSpamthor@sm.luth.seNoSpam - remove the obvious when replying > Lulea University of Technology > SwedenArticle: 24018
Hi there! I am looking for an open (free) MP3 decoder source file, if something like this is avaiable. The company Snom, in Germany in the area of Intelectual Property, offers a file that is a compete MP3 processor, but it plays for only about one minute. For those intersted in it, take a look at http://www.snom.de/ap1002.html. Does anyone have the sourde for the decoder in vhdl? I would appreciate it a lot. Mail to longaray@conex.com.br Yours, MárcioArticle: 24019
*******To anyone is involved in VLSI digital designs******* This is to announce a new family of adders that involve a new bit block structure that computes propagate signals called "carry strength" in a ripple fashion. A 32-bit carry-skip adder designed using the new method and realized using 0.6um CMOS technology shows a performance gain of more than 30% with respect to a conventional carry-skip adder, and reaches a performance comparable with that of a traditional block-CLA saving more than 26% silicon area and more than 34% power. Results will be discussed at the SSGRR 2000 Conference in L'Aquila, Italy (http://www.ssgrr.it/en/conferenza/index.htm). The new approach has been also applied to spanning-tree adders (Lynch-Swartzlander 1991 and Kantabutra 1993). Results will be broadcast at the First Online Symposium for Electronics Engineers (www.techonline/OSEE) Please, anyone interested in these results may visit our Web sites or contact us. http://www.ing.unirc.it/didattica/elettr01/index.html http://www.isu.edu/~kantviti/ ********************************************** *Pasquale Corsonello Microelectronic and Microsystem *Laboratory *Department of Electronic Computer Science and System *University of Calabria *Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY *Tel:+39 984 494708 Fax:+39 984 494713 *email: pascor@deis.unical.it * http://www.ing.unirc.it/didattica/elettr01/index.html ********************************************** Vitit Kantabutra, Ph.D. Associate Professor of Computer Science College of Engineering Idaho State University Pocatello, Idaho 83209-8060 U.S.A.Article: 24020
Hi, all, Does anyone know if the BlockRAMs in Xilinx Spartan II/Virtex/Virtex-E series have their dedicate routing resources, or their share the routing resources with other CLBs ? Any help will be appreciated. Channing Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24021
Hi, all, Does anyone know if the BlockRAMs in Xilinx Spartan II/Virtex/Virtex-E series have their dedicate routing resources, or their share the routing resources with other CLBs ? Any help will be appreciated. Channing Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24022
Hello! I've got myself in a bit of a quandry here, and would like some advice. I'm using a Virtex 150, using two clocks. Each clock is coming in on a clock pin, so there's no problem there. Due to a severe shortage of pins, I have used the other two clock pins as regular I/O ( I was willing to pay the slight timing penalty of having them routed onto a clock net and then off again.) Now, I would like to use one of the DLL Outputs other than the 0 degrees output (The 180 degress output, to be precise). As I see it, I'm not going to be able to implement this, because there's only 4 clock buffers, and I need 5: Buffer #1, #2: Wasted on regular input pins. Buffer #3: Used for first clock (Feedback and clock signal at 0 degrees) Buffer #4: Used for 2nd Clock feedback. Buffer #5: Used for 2nd clock signal at 180 degrees. Can anyone think of a way to still use those dedicated pins without "consuming" a global clock net? Or, a way to provide a feedback to the 2nd clock without consuming a global clock net? Any suggestions at all would be appreciated. Note: Since the PCB is already finished, it's difficult to change pin locations. Thanks! -Kent ------------ Kent Orthner korthner at hotmail dot comArticle: 24023
'fraid that I don't have any advice for you; only a further question: What exactly is a "Metastability Flip Flop"? I'm doing the same thing, with flags and such that cross clock domains, and am wondering if there's a better way I could be doing it. Thanks! -Kent <qwerty@scottfamily.cc> wrote in message news:S71e5.39806$DJ2.191608@typhoon.ne.mediaone.net... > I am doing a real time sim with the back annotated Verilog and SDF file. > I have a flag which crosses clock domains which at some point changes within > the setup time of a flop in the other domain. This is not really a concern > because it is treated with a metstability flop- but unfortunately it sets > all the internal signals to X- this of course screws up the state machine on the > other side- and the sim is hosed. > > Is there a way to keep the value valid when this happens? Can you back annotate > is as such or is there a switch in NC-Verilog? > > Thanks, > Mike Scott > -- ------------ Kent Orthner korthner at hotmail dot comArticle: 24024
It seems as though everyone has targetted the cost of buying a house in the Bay area. I've been considering moving there, and would be considerably more interested in a simple 2-bedroom apartment than a house. Are the prices for renatl apartments just as unreasonable? And would I expect the drive to be just as far? (2 hours just doesn't seem reasonable to me.) I figure there has to be some place that the non-high tech people live, right? Or are there in non-high tech people left? -Kent ------------ Kent Orthner korthner at hotmail dot com
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