Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I have to design a power supply for two Spartan-II (XC2S150). Does anyone know how is the power consumption for these Chips. I know it depends of a lot of things. Although a approximate value would be helpfull. @ 48MHz. Vccint @ 2.5V --> I= ? Vcco @ 3.3V --> I = ? thanks RobertArticle: 24126
Here is some more rope (:>) Take a look at the signals that are "optimized" away. Are they inputs? Are the connected to input pads? Its been a few years but I think I had this problem which turned out I had signals that were inputs but I didn't connect to input pads and buffers. Keep us posted. "K.Orthner" wrote: > As the subject says, I fell like I'm at the end of my rope, here. ( I get > the feeling I'm mixing metaphors, but I haven't actually had an english > conversatoin for so long, I forget.) > > This is (was?) related to the coregen thread, except that now, I have > completely removed everything Coregen-related. > > I have the simple problem of: > > My code simluates fine, I get exactly the answers that I expect. Then I put > it throught the Xilinx mapper, it "optimizes" out some signals that are > rather important. It then falls over saying that there are components who's > input signals have been optimized. > > If I select the "Don't trim logic"option it seems to work fine; but I > haven't tested it on a real board yet. (It's PnR'ing as I type.) > > Anyone have a suiggestion for how to track this problem down? > > I've been tracing nets with the EDIF file/FPGA Express Schematic viewer, and > as far as I can tell, the output of the synthesizer is just fine. > > ------------ > Kent OrthnerArticle: 24127
nullandvoid wrote: > > or you could try a function similar to the following: > > function shift_right ( > A : std_logic_vector; > num_shift : natural) return std_logic_vector is > begin > for i in num_shift downto 0 loop > A := '0' & A(A'left downto (A'right + 1)); > end loop; > return A; > end function shift_right; > This won't synthesise will it? Nial.Article: 24128
> I use the ieee.std_logic_signed > in order to perform synthesizable arithmetic functions using the > operators +,-,*,/ > but I do not know which representation do they use (sign magnitude, 1's > complement or so). The two's cpmplement representation is used > I want to use sign magnitude representation Therefore you should use unsigned arithmetic and you should write your own logic to generate sign. > What can I do if some of the operations in the same module are signed > and the others are not? I am trying to append '0' on the left of the > std_logic_vector signals and perform the operation. You may also use pre-defined IEEE.std_logic_arith block and use signed or unsigned insted of std_logic_vector signal declarationArticle: 24129
Renaud Pacalet wrote: > You're welcome. I learnt something today too: nobody seems able to > explain me why left and right are inverted in a mirror but not top > and bottom ;-) If you invert both top and bottom as well as left and right, you get back the original image. In reallity you can not distinguish which direction is inverted and which is not. The image is a mirror image, with top above, bottom below, left on your left and right on your right. So to say the left right direction is inverted is not correct. That is based on your frame of reference. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24130
On the Xilinx website, I know that there is a power estimator applet/spreadsheet for the virtex series. Since the Spartan-II architecture is the same as the Virtex (They're shipping Virtex 150's as "engineering model" Spartan-II 150's), it should be safe to use. That spreadsheet takes into consideration gate count, blockram usage, frequancy, i/o pins, and so on; it's pretty comprehensive. You can find it at http://www.xilinx.com/products/virtex/design.htm. -Kent ------------ Kent Orthner korthner at hotmail dot comArticle: 24131
In article <397FBBD0.8EBC4B28@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > I remember from years ago that Viewlogic has a licensing "quirk" (I used > much stronger language at the time). They had and still seem to have two > types of licenses. You can get a target specific license which will only > let the tools work with the libraries for a specific chip vendor's > devices. Or if you paid a much higher price you can get a full "board" > package that will work with any library including board design libs. > > The problem was if you paid the big bucks for the board package you > could not share any files with a customer who was using a vendor > specific version. This was not limited to files that were done for other > vendor's chips, but even for the libraries that their license was > authorize for. > > I investigated extensively and understand just how the licensing works. > I even found a way around the problem by cutting and pasting one line > from the schematic files. But this was a real pain and had to be done > each and every time the file was saved. > > The question is, has Viewlogic found a way to deal with this problem? I > am thinking about buying a full license for board level design. But > there is not much point if I can't share schematics with customers who > only have the chip level package. > The obvious response here is: What does Innoveda (Viewlogic) have to say about this? In any case, I use ViewDraw and ViewSim (latest versions) for FPGA entry and simulation, and I know that the file formats have not changed in many years. Since ViewDraw is also used for board schematic capture, I suspect that nothing has changed. Maybe you could write a BASIC program to post-process the schematic files and replace the line in question. We use OrCAD Capture for board level schematic capture, OrCAD Layout for PCB Layout, and Specctra for autorouting. We also bought OrCAD Express, but that was a nightmare. Since we use both OrCAD and Viewlogic tools, I have to say that OrCAD's entry tools are easier to use, and we are more productive when using them. Also, from a configuration management point of view, OrCAD board design files include all schematic sheets and all parts. You don't have to worry about synchronizing libraries with schematic files, and it makes it easy to deliver designs. OTOH, OrCAD back end tools (i.e. simulators, libraries, and routers) are not what you would call 'best in class'. We build our own parts for schematics. We bolt on Specctra for board routing. We don't use OrCAD at all for FPGA entry and simulation. With OrCAD, we were tring to use one EDA vendor for all of our design entry and simulation needs. This didn't work out. For the time being, we will stick with Viewlogic for FPGA schematic entry and simulation, and we will stick with OrCAD for board entry and layout. I would be interested to hear what other people think of ViewDraw versus other board-level schematic capture tools. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24132
The Spartan II architechture is the same as the Virtex, but isn't it a smaller geometry? Of course that would lower the power consumption numbers so that the value from the calculator will be an upper bound. "K.Orthner" wrote: > > On the Xilinx website, I know that there is a power estimator > applet/spreadsheet for the virtex series. Since the Spartan-II architecture > is the same as the Virtex (They're shipping Virtex 150's as "engineering > model" Spartan-II 150's), it should be safe to use. > > That spreadsheet takes into consideration gate count, blockram usage, > frequancy, i/o pins, and so on; it's pretty comprehensive. > > You can find it at http://www.xilinx.com/products/virtex/design.htm. > > -Kent > > ------------ > Kent Orthner > korthner at hotmail dot com -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24133
I want to know how to do an implementation on fpga in 8*8 block for a DCT !! Because i understand DCT algorithm and coeficients, but i can't continue because i don't understand how to implement in FPGA, all comment are welcome !! THXArticle: 24134
Nial Stewart <nials@sqf.hp.com> wrote:
>nullandvoid wrote:
>
>>
>> or you could try a function similar to the following:
>>
>> function shift_right (
>> A : std_logic_vector;
>> num_shift : natural) return std_logic_vector is
>> begin
>> for i in num_shift downto 0 loop
>> A := '0' & A(A'left downto (A'right + 1));
>> end loop;
>> return A;
>> end function shift_right;
>>
>
>
>
>This won't synthesise will it?
>
>Nial.
>
>
i'm not sure if it will synthesize (don't currently have synth
tools at my disposal) but i don't see why not. i've seen
functions containing loops used in synthesizable code several
times before. perhaps someone could test it and post the
results?
also, in my haste to post, i didn't check for syntax. the
function should read as follows:
function shift_right (
A : std_logic_vector;
num_shift : natural) return std_logic_vector is
variable B : bit_vector(A'range) := A; -- a copy of A
begin
if (i <= 0) then
report "ERROR";
return A;
end if;
for i in num_shift downto 0 loop
B := '0' & A(A'left downto (A'right + 1));
end loop;
return B;
end function shift_right;
FWIW,
NaV
-----------------------------------------------------------
Got questions? Get answers over the phone at Keen.com.
Up to 100 minutes free!
http://www.keen.com
Article: 24135Seb C a écrit : > > I want to know how to do an implementation on fpga in 8*8 block for a > DCT !! Because i understand DCT algorithm and coeficients, but i > can't continue because i don't understand how to implement in FPGA, > all comment are welcome !! Do you understand digital electronics? An FPGA is nothing more than a bunch of tiny logic elements that you can configure to perform some operations, with lots of wires you can configure to link them. No magic in here... -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24136
Hi, Experts, Does the CLKDLL in Virtex/Spartan II could be drived by a internal signal ? If so, how to implement this ? Thanks. Channing Wen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24137
In article <398049CC.C21F76AA@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > The Spartan II architechture is the same as the Virtex, but isn't it a > smaller geometry? Of course that would lower the power consumption > numbers so that the value from the calculator will be an upper bound. > If the supply voltages are the same then the geometries will be the same: 1.8V -> .18um 2.5V -> .22um 3.3V -> .35um 5V -> .5um -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24138
Because the F2.1i only support the subsets of VHDL. So I have to synthesis my VHDL core by using Leonardospectrum and got the *.edf. The target device is Virtex V800hq240. Then I want to implement this core in F2.1i. The steps are: 1. Create a new project 2. add the *.ucf and *.edf to this project (But at this time, the manual tools>implementations> are all unenable, so I can not use the 'Flow Engine'. 3. I have to click 'implementation' button, then I got the message 'can't create the chip' How can I do that by using the *.edf and *.ucf in F2.1i? Thanks a lot! Daixun -- Posted from IDENT:exim@prue.eim.surrey.ac.uk [131.227.76.5] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 24139
MK Yap wrote in message <397fb653$1@news.starhub.net.sg>...
>Hi all,
>
>I know both produce the same behaviour, but which is a good and preferred
>coding style? Which one is more power efficient?
>ByteReq is generated from other process, which is not straightforward.
That
>results in the preset value in ByteCntr driven by complicated logics in
>Example2 (not preferable right??)
>
>Any comments?? Thank you very much.
>
>
>Regards
>MKYap
>
>#Example 1
> delaycntr: PROCESS(nReset,Clk)
> BEGIN
> IF nReset='0' THEN
> DelayCntr<=0;
> ELSIF Clk'event AND Clk='0' THEN
> IF ByteReq='0' THEN
> DelayCntr<=0;
> ELSE
> DelayCntr <= DelayCntr + 1;
> END IF;
> END IF;
> END PROCESS delaycntr;
>
>#Example 2
> delaycntr: PROCESS(nReset,ByteReq, Clk)
> BEGIN
> IF nReset='0' OR ByteReq='0' THEN
> DelayCntr<=0;
> ELSIF Clk'event AND Clk='0' THEN
> DelayCntr <= DelayCntr + 1;
> END IF;
> END PROCESS delaycntr;
These processes won't generate the same logic. Example 1 has both a
synchronous reset and an async reset. Example 2 has two async resets.
Different behaviour. Of course, if ByteReq is generated by synchronous
logic, then it will "appear" to be a sync reset, but it's not.
In fact, an FPGA synthesis tool will probably choke on Example 2, because
the template for flip-flops has only the clock and the async reset in the
sensitivity list.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24140
rickman wrote in message <397F8AF0.A0F51633@yahoo.com>...
>Andy Peters wrote:
>> Another detail, of course, is the the synthesis vendors need to be able
to
>> support this tri-state register feature. I mean, FPGA Express is so
stupid
>> that it doesn't realize that the IOB tristate enables have a mux in front
of
>> 'em to select the polarity! Yup -- if you write code for an active-high
>> output enable, the goddamn tool inverts the OE in a CLB, and that
inverted
>> signal is what drives all of your output enables.
>
>I don't understand why the synthesis vendors need to deal with it. This
>should be a map, place and route issue which is done in the Xilinx
>tools. The synthesis tools only need to generate the FF and the MPR
>tools can put it where it will work best.
In this particular case, I guess the place-and-route tool should notice that
this particular CLB (with the inverter) drives the tristate enable of, oh,
32 output pins, and you'd think that it figure out that the CLB could be
eliminated. But, you'd also think that the synthesis tool should understand
the chip architecture better and not put the inverter in there in the first
place!
>> I mean, would you actually go out and PURCHASE a copy of MS Office, if it
>> wasn't pre-loaded onto your computer?
>
>Somebody must be buying it. Office does not come free!
OK, you DO pay for it, because your computer costs more than it really
should, but that cost is buried.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24141> Renaud Pacalet wrote: > > You're welcome. I learnt something today too: nobody seems able to > > explain me why left and right are inverted in a mirror but not top > > and bottom ;-) It's not a physics problem, but a liguistic one. If you're facing east (or west) looking in a mirror at a compass then the compass still points north-south. The mirror is a red herring. If you face somebody else who may or may not happen to look identical to you then your left hand will be next to their right hand. It is all to do with the position of "left" and "right" depending on the direction you are facing. Also, the date when the third millenium starts is a lingustic problem, not a religous one. Since ordinal numbers begin from "first" and A.D. means "in the year of the Lord", there is no such word (or concept) as "zeroth" so 1 A.D. is the next year after 0 B.C. Therefore the first millenium began in 1 A.D. By extrapolation, the second millenium began in 1001 AD and the third millenium will begin on 1 January 2001. Of course, the most important thing to remember is that its another excuse to have a big party. -- Andrew MacCormack email: andrewm@cadence.com -- Senior Design Engineer -- Cadence Design Systems, Alba Campus, Livingston EH54 7HH, Scotland -- Phone: +44 1506 595360 Fax: +44 1506 595959Article: 24142
rickman wrote in message <397F8AF0.A0F51633@yahoo.com>...
>Andy Peters wrote:
>>I mean, FPGA Express is so stupid
>> that it doesn't realize that the IOB tristate enables have a mux in front
of
>> 'em to select the polarity! Yup -- if you write code for an active-high
>> output enable, the goddamn tool inverts the OE in a CLB, and that
inverted
>> signal is what drives all of your output enables.
>
>I don't understand why the synthesis vendors need to deal with it. This
>should be a map, place and route issue which is done in the Xilinx
>tools. The synthesis tools only need to generate the FF and the MPR
>tools can put it where it will work best.
I just took a look at an older XC4KE design, which has an SRAM interface.
The XC4KE has a simple mux to select output enable polarity. The SRAM data
bus' output enable is written as active high, and the tools all did "the
right thing" -- no extra inverters.
weird.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24143I think this would tend to be correct, but Xilinx is redesigning the chips from the Virtex for lower cost. So I am pretty sure that they have reduced the feature size while keeping the voltage the same. The datasheet says the Virtex is .22 um. The Spartan II is .18 um according to an XCell article, xl35_5.pdf. Greg Neff wrote: > > In article <398049CC.C21F76AA@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > > The Spartan II architechture is the same as the Virtex, but isn't it a > > smaller geometry? Of course that would lower the power consumption > > numbers so that the value from the calculator will be an upper bound. > > > > If the supply voltages are the same then the geometries will be the > same: > > 1.8V -> .18um > 2.5V -> .22um > 3.3V -> .35um > 5V -> .5um > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24144
Andy Peters wrote: > >I don't understand why the synthesis vendors need to deal with it. This > >should be a map, place and route issue which is done in the Xilinx > >tools. The synthesis tools only need to generate the FF and the MPR > >tools can put it where it will work best. > > In this particular case, I guess the place-and-route tool should notice that > this particular CLB (with the inverter) drives the tristate enable of, oh, > 32 output pins, and you'd think that it figure out that the CLB could be > eliminated. But, you'd also think that the synthesis tool should understand > the chip architecture better and not put the inverter in there in the first > place! My understanding is that when it comes to inverters, the MPR tools are supposed to be smart. They have always been capable of moving inverters into any useful place, like the tristate control for example. But then I may be thinking of a different vendor, Lucent. I know they support a polarity selection on the tristate controls. I don't remember if Xilinx does or not. That is why I hate using many of the tools. They expect you to remember all the grody details of the parts in order to get maximum utility from them. > >> I mean, would you actually go out and PURCHASE a copy of MS Office, if it > >> wasn't pre-loaded onto your computer? > > > >Somebody must be buying it. Office does not come free! > > OK, you DO pay for it, because your computer costs more than it really > should, but that cost is buried. Many people actually do BUY it intentionally. It is not my first choice, but someone is buying it or Best Buy wouldn't keep it on their first row of shelves. The one way I would never buy it is with a computer. They can't make you buy software with the machine. Someone wrote about how they refused to agree to the license agreement for Windows that came up on their new laptop. The software said if you did not agree, return the product for a refund. After much argument from the vendor (some Japanese company like Toshiba maybe) they send him the $50 and he ran Linux. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24145
Vicente Marti <lavhek@teleline.es> escribió en el mensaje de noticias ... > Desearia poder conseguir informacion en castellano sobre la FPGA > XCS05XL de Xilinx > >Article: 24146
Vicente Marti <lavhek@teleline.es> escribió en el mensaje de noticias ... > Desearia poder conseguir informacion en castellano sobre la FPGA > XCS05XL de Xilinx > >Article: 24147
come si entra nel bios?Article: 24148
Well, the F5 mux is still a 2 input mux, sure you get it for "free", but that is beside my point. Consider the simple case of a 4 input rotator (a barrel shift with the inputs 'wrapped around'). If you implement it in 4 input muxes, you need 4 of them right. That is 4 slices or 4 CLBs depending on the xilinx architecture, fine. If you use 2 input muxes in a merged tree, the first layer uses 4, and the second layer uses 4, for a total area that is the same as that of the case using 4 input muxes, but without using the F5 muxes. The difficulty with using the F5 muxes is that you don't get to share the terms. rickman wrote: > Ray Andraka wrote: > > > > rickman wrote: > > > > > I can't say that I know what you mean when you say "an optimal merged > > > tree." Certainly you would want to connect the muxes in a tree, but what > > > further optimizations can you do unless you can restrict the range of > > > the select inputs? > > > > a merged tree eliminates the duplicate terms at each level. As a result each level > > is N 2 input muxes. Think of it this way: you do the aggregate shift as a series > > of incremental shifts by powers of 2. If you use 4 input muxes, then you need N 4 > > input muxes for each layer. That is equivalent logically to 3*N 2 input muxes. The > > 2 layers a 2x2 merged tree only uses 2*N 2input muxes. From that you can see both > > use the same area in the xilinx architecture, or in the case of Altera, the 4 input > > actually uses 1-1/2 times the area! > > I see how the sharing of muxes between bits minimized the number of LUTs > used, but I don't agree that the 4 input mux is equivalent to 3 2 input > muxes. By using the F5 mux in the Virtex and the Spartan II chips, you > get a four input mux from two LUTs which is the same as 2 two input > muxes with less delay. > > > > I would take exception to the statement "There's no savings using 4 > > > input muxes in this architecture". To implement a 4 input mux using 2 > > > input muxes in 4 input LUTs requires 3 LUTs. By using the F5 mux you can > > > save one LUT. Similarly (after looking at the data sheet) I see that > > > there is a F6 mux which will allow you to implement an 8 input mux using > > > just 4 LUTs vs. 7 LUTs by your method. > > > > > > Hmmmm... why do I feel like I am missing something important? > > > > Probably because you are! Normally, yes a 4 input mux is more compact in xilinx. > > The point in this case is for N inputs you need N outputs, and by merging the first > > layer you eliminate half of the logic in that first layer (by sharing the outputs). > > I still maintain that even with sharing of muxes you get a better design > with the 4 and 8 input muxes. I am also not too sure that the routing > congestion is not a problem. At the last level in a large barrel shifter > you have to route N/2 signals from mux i to i + N/2. This puts N/2 > signals through a single spot. If you are doing a circular shift, this > becomes N signals! > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24149
If you are concerned about power consumption in Virtices, remember that the Blockrams really burn the stuff. K.Orthner wrote in message <8lpfog$jc4@inf-gw.inf.furukawa.co.jp>... >On the Xilinx website, I know that there is a power estimator >applet/spreadsheet for the virtex series. Since the Spartan-II architecture >is the same as the Virtex (They're shipping Virtex 150's as "engineering >model" Spartan-II 150's), it should be safe to use. > >That spreadsheet takes into consideration gate count, blockram usage, >frequancy, i/o pins, and so on; it's pretty comprehensive. > >You can find it at http://www.xilinx.com/products/virtex/design.htm.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z