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Hi, I think you have used BUFGP for #1, #2. How about to use IBUFG for #1,#2 ? > Buffer #1, #2: Wasted on regular input pins. > Buffer #3: Used for first clock (Feedback and clock signal at 0 degrees) > Buffer #4: Used for 2nd Clock feedback. > Buffer #5: Used for 2nd clock signal at 180 degrees.Article: 24026
Tom Vrankar wrote: > > Does any JEDEC to VHDL converter exist to allow me to quickly migrate old > circuit card designs based on rafts of 22V10s in DIPs to a single large FPGA? > Either freeware or from a FPGA vendor? I've researched it enough to know I > could do it, but figured it was so obvious someone else must've already done > it, though I don't see it mentioned in any FAQs I've found. How many 22V10's ? There are two things you'll need : - The Equations for each 22V10, ideally source, or rev-eng there are various older pgms that do JED2EQN - The PCB netlist(s), for interconnect of the 22V10. If there are a lot of 22V10's ( dozens ), the PCB netlist may be more of a problem :-) Conversion to Altera AHDL, or ABEL might be easier, as they are closer to the equation formats that come out of the jed 'dis-assemblers'. As a 22V10 is closer to a CPLD block, ( typ 36V16) than a FPGA, you might also look at CPLD targets - it does depend on total register count, over 25-50 22V10's and you are more into FPGA territory. - jgArticle: 24027
Using Xilinx Foundation 2.1i . . . . . I believe that I've managed to create an Asynch FIFO using Xilinx CoreGen utility. I have the .VHO and .EDF files. I'm trying to figure out how to include the CoreGen Part in my simulation. I've read the bit about using get_models, and that seems ro run fine. I've also fiddled with the configuration until it compiles fine. but when it's all said and done, I get the message "Warning: ELAB1_oo26: xpif_sif.vhd : There is no default binding for compnent "fifo_sr_5x15". (No entity named "fifo_sr_5x15" was found.)" (Using Aldec Active-VHDL v3.6) Any suggestions on how to get this working properly would be greatly appreciated. -Kent ------------ Kent Orthner korthner at hotmail dot comArticle: 24028
In article <8lgo13$2nj@inf-gw.inf.furukawa.co.jp>,
"K.Orthner" <nospam@ihatespam.com> wrote:
> Using Xilinx Foundation 2.1i . . . . .
>
> I believe that I've managed to create an Asynch FIFO using Xilinx
CoreGen
> utility. I have the .VHO and .EDF files. I'm trying to figure out
how to
> include the CoreGen Part in my simulation. I've read the bit about
using
> get_models, and that seems ro run fine. I've also fiddled with the
> configuration until it compiles fine. but when it's all said and
done, I
> get the message "Warning: ELAB1_oo26: xpif_sif.vhd : There is no
default
> binding for compnent "fifo_sr_5x15". (No entity named "fifo_sr_5x15"
was
> found.)" (Using Aldec Active-VHDL v3.6)
>
> Any suggestions on how to get this working properly would be greatly
> appreciated.
>
> -Kent
>
> ------------
> Kent Orthner
> korthner at hotmail dot com
>
>
Kent,
you may want to the following Perl script to integrate CoreGen Modules
into Active-HDL. Main purpose of the script is, to create a VHDL file
from the VHO, so that you do not need configurations. Furthermore I
feel that it integrates very nicely with Active-HDL... In case you
cannot reformat the line breaks, I will be happy to mail the script to
you.
You may need to update Active-HDL's XilinxCoreLib library to match your
CoreGenerator version, there is an updated version on Aldec's website.
Best regards
Felix Bertram
#-----------------------------------------------------------------------
--------
use Aldec::FrameConnector;
use Aldec::ID;
#-----------------------------------------------------------------------
--------
$DesignBrowser = ConnectPlugIn(CLSID_ProjectPlugIn, IID_IDesignBrowser);
$DesignInfo= ConnectPlugIn(CLSID_ProjectPlugIn, IID_IDesignInfo);
$DesignFiles= ConnectPlugIn(CLSID_ProjectPlugIn, IID_IDesignFiles);
$Opened= $DesignBrowser->IsDesignOpened;
$DesignName= $DesignInfo->GetDesignName();
$DesignFolder= $DesignInfo->GetDesignFolder();
$CurrentConfig= $DesignInfo->GetCurrentConfigName();
$DesignLibrary= $DesignInfo->GetDesignLibraryName();
$DesignSrc= $DesignInfo->GetDesignSrcFolder();
@Files= split("\n", $DesignFiles->GetDesignFiles(0x70001, ""));
#-----------------------------------------------------------------------
--------
$CoreFolder= $DesignSrc."\\LogiCORE";
$CoreFolder=~ s/\\/\//g;
$CorePrj= "coregen.prj";
$CoreCm= "core.cm";
$CoreIni= "core.ini";
mkdir($CoreFolder, 0744);
chdir $CoreFolder;
#-----------------------------------------------------------------------
--------
# create new CoreGenerator project
if (!-e $CorePrj)
{ print "*** create new project ***\n";
open(CM, ">$CoreCm");
print CM "NEWPROJECT $CoreFolder";
close CM;
open(INI, ">$CoreIni");
print INI '# Xilinx CORE Generator'."\n";
print INI "SET FoundationPath = %XILINX%\n";
print INI "SET XilinxFamily = Virtex\n";
print INI "SET DesignFlow = VHDL\n";
print INI "SET FlowVendor = Other\n";
print INI "SET BusFormat = BusFormatAngleBracket\n";
print INI "SET SimulationOutputProducts = VHDL\n";
print INI "SET OverwriteFiles=True\n";
#print INI "SET LockProjectProps = true\n";
close INI;
#*** launch core generator
# -b <command file name>
# -i <coregen ini file name>
# -p <project path>
# -q <polling dir path>
$syscmd= "$ENV{XILINX}\\bin\\nt\\coregen.bat -b $CoreCm";
system($syscmd); #print $syscmd;
$syscmd= "$ENV{XILINX}\\bin\\nt\\coregen.bat -p . -q . -i
$CoreIni";
system($syscmd); #print $syscmd;
}
else
#-----------------------------------------------------------------------
--------
# open existing CoreGenerator project
{ print "*** open existing project ***\n";
$syscmd= "$ENV{XILINX}\\bin\\nt\\coregen.bat -p . -q .";
#system($syscmd); #print $syscmd;
}
#-----------------------------------------------------------------------
--------
# scan vho files
opendir(VHODIR, ".");
while($vhofile= readdir(VHODIR))
{ if ($vhofile=~ m/.*\.vho$/)
{ print "*** convert $vhofile ***\n";
$state= 0;
$vho_comp= ""; # state= 1
$vho_inst= ""; # state= 2
$vho_lib= ""; # state= 3
$vho_conf= ""; # state= 4
open(VHO, $vhofile);
while($line= <VHO>)
{ if ($line=~ m/_TAG_END/) {$state= 0};
if ($state== 1) {$vho_comp.= $line;}
if ($state== 2) {$vho_inst.= $line;}
if ($state== 3) {$vho_lib.= $line;}
if ($state== 4) {$vho_conf.= $line;}
if ($line=~ m/COMP_TAG$/) {$state= 1};
if ($line=~ m/INST_TAG$/) {$state= 2};
if ($line=~ m/LIB_TAG$/) {$state= 3};
if ($line=~ m/CONF_TAG$/) {$state= 4};
}
close(VHO);
#-----------------------------------------------------------------------
--------
# convert to vhd file
$entity= $vhofile;
$entity=~ s/.vho//;
$entity2= $entity."ii";
$vhdfile= $entity.".vhd";
open(VHD, ">$vhdfile");
#-- header comment
print VHD "-"x80 ."\n";
print VHD "-- File: $vhdfile\n";
print VHD "-- Description: CoreGenerator simulation
model\n";
print VHD "-- Notes: * * * D O N O T E D I
T * * *\n";
print VHD "-- Created by: COREGEN.pl script\n";
print VHD "-"x80 ."\n";
#-- library declaration
print VHD "library IEEE;\n";
print VHD "use IEEE.STD_LOGIC_1164.all;\n";
print VHD $vho_lib;
#-- entity declaration
$vhd_entity= $vho_comp;
$vhd_entity=~ s/component/entity/;
$vhd_entity=~ s/component/entity/;
$vhd_entity=~ s/port/is port/;
print VHD $vhd_entity;
#-- architecture declaration
print VHD "\n". "-"x80 ."\n";
print VHD "architecture Sim of $entity is\n";
#-- component declaration
$vhd_comp= $vho_comp;
$vhd_comp=~ s/$entity/$entity2/;
print VHD $vhd_comp;
#-- configuration
$vhd_conf= $vho_conf;
$vhd_conf=~ s/$entity/$entity2/;
$vhd_conf=~ s/end for;//;
print VHD $vhd_conf;
print VHD "begin\n";
#-- instantiation
$vhd_inst= $vho_inst;
$vhd_inst=~ s/$entity/$entity2/;
print VHD $vhd_inst;
print VHD "end Sim;\n";
print VHD "-"x80 ."\n-- end of file\n";
close(VHD);
#-----------------------------------------------------------------------
--------
#-- add vhd file to project
$addpath= $CoreFolder."/$vhdfile";
$DesignFiles->AddFile($addpath, "", "", 0);
}
}
closedir(VHODIR);
print "*** done ***\n";
#-----------------------------------------------------------------------
--------
# end of file
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24029Jonas Thor wrote: > > Hi, > > Hello! > > We have an interesting problem, 17 clocks that are not synchronized. > We are going to prototype an 8 port Ethernet (10 Mbit) switch in a > Virtex 1000. There's one tx-clock and one rx-clock for each interface > and there is a global clock which we will set to 10Mhz. The tx are rx > clocks are 2.5 MHz. The reason why the global clock will only be at 10 > MHz is simply because we want to make the design more challenging, > since a low clock rate makes the queing and buffering handling more > difficult. I should say that I work at a university, so we are allowed > to make things more difficult than they really are ;) > > Anyway our first problem is to synch the data from the 8 ports to the > global clock. Since we have 17 clocks we are out of global clock > routing. My first idea would be to have 16 16-bit deep asynch fifos > implemented in CLBs. Each port would have one rx fifo and one tx fifo > and the fifos should be placed as close to the port as possible. The > fifo would be based on Peter Alfkes appnote (XAPP051 I believe). > > However the problem here, as I see it, is to make sure that the skew > between the port data rx and tx clocks are minimal. > > Any comments about the suggested solution? Some other approach that > migth be better? I have never worked with a Virtex device before. > Previous work has been with the XC4000 and these have different clock > distributing resources compared the Virtex series. > > Jonas Thor > NoSpamthor@sm.luth.seNoSpam - remove the obvious when replying > Lulea University of Technology > Sweden Hi Jonas, What about this: 2.5MHz is not very fast, so You can use your 10MHz clock as the one and only global clock for all the things you do. I.e. if an input signal is high, you have 4 cycles to get it. All of your rx_clock's are 2 cycles long high (they should be???), this allows you following code: process ... if(clk'EVENT) and (clk='1') then if(rx_clk='1') then reg_input <= rx_data; else reg_input <= reg_input; end if; end if; ... Look in the 10Mbit-PHY Databook. There You will find exakt specifications about the timings (i.e. high/low-times of your rx_clocks). They will help you to find a suitable global clock. Maybe 20MHz are better, I don't know. So You have one global clock clk and a registered input reg_input. Michael mlschmid@iis.fhg.deArticle: 24030
This is just to correct the percentage of area and power saving of our latest prototype that actually are 41% and 42 %, respectively. Best regards, Pasquale Corsonello Pasquale Corsonello wrote: > *******To anyone is involved in VLSI digital designs******* > > This is to announce a new family of adders that involve a new bit block > structure that computes propagate signals called "carry strength" in a > ripple fashion. A 32-bit carry-skip adder designed using the new method > and realized using 0.6um CMOS technology shows a performance gain of > more than 30% with respect to a conventional carry-skip adder, and > reaches a performance comparable with that of a traditional block-CLA > saving more than 26% silicon area and more than 34% power. Results will > be discussed at the SSGRR 2000 Conference in L'Aquila, Italy > (http://www.ssgrr.it/en/conferenza/index.htm). > > The new approach has been also applied to spanning-tree adders > (Lynch-Swartzlander 1991 and Kantabutra 1993). Results will be broadcast > at the First Online Symposium for Electronics Engineers > (www.techonline/OSEE) > > Please, anyone interested in these results may visit our Web sites or > contact us. > > http://www.ing.unirc.it/didattica/elettr01/index.html > http://www.isu.edu/~kantviti/ > > ********************************************** > *Pasquale Corsonello Microelectronic and Microsystem > *Laboratory > *Department of Electronic Computer Science and System > *University of Calabria > *Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY > *Tel:+39 984 494708 Fax:+39 984 494713 > *email: pascor@deis.unical.it > * http://www.ing.unirc.it/didattica/elettr01/index.html > ********************************************** > > Vitit Kantabutra, Ph.D. > Associate Professor of Computer Science > College of Engineering > Idaho State University > Pocatello, Idaho 83209-8060 > U.S.A.Article: 24031
"K.Orthner" a écrit : > > [...] I get the message "Warning: ELAB1_oo26: xpif_sif.vhd : There is > no default binding for compnent "fifo_sr_5x15". (No entity named > "fifo_sr_5x15" was found.)" (Using Aldec Active-VHDL v3.6) > > Any suggestions on how to get this working properly would be greatly > appreciated. I had a similar problem last week. You have to add the "for all: xxx use ..." clause right after your component declaration. Don't forget to include the XilinxCoreLib library, too. -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 92400 COURBEVOIE Fax +33 1 46 67 51 01 FRANCEArticle: 24032
Hi I am no expert when it comes to Virtex but you seem to have interpreted the data sheet differently to me. Table 16 says: GCK0, GCK1, GCK2, GCK3 Clock input pins that connect to Global Clock Buffers. These pins become user inputs when not needed for clocks. I took this to mean that if you didn't want/need to use the clock buffer with an input signal you could just use an IBUF instead of IBUFG. This would leave the clock buffer free for use with the DLL etc. If this is not the case I would like to know. Perhaps someone else could clarify this. Kate K.Orthner <nospam@ihatespam.com> wrote in message news:8lg4u4$gjt@inf-gw.inf.furukawa.co.jp... > Hello! > > I've got myself in a bit of a quandry here, and would like some advice. > > I'm using a Virtex 150, using two clocks. Each clock is coming in on a > clock pin, so there's no problem there. Due to a severe shortage of pins, I > have used the other two clock pins as regular I/O ( I was willing to pay the > slight timing penalty of having them routed onto a clock net and then off > again.) > > Now, I would like to use one of the DLL Outputs other than the 0 degrees > output (The 180 degress output, to be precise). As I see it, I'm not going > to be able to implement this, because there's only 4 clock buffers, and I > need 5: > > Buffer #1, #2: Wasted on regular input pins. > Buffer #3: Used for first clock (Feedback and clock signal at 0 degrees) > Buffer #4: Used for 2nd Clock feedback. > Buffer #5: Used for 2nd clock signal at 180 degrees. > > Can anyone think of a way to still use those dedicated pins without > "consuming" a global clock net? Or, a way to provide a feedback to the 2nd > clock without consuming a global clock net? > > Any suggestions at all would be appreciated. > > Note: Since the PCB is already finished, it's difficult to change pin > locations. > > Thanks! > > -Kent > > ------------ > Kent Orthner > korthner at hotmail dot com > >Article: 24033
Hello Andy, We need all 17 clocks, since the 8 tx clocks are generated by the Etherneth PHY chips. / Jonas On Sat, 22 Jul 2000 18:41:23 +0100, Andy Holt <andyh@ncity.ac.uk> wrote: >Do you really need the 17 clocks - cannot all 8 tx-clocks be the same? > >AndyArticle: 24034
Yes create your self a small sdf file with the particular instances that are known to exibit async behaviour and change them to have 0 setup hold. Carry this out after your first annatotion has been done. If you have a lot of them you can even write a perl program to create the sdf for you. If you are really sensible you will append _Meta or something similar so you can find them all at one. If not it is just an iterative process to find all the async flops. Then go and give the designer/coders a big kick up the behind because on large design it makes verification really difficult. Stephen PS. This process works with NC-verilog qwerty@scottfamily.cc wrote: > I am doing a real time sim with the back annotated Verilog and SDF file. > I have a flag which crosses clock domains which at some point changes within > the setup time of a flop in the other domain. This is not really a concern > because it is treated with a metstability flop- but unfortunately it sets > all the internal signals to X- this of course screws up the state machine on the > other side- and the sim is hosed. > > Is there a way to keep the value valid when this happens? Can you back annotate > is as such or is there a switch in NC-Verilog? > > Thanks, > Mike ScottArticle: 24035
"$B0B0f(B $B7r(B" <yasui149@oki.co.jp> wrote in message news:8lgi98$807$1@lyra.eoa.telcom.oki.co.jp... > Hi, > I think you have used BUFGP for #1, #2. How about to use IBUFG for #1,#2 ? You are exactly correct. Once I changed by instantiation of my "wasted pins" to be IBUFG instead of BUFG, it worked perfectly. $B$"$j$,$H$&$4$6$$$^$9!#(B -Kent > > Buffer #1, #2: Wasted on regular input pins. > > Buffer #3: Used for first clock (Feedback and clock signal at 0 degrees) > > Buffer #4: Used for 2nd Clock feedback. > > Buffer #5: Used for 2nd clock signal at 180 degrees. > > ------------ Kent Orthner korthner at hotmail dot comArticle: 24036
sorry, but what's JEDEC Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24037
Hi, should we consider the output of XC4000 SELECT-RAM as combinatorial or no... thanks in advance Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24038
They share the same routing resource. I can't say for the Spartan II familly, but in the Virtex and VirtexE their isn't too many problems for routing since they have a lot of resources. Good luck! Seb. In article <8lf58e$1vs$1@nnrp1.deja.com>, channing@21cn.com wrote: > Hi, all, > > Does anyone know if the BlockRAMs in Xilinx Spartan II/Virtex/Virtex-E > series have their dedicate routing resources, or their share the > routing resources with other CLBs ? > > Any help will be appreciated. > > Channing > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24039
Hi, I was designing for a Virtex XC2000 and I switch to VirtexE familly. On my main computer the change was OK but I got an other computer installed and it failed the mapping saying that the only DLL instance allowed for VirtexE XCV2000 was the CLKDLLE. Does any body now why it work with one computer and not the other or where I could find info about that CLKDLLE? I have look on the xilinx support site but their isn't mutch about that instance. P.S.: I'm running Xilinx Aliance version 3.1i with service patch 1 on both computers and I'm starting the PAR from a common drive. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24040
In article <8lhs5g$tpe$1@nnrp1.deja.com>, erika_uk@my-deja.com wrote: > sorry, but what's JEDEC > > Sent via Deja.com http://www.deja.com/ > Before you buy. > see http://www.jedec.org/ -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24041
K.Orthner wrote in message <8lgfi1$p1k@inf-gw.inf.furukawa.co.jp>...
>It seems as though everyone has targetted the cost of buying a house in the
>Bay area. I've been considering moving there, and would be considerably
>more interested in a simple 2-bedroom apartment than a house. Are the
>prices for renatl apartments just as unreasonable? And would I expect the
>drive to be just as far? (2 hours just doesn't seem reasonable to me.)
A friend of mine moved from here (Tucson) to SF. Since he's single and had
friends there, it was easy for him to find an apartment to share with three
friends. The total rent for the place is something like $1800 per month (I
haven't seen it). He also sold his cars and takes BART.
If you're married, or otherwise have a significant other, I would imagine
that the "Friends" scenario won't interest you.
And a two-hour one-way commute is completely unreasonable. Especially if
it's a twenty-mile drive.
>I figure there has to be some place that the non-high tech people live,
>right? Or are there in non-high tech people left?
Ah, there's the rub. With the incursion of the dot-coms and their
worker-bees into the former "less desireable" areas, the price increases
have pushed out a lot of the indigenous residents. So, who's gonna work in
the Starbucks where you get your $5 latte every morning?
Phooey.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24042The routing is not really shared. You should look carefully at the VIrtex routing structure to understand it. It can't be adequately described in the number of words appropriate for a ng post. If you have the xilinx tools, open up the chip editor for a new design using a virtex 50. From there you will be able to see how the routing, and in particular the BRAM routing is done. The BRAMs can be found on the right and left edges of the die image. channing@21cn.com wrote: > Hi, all, > > Does anyone know if the BlockRAMs in Xilinx Spartan II/Virtex/Virtex-E > series have their dedicate routing resources, or their share the > routing resources with other CLBs ? > > Any help will be appreciated. > > Channing > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24043
FPGA 2001: Call for Papers
Ninth ACM* International Symposium on Field-Programmable Gate Arrays
Monterey, California
February 11-13 2001
Submissions due: September 29, 2000
web site: http://www.ecs.umass.edu/ece/fpga2001
The annual ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays is the premier conference for presentation of advances
in all areas related to FPGA technology. For FPGA 2001, we are
soliciting submissions describing novel research and developments
in the following (and related) areas of interest:
* FPGA Architecture: Logic block & routing architectures, I/O
structures and circuits, new commercial architectures,
Field-Programmable Interconnect Chips and Devices (FPIC/FPID),
Field-Programmable Analog Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization,
technology mapping, system-level partitioning, logic generators,
testing and verification, CAD for FPGA-based accelerators.
* Applications: Innovative use of FPGAs, exploitation of FPGA
features, novel circuits, high-performance and
low-power/mission-critical applications, DSP techniques,
uses of reconfiguration, FPGA-based cores.
* FPGA-based computing engines: Compiled accelerators, reconfigurable
computing, adaptive computing devices, systems and software.
* Rapid-prototyping: Fast prototyping for system-level design,
Multi-Chip Modules (MCMs), logic emulation.
Authors are invited to submit PDF of their paper (12 pages maximum) by
September 29, 2000 via E-mail to fpga2001@cse.ucsc.edu. Notification of
acceptance will be sent by November 22, 2000. The authors of the accepted
papers will be required to submit the final camera-ready copy by
December 6, 2000. A proceedings of the accepted papers will be published
by ACM, and included in the Annual ACM/SIGDA CD-ROM Compendium publication.*
Address questions to:
Martine Schlag, Program Chair, FPGA 2001
Dept. of Computer Engineering,
University of California, Santa Cruz
Santa Cruz, CA 95064
phone: (831) 459-3243
fax: (831) 459-4829
Email: martine@cse.ucsc.edu
General Chair: Scott Hauck, U. of Washington
Program Chair: Martine Schlag, UCSC
Publicity Chair: Russ Tessier, U. Mass.-Amherst
Finance Chair: Steve Trimberger, Xilinx
Program Committee
Ray Andraka, Andraka Consulting Arun Kundu, Actel
Mike Bershteyn, Quickturn Miriam Leeser, Northeastern U.
Richard Cliff, Altera Wayne Luk, Imperial College
Jason Cong, UCLA Margaret Marek-Sadowska, UCSB
Andre DeHon, Caltech Jonathan Rose, U. Toronto
Eugene Ding, Lucent Martine Schlag, UCSC
Carl Ebeling, U. Washington Herman Schmit, CMU
Scott Hauck, U. Washington Charles Stroud, UNC-Charlotte
TingTing Hwang, Natl. Tsing Hua U. Russ Tessier, U. Mass.-Amherst
Sinan Kaptanoglu, Adaptive Silicon Steve Trimberger, Xilinx
Tom Kean, Algotronix Steve Wilton, U. British Columbia
Sponsored by ACM SIGDA, with support from industry.*
Please visit the web site <http://www.ecs.umass.edu/ece/fpga2001> for
more information.
*Pending approval
Article: 24044Guess the question is ambiguous enough to get polar opposites for the answer! The xilinx virtex has a large number of routing traces that are not committed to any one CLB or memory. These are connected by a switch matrix at each CLB location, as well as matrices near the Block RAMs. By appropriate switch connections you can utilize all the CLBs neighboring the Block RAMs as well as the Block RAMs, usually without conflict. The only part of the routes that are dedicated to a particular asset are the short stubs between the asset and the switch matrix, and those are generally not shared with other assets. seb30@my-deja.com wrote: > They share the same routing resource. I can't say for the Spartan II > familly, but in the Virtex and VirtexE their isn't too many problems for > routing since they have a lot of resources. > Good luck! > Seb. > In article ?8lf58e$1vs$1@nnrp1.deja.com?, > channing@21cn.com wrote: > ? Hi, all, > ? > ? Does anyone know if the BlockRAMs in Xilinx Spartan II/Virtex/Virtex-E > ? series have their dedicate routing resources, or their share the > ? routing resources with other CLBs ? > ? > ? Any help will be appreciated. > ? > ? Channing > ? > ? Sent via Deja.com http://www.deja.com/ > ? Before you buy. > ? > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24045
Depends on the usage. The output is combinatorial from the address inputs, it is synchronous from the data input (which is clocked by the rising edge of the write clock). You can put the register in the cell with the RAM to make the output synchronous too. erika_uk@my-deja.com wrote: > Hi, > > should we consider the output of XC4000 SELECT-RAM as combinatorial or > no... > > thanks in advance > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24046
You ought to be able to get it in less than 100 CLBs, although I don't know of a commercially available core off hand. You might check Memec, I think they might have one. The 16 deep FIFOs are a cinch in xilinx thanks to the 'select RAM' which turns a LUT into a 16x1 RAM. You may not need all the modes of the 8250, in which case you can substantially simplify the circuit by having a fixed number of bits, stop and start bits, parity etc. David Dart wrote: > Hi All, > does any one know of a core which has the 8250 with a 16 byte fifo > (Or equivalent) and only uses approx 100 CLB's. I need to place 3 of these > in a XCS30XL with some room to spare. > > thanks in advance. > > -- > David Dart, > email davidd@nulec.com.au -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24047
Not to mention that the xilinx carry chains let you have 3 input arithmetic functions in one level of logic in 4K, or 4 inputs in virtex whether or not you use the clock enable. Altera 10K and Apex only allows 2 inputs in one level for arithmetic, or only 1 input (now there's a useful arithmetic function) if you use clock enable in 10K. This little factoid can double the LUT count required for a design in Altera vs Xilinx. Now, if you use the Xilinx select RAM or SRL16's for delay queues for things like digital filters then you can use as many as 17 times the LUTs in Altera as the same design targeted to Xilinx. Ya'll be careful countin them thar LUTs now, ya hear! Steve Casselman wrote: > You should ask "what company's marketing department should I be working > for?" How many "gates" this translates into is another story but the F5 and > F6 muxes makes the Virtex CLB very powerful in terms of 4 input LUTs. > > Steve Casselman, President > Virtual Computer Corporation > > "rickman" ?spamgoeshere4@yahoo.com? wrote in message > news:396C01FE.F9DAC670@yahoo.com... > ? And what company's marketing department do you work for? ;) > ? > ? > ? Steve Casselman wrote: > ? ? > ? ? There are four 4 LUTs and some other stuff per CLB. > ? ? Really though you can do any function of 6 inputs and it is really a 6 > LUT. > ? ? If you just used 4 LUTs to do any function of 6 inputs you would need > more > ? ? than four 4 LUTs. So 4.5 4 LUTs per CLB is a conservative in my > opinion. > ? ? > ? ? Steve Casselman > ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24048
Yep, just about when the full-up foundation hits v3.1. Coincidence? I don't think so. Anna Acevedo wrote: > The 2.1i Xilinx Student Edition will be available for the start of the Fall > semester > You should be able to order it from www.amazon.com or www.xess.com by > mid August. > > Pratip Mukherjee wrote: > > ? Does any body know when will the new version of Xilinx Student Edition with > ? Foundation 2.x be out? Since coming to know that there will be a new version > ? shortly, I am holding on from buying the new version for about two months now. > ? The wait is killing me. > ? > ? Pratip Mukherjee > > -- > ***************************** > Anna M. Acevedo > Xilinx University Program > 2100 Logic Drive > San Jose, CA 95124 > PH: (408) 879-5338 > FAX: (408) 879-4780 > > Email: anna.acevedo@xilinx.com > http://www.xilinx.com/programs/univ.htm > ***************************** -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24049
Not likely to get good usage by a direct port. The CLB structure is much narrower than the 22V10 macrocell. You'd be much better off going to a CPLD. Also, you'll have to capture the circuit board design somehow too, as the JEDEC files only contain the logic inside each PLD. If you have the source, that would be easier to translate. Tom Vrankar wrote: > Does any JEDEC to VHDL converter exist to allow me to quickly migrate old > circuit card designs based on rafts of 22V10s in DIPs to a single large FPGA? > Either freeware or from a FPGA vendor? I've researched it enough to know I > could do it, but figured it was so obvious someone else must've already done > it, though I don't see it mentioned in any FAQs I've found. > > Thanks. > > twv@ > -- > --------------------------------- > Tom Vrankar > twv at ici.net > http://home.ici.net/~twv/ > Rhode Island, USA -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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