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Brad Smallridge wrote: > I often get Xilinx error messages saying that I can't read a pin that is > configured "out mode" (or something like that). Up to now, to get around > the error, I have been mirroring such a pin with an internal register and > reading the output of the register instead. Recently I find that making > such a pin an inout instead of an out will also let it be read. That's > reasonable but seems contrary to what I believe that an inout pin is a > bidirectional pin. What is the best way to do this, as a matter of style? There is a way to do this, it is called mode "buffer". However, some synthesis tools don't handel it correctly. I typically just make a temporary signal. In vhdl-200x, the next release of VHDL, we are making a "buffer" and "out" signal the same.Article: 73626
ADS.AVNET.COM has several Xilinx-based 'kits.' They also have expansion modules/daughterboards. The kit-boards and expansion-cards use an expansion bus called 'AvBus.' But when I read the product description closely, it seems that all boards use the 'female' connector. I searched and searched AVNET for a AvBus cable, but couldn't find any. So how exactly are users supposed to use those expansion modules, if Avnet doesn't even provide a cable?!?Article: 73627
One of our customers will be asking us to
implement a bunch of math functions on an FPGA-boards.
There are a lot of "decisions" that affect control
processing/algorithm selection, so they specifically
requested an FPGA with "PowerPC." (This immediately
tells me Xilinx's marketing has done an A+ job of getting
managers and other non-technical people to subconsciously
associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :))
As an engineer, for me, the problem isn't the choice of
CPU; Any embedded CPU (OpenRISC, Microblaze,
Nios, etc.) would serve the purpose; as its only going
to read/write internal status/contorl registers
every few 10,000 cycles. The problem is 'how to run
the software app' on the CPU.
Now for my awkward question. I've never done this kind of
'embedded' development before, so I have no clue as to
the normal development flow.
In digging around a few enthusiast websites, I think I
the normal flow requires
a) 'embedded O/S' (running on the embedded CPU target)
b) development tools (C-compiler to target the CPU)
c) your own custom files (for defining I/O ports,
application hardware, etc.)
It sounds all very complicated to me. Can I "skip" the
embedded O/S? I'm just read/writing some registers, not
trying to access a TCP/IP network or USB-filesystem.
I'm an ASIC engineer (mostly RTL Verilog coder) by training,
so I know my way around hardware development.
So, what do you guys recommend to the novice embedded engineer?
Is the Xilinx EDK a good choice? What about the 'OpenRISC'
CPU on opencores.org?
Article: 73628> There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately When the customer hands me a hammer, this is usually a danger flag. > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. Well, of course you can write down-to-the-metal code on any CPU, an OS is not absolutely necessary. However, the "lots of math" specification points me to you probably wanting a DSP, or custom logic implementing the functions in question. Since this is an _F_PGA (after all...) you can always add new algorithms later, no? The question of OS choice generally begins "What features do you expect to get from this OS?" and from the sounds of things, an OS would just get in the way for you.Article: 73629
Lewin A.R.W. Edwards wrote: > The question of OS choice generally begins "What features do you > expect to get from this OS?" and from the sounds of things, an OS > would just get in the way for you. I would have to agree. I'm actually from a software background and from the sounds of what you're doing, an OS (especially something like linux) would be extreme overkill, extend the development, increase the product cost and probably result in a less robust product. I'd stick with a small (customisable) RISC core which will allow you to use a smaller device and easier glue to the core if you can configure the I/O on it. Doing a bit of 'math' every 10,000 cycles shouldn't require a DSP I wouldn't have thought?!? Regards, MarkArticle: 73630
"Christian E. Boehme" <boehme@os.inf.tu-dresden.de> wrote in message news:1096219029.699683@erwin.inf.tu-dresden.de... > Hi all, > > I am currently using the (gratis) Xilinx ISE 6.2i WebPack > for Windows version for developing CPLD and FPGA designs > for reasons that shall not be discussed right now ;) > First thought was to play a little with the tools that come > with it using some application notes code from Xilinx (namely > from XAPP137). Well, that first attempt half-way failed due > to the fact that I somehow seemed to be unable to restore the > archived project that was contained in the xapp137.zip archive > from within the Project Navigator. Is this functionality > possibly only available in the paid-for version ? > > > Thanks and regards, > Christian Boehme Restore ? Need to extract the files from the zip first then add them to a project. Don't think ISE has had a restore function for a while (could be wrong) Remember 2.1 having one. AlexArticle: 73631
Mark McDougall wrote: > Lewin A.R.W. Edwards wrote: > >> The question of OS choice generally begins "What features do you >> expect to get from this OS?" and from the sounds of things, an OS >> would just get in the way for you. > > > I would have to agree. I'm actually from a software background and from > the sounds of what you're doing, an OS (especially something like linux) > would be extreme overkill, extend the development, increase the product > cost and probably result in a less robust product. I agree with this but i'me not an expert (just doing research on this for a project currently). The Stratix2 has some embedded DSP cells that might do the trick. Honnestly if your doing 'lots of math' to me that means 'most likley floating poing'. That can be hard to implement on an fpga. > I'd stick with a small (customisable) RISC core which will allow you to > use a smaller device and easier glue to the core if you can configure > the I/O on it. Doing a bit of 'math' every 10,000 cycles shouldn't > require a DSP I wouldn't have thought?!? I agree also. What kind of "Math" are you doing? IS this a control system? If so there might be better tools to do the job. Does it have to be exactly 10K cycles? if so linux is not a RT operating system (you would have to RTlinux patch it). "Math" is a big field. Doing simple additions would be easy to do in an fpga. Doing non-numerical integration would be very hard on an FPGA but is possible to do on a CPU because they are faster at doing AI stuff. Can you give us a hint of what kind of math will be done? Thanks Andre,Article: 73632
My first bit of advice is take what you get on these newsgroups with a grain of salt. Some of the responses I've seen have basically advised you to tell your customer to bugger-off with the PPC idea. Tactically, that seems like questionable advice to me. In fact, your posting implied that you were ok with the PPC, and just wondering about the OS/tools. Let me address that: Some things to consider: 1) What is the startup time from power-on? An OS like Linux can easily add several seconds to the power-on time-line, depending on how much effort you want to spend to minimize initialization. 2) There are several OS's but Vxworks from Wind River, Integrity from Green Hills Software, and embedded Linux are probably the primary choices. If you are concerned about royalty costs, some flavors of Linux are probably going to be the cheapest approach. (You didn't say if you were particularly cost sensitive). 3) It doesn't sound like your application needs much in the way of OS support with the possible exception of a periodic delay. That can be done pretty easily with a timer channel. 4) A nice benefit of an OS is the ease by which you can develop. For example, OS's often have the ability to automatically collect timing data, or download images via Ethernet. You can usually have several executables installed that you can switch between or even run both at the same time and compare the results. If your algorithm development is going to need a lot of tweaking on the target, an OS may have some benefit. However, if you can do the algorithm modeling on a development workstation, that is probably preferred and just use the EDK to download to a 'bare' the target via the parallel port. Do you know how many lines of software you expect to develop? "A bunch of math functions" could be a chess game or a robotics application. -bh "hol" <abol@hol.com> wrote in message news:MrI5d.20255$QJ3.5247@newssvr21.news.prodigy.com... > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. > > Now for my awkward question. I've never done this kind of > 'embedded' development before, so I have no clue as to > the normal development flow. > > In digging around a few enthusiast websites, I think I > the normal flow requires > a) 'embedded O/S' (running on the embedded CPU target) > b) development tools (C-compiler to target the CPU) > c) your own custom files (for defining I/O ports, > application hardware, etc.) > > It sounds all very complicated to me. Can I "skip" the > embedded O/S? I'm just read/writing some registers, not > trying to access a TCP/IP network or USB-filesystem. > > I'm an ASIC engineer (mostly RTL Verilog coder) by training, > so I know my way around hardware development. > > So, what do you guys recommend to the novice embedded engineer? > Is the Xilinx EDK a good choice? What about the 'OpenRISC' > CPU on opencores.org?Article: 73633
Quote from Xilinx Website (the best support web as many seem to claim!): "Support for 3S1000 and 3S1500 devices is available in ISE WebPACK 6.3i only when the product is downloaded and installed from the Web at www.xilinx.com/ise/webpack6" if you go to the link to download 6.3 you get what ? guess: you land to 6.2 download pages!! ISE 6.3 is available as ""free"" CD for 20 USD shipping, but as per quote above if you dont download from the (dead) link you will not get 3S1000/1500 support! So you have to pay 20 USD to get less than you could get for free (if xilinx would fix the wrong link to the download) So as the things stand today: since ISE 6.3 free webpack is no longer available, not from web download not as CDROM (20USD shipping charges apply). I dont mind the 20USD and I dont need the Webpack either, but I also dont like people being fooled around with incorrect information. AnttiArticle: 73634
> : So as the things stand today: since ISE 6.3 free webpack is no longer > : available, not from web download not as CDROM (20USD shipping charges > : apply). I dont mind the 20USD and I dont need the Webpack either, but I also > : dont like people being fooled around with incorrect information. > > The 6.3 Webpack had problems and was withdrawn. Expect a corrected version soon. thanks! I wonder why that information is not available from Xilinx!! AnttiArticle: 73635
Ah, but Steve Lass posted and apologised on comp.arch.fpga about it. Check out the thread entitled "Webpack 6.3 and Spartan3-1000/1500". Cheers, Syms. "Antti Lukats" <antti@case2000.com> wrote in message news:cj74jc$le8$00$1@news.t-online.com... >> : So as the things stand today: since ISE 6.3 free webpack is no longer >> : available, not from web download not as CDROM (20USD shipping charges >> : apply). I dont mind the 20USD and I dont need the Webpack either, but I > also >> : dont like people being fooled around with incorrect information. >> >> The 6.3 Webpack had problems and was withdrawn. Expect a corrected >> version > soon. > > thanks! > I wonder why that information is not available from Xilinx!! > Antti > >Article: 73636
"Andre Bonin" <Yoyoma_2@[at-]Hotmail.com> wrote in message news:4TK5d.120311$%S.55720@pd7tw2no... > Mark McDougall wrote: > > Lewin A.R.W. Edwards wrote: > > > >> The question of OS choice generally begins "What features do you > >> expect to get from this OS?" and from the sounds of things, an OS > >> would just get in the way for you. > > > > > > I would have to agree. I'm actually from a software background and from > > the sounds of what you're doing, an OS (especially something like linux) > > would be extreme overkill, extend the development, increase the product > > cost and probably result in a less robust product. > > I agree with this but i'me not an expert (just doing research on this > for a project currently). > > The Stratix2 has some embedded DSP cells that might do the trick. > > Honnestly if your doing 'lots of math' to me that means 'most likley > floating poing'. That can be hard to implement on an fpga. > Floating point is not hard - fast, high-resolution, compact floating point is hard. If you are looking at doing "some" maths every 10,000 cycles, then any decent 32-bit risc cpu can handle it in software without breaking a sweat. From the programmer's viewpoint, the software code is the same. > > I'd stick with a small (customisable) RISC core which will allow you to > > use a smaller device and easier glue to the core if you can configure > > the I/O on it. Doing a bit of 'math' every 10,000 cycles shouldn't > > require a DSP I wouldn't have thought?!? > I think you are best looking at ready-to-run setups, and almost certainly using a soft cpu. Forget the Virtex embedded PPC unless you have real, concrete figures showing that it is necessary - I'm sure there are many applications where they are highly suitable, but the PPC is a beast of a processor to work with, and your chips and tools are going to be very expensive. These particular chips are clocked at a few hundred MHz (IIRC), but they have no floating point, so they have to use software. If you pick a soft cpu, you can add floating point hardware as needed in the fpga structure, and have it running the maths much faster than the ppc. I can't talk about Xilinx Microblaize, having never tried it, but I think you'd find the Altera Nios II at least as easy as anything else around. Buy a developer kit, and you get a board and all the software and tools you need. I don't think you need an OS for this project - but if you want one, there is well-integrated support for uC/OS-II (although you'd need to by a license seperately), and you can download ucLinux support. > I agree also. What kind of "Math" are you doing? IS this a control > system? If so there might be better tools to do the job. > > Does it have to be exactly 10K cycles? if so linux is not a RT operating > system (you would have to RTlinux patch it). "Math" is a big field. > Doing simple additions would be easy to do in an fpga. Doing > non-numerical integration would be very hard on an FPGA but is possible > to do on a CPU because they are faster at doing AI stuff. > > Can you give us a hint of what kind of math will be done? > > Thanks > Andre,Article: 73637
Hi, How do I get this library trough compilation. When I include this in my vhdl it gives an error with compilation. If I leave it out synplify giveas an error with synthesis. And I don't like to manual add this to the vhdl every thime. BramArticle: 73638
Use the unisim library instead. library unisim; use unisim.vcomponents.all; the "virtex2.components" package is only there for compatability with old projects. - Ken van de Kerkhof wrote: > Hi, > > How do I get this library trough compilation. When I include this in my vhdl > it gives an error with compilation. > If I leave it out synplify giveas an error with synthesis. And I don't like > to manual add this to the vhdl every thime. > > Bram > >Article: 73639
hol wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. > > Now for my awkward question. I've never done this kind of > 'embedded' development before, so I have no clue as to > the normal development flow. > > In digging around a few enthusiast websites, I think I > the normal flow requires > a) 'embedded O/S' (running on the embedded CPU target) > b) development tools (C-compiler to target the CPU) > c) your own custom files (for defining I/O ports, > application hardware, etc.) > > It sounds all very complicated to me. Can I "skip" the > embedded O/S? I'm just read/writing some registers, not > trying to access a TCP/IP network or USB-filesystem. > > I'm an ASIC engineer (mostly RTL Verilog coder) by training, > so I know my way around hardware development. > > So, what do you guys recommend to the novice embedded engineer? > Is the Xilinx EDK a good choice? What about the 'OpenRISC' > CPU on opencores.org? Hi Hol, After very good answers (IMO) depending your OS questions I will try to give You some hints about Xilinx Virtex2-Pro and EDK. 1. The EDK contains lots of IP-Cores important to build an Embedded System inside Your Xilinx FPGA (i.e. Microblaze, Bus-Interfaces, DRAM-Controller, Flash-Interface, UART, ...). The important cores are free, some cores have costs (i.e. Ethernet, FullFunction-UART, ...). 2. The EDK comes with the GNUCompilerConnection for PPC and Microblaze, including also Debug-Tools who are essentially for every SW-Developer! 3. Without the EDK You will have big trouble to implement a PPC-System because of missing Bus-Interfaces and other environmental things needed to get the PPC working. I don't say it doesn't work and it doesn't make sense in some cases, but it definitely makes a lot of work to build a PPC-System inside the XC2VP without support from EDK. 4. The EDK brings You libraries for the IP-Cores which speed up the Programming process. This is a good thing and works most times. But like every SW it has sometimes problems. 5. The EDK tries (more and more with every version :-) to keep HW- and SW-Designflow together which is not trivial if You do it on Your own. Fazit: If You want to do an Embedded System on an Xilinx FPGA don't start without EDK. If You know exectly that some easy register moving and BitManipulation is everything you want to do, writing an Application without OS could work for you. Positive Sideeffekt: Small Applikations fit often in BlockRAMs (less external components). If you need things like networking, multitasking, graphics, ... don't try it on yourself, use the right OS for your type of applications. Hope this helps, Michael -- Notice: If You want to send me an E-Mail please remove the abc and xyz from my address.Article: 73640
Dear All, I connect an open drain Pin from a PIC18F448 (RA4) to the GCLRn Pin of a max7000s and to a 4k75 pull-up. When the Altera is not connected and I put a '0' in that pin all goes OK, I see a '0'. But, if I connect the Altera and place a '0' I see an '1'. So here is my question, is the GCLRn pin an special pin?. I mean, does it need more input current than 10uA (from datasheet)?. Thanks a lot and best regards, JaviArticle: 73641
hol wrote: > ADS.AVNET.COM has several Xilinx-based 'kits.' They > also have expansion modules/daughterboards. The > kit-boards and expansion-cards use an expansion bus > called 'AvBus.' But when I read the product description > closely, it seems that all boards use the 'female' > connector. > > I searched and searched AVNET for a AvBus cable, but > couldn't find any. So how exactly are users supposed > to use those expansion modules, if Avnet doesn't > even provide a cable?!? The kit I have ( Spartan 3 ), has both male and female, on each side of the PCB.Article: 73642
Maybe someone knows where I can get a schematic of the MJL Cyclone Development Kit board? Thx.Article: 73643
gvaglia@gmail.com (Guido) wrote in message news:<44f5f440.0409260126.471a2365@posting.google.com>... > Thank you for your reply. > I read that the PROM used in my Spartan3 Board, a XCF02S is full 5V > tolerant if supplied with 3.3V (as it is in the board). So in this > case it's not strictly necessary to put the series resistors, is it? Well, if you do JTAG programming and the FPGA is in the same JTAG chain then the FPGAs TCK and TMS inputs will be driven by the download cable. So you need the series resistors. Also, if the FPGA is behind the PROM in the JTAG chain the TDO pin will be driven to 2.5V by the XC3S. A 5V download cable with CMOS buffers will not recognize this as logic 1. (TTL buffers would) > Another thing...can you tell me where can I found the schematic for > the parallel cable III? first hit on google for parallel cable III schematic also answer #3418 in the xilinx answer database. Search this newsgroup for more detailed comments by me on how to improve the download cable. Kolja SulimmaArticle: 73644
"zg" <zohargolan@hotmail.com> wrote in message news:e24ecb44.0409241455.340ba130@posting.google.com... > Hi All, > > I am trying to use the SDR SDRAM controller that is comming with the > NIOS II development package. In the simulation it looks like this core > supports only 2 words bursts. I couldn't find anything in the > documentations. > Am I correct? > If this core supports bigger bursts then 2 words, any ideas what am I > doing wrong? > > Thank you all > Zohar Zohar, I'm working on a design that uses one 16MB sdram chip for most of its instruction and data memory. I rely heavily on dma and other burst reads and writes (ie cache) to get the performance I need. The sdram controller you're talking about is good enough to burst 480 32 bit words in under 485 cpu clocks. It's a beautiful thing to watch in Signal Tap as I get this performance. (Haven't explored the lenght limits above 480 - my external fifo's AlmostFull level) I'm hammering that sdram (through the Altera sdram controller) nines ways to Sunday and it performs flawlessly. I have some serious issues with the whole NiosI/II chain, but the sdram controller has been a champ. KenArticle: 73645
Dear All,
I have used the Behavioral Compiler to synthesize a FIR filter.
I want to constrain a loop. But when I use " find " command to find the
loop, it always reports error and get no results.
the command I used is
"bc_shell> find cell -hierarchy *filter_loop*"
and the feedback is :
"Error: Can't find object '*filter_loop*'.(UID-109)
{}"
How could I solve this problem?
Thanks a lot.
Best Regards
Yiyin Wang
My code is below:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY fir_filter2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
load : IN std_logic;
data_in : IN signed( 11 DOWNTO 0 );
coeff_addr : IN unsigned( 3 DOWNTO 0 );
start : IN std_logic;
data_out : OUT signed( 11 DOWNTO 0 )
);
END fir_filter2;
ARCHITECTURE behavioral OF fir_filter2 IS
BEGIN
main_proc: PROCESS
SUBTYPE coeff_element IS signed( 11 DOWNTO 0 );
TYPE coeff_type IS ARRAY ( integer RANGE <> ) OF
coeff_element;
VARIABLE coeff : coeff_type( 0 TO 14 );
SUBTYPE history_element IS signed( 11 DOWNTO 0 );
TYPE history_type IS ARRAY ( integer RANGE <> ) OF
history_element;
VARIABLE history : history_type( 0 TO 14 );
VARIABLE sum : signed( 23 DOWNTO 0 );
ATTRIBUTE unroll_new_instance : boolean;
ATTRIBUTE unroll_new_instance OF sum : VARIABLE IS true;
BEGIN
reset_loop: LOOP
--
-- reset the data output
--
data_out <= ( OTHERS => '0' );
WAIT UNTIL clk'EVENT AND ( clk = '1' );
EXIT reset_loop WHEN ( rst = '1' );
--
-- Initialize all coefficients to zero
--
FOR i IN 0 TO 14 LOOP
coeff( i ) := ( OTHERS => '0' );
END LOOP;
--
-- Initialize history memory to zero
--
FOR i IN 0 TO 14 LOOP
history( i ) := ( OTHERS => '0' );
END LOOP;
main_loop: LOOP
config_loop: LOOP
--
-- Wait until next clock cycle to check for
-- load or filter signals.
--
WAIT UNTIL clk'EVENT AND ( clk = '1' );
EXIT reset_loop WHEN ( rst = '1' );
IF ( start = '1' ) THEN
EXIT config_loop;
END IF;
IF ( load = '1' ) THEN
coeff( conv_integer( '0' & coeff_addr ) ) :=
data_in;
END IF;
END LOOP config_loop;
--
-- Main filter loop
--
filter_loop: LOOP -- pragma n_unroll 3
-- pragma pipeline_init_interval 1
WAIT UNTIL clk'EVENT AND ( clk = '1' );
EXIT reset_loop WHEN ( rst = '1' );
history( 0 ) := signed( data_in );
sum := ( ( ( history( 0 ) * coeff( 0 ) +
history( 1 ) * coeff( 1 ) ) +
( history( 2 ) * coeff( 2 ) +
history( 3 ) * coeff( 3 ) ) ) +
( ( history( 4 ) * coeff( 4 ) +
history( 5 ) * coeff( 5 ) ) +
( history( 6 ) * coeff( 6 ) +
history( 7 ) * coeff( 7 ) ) ) ) +
( ( ( history( 8 ) * coeff( 8 ) +
history( 9 ) * coeff( 9 ) ) +
( history( 10 ) * coeff( 10 ) +
history( 11 ) * coeff( 11 ) ) ) +
( ( history( 12 ) * coeff( 12 ) +
history( 13 ) * coeff( 13 ) ) +
history( 14 ) * coeff( 14 ) ) );
data_out <= sum( 23 DOWNTO 12 );
FOR i IN 14 DOWNTO 1 LOOP
history( i ) := history( i - 1 );
END LOOP;
END LOOP filter_loop;
END LOOP main_loop;
END LOOP reset_loop;
END PROCESS;
END behavioral;
Article: 73646
I have an EDK design with a MicroBlaze processor and use the External
Memory Controller (EMC) to get access to off-chip SRAM.
I access the SRAM from c using a pointer and have a loop in my program
that writes a value and increments the pointer to the next address.
As I am using a pointer to type integer it is increased by 4 locations
each time I increment it. The SRAM I am accessing however is 32 bits
wide so I am not getting access to the full memory capacity. Is there a
setting somewhere for the compiler to tell it to increase by 1 address
location or am I using the wrong approach.
I am a beginner with this technology so apologies if this is a dumb
question.
>>>>
int *sram_addr_data;
int i;
sram_addr_data=(int *) XPAR_SRAM0_MEM0_BASEADDR;
for(i=0;i<NUM_LOOP;i++)
{
*sram_addr_data = i;
sram_addr_data++;
}
>>>>
Article: 73647Kubik, They may only be used in an hspice environment. Depending on the device, there are also nspice encrypted format models available, as well as Mentor's spice format. The only model that is worth anything at all for MGTs is a spice model, and since we (and others) do not design MGTs for free, we must protect ourselves by encrypting. If you are interested in "what if" type of information, please consult: http://www.support.xilinx.com/products/xaw/hsd/simulator.htm There are thousands of spice simulations that we already ran for you, just pick the ones that are like your application. Austin kubik wrote: > I' ve registered my account into xilinx form for downloading > the spice models for rocket io etc etc that xilix give on the site. > However these models are encrypted. > How can i use them if they are encrypted. What else i need for using them? > Can i use them in a spice3f5 or LTspice or Orcad environment? > > Thanks >Article: 73648
Steven, As your mention, "If the power supply doesn't have enough capacity, then the FPGA may fail to configure.". Does it effect in only the master serial mode or all configuration mode include JTAG mode? Channing "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> дÈëÓʼþ news:civ1kc$k762@cliff.xsj.xilinx.com... > > "Kolja Sulimma" <news@sulimma.de> wrote in message > news:b890a7a.0409230709.2c524560@posting.google.com... > > Austin, > > > > you are probably the right person to answer this question: > > > > I made a mistake and now I have a board with a XC3S200FT that has a > > ramp up time for the 2.5V power supply of only about 300us. That is > > only about half us much as required by the datasheet. > > > > One I/O bank uses 2.5V as VCCIO, the others use 3.3V which has a ramp > > up time of 600us. > > > > Apparently the board is working normally. Can anyone comment on what > > kind of mishap I could expect because of this? > > If there is a bad effect that does not happen on the prototype, how > > will it be triggered on future boards: Temperature? Chip to chip > > tolerances? > > > > Or is the safety margin in the datasheet large enough that I can > > ignore this? > > > > Kolja Sulimma > > If the 2.5V, 300 us ramp is on the VCCAUX supply only, then no problem. > However, if one of the VCCO_# supplies also connects to the 2.5V supply, > then yes, the design violates the current Tcco specification in the > Spartan-3 data sheet (Table 3 of the Spartan-3 data sheet, page 3). > http://www.xilinx.com/bvdocs/publications/ds099-3.pdf > > The Tcco specification for the XC3S200 in the FT256 package is 600 us (0.6 > ms). That's a worst-case value. Most devices, but not all under worst-case > conditions, should function with a 300 us ramp rate. Your prototype design > should be fine, although Xilinx does not guarantee it with a 300 us ramp > rate. Can you ignore it for your production design? Not if you want > guaranteed success for every board. > > So what happens if you violate the specification? In the XC3S200, you could > potentially trigger the aggressive ESD protection circuit. You will see > additional current draw, but only if the VCCO ramps too fast. If the power > supply doesn't have enough capacity, then the FPGA may fail to configure. > If the supply does have enough capacity, then the FPGA will configure, but > may still draw current. If the VCCO supply ramps slower than the Tcco > specification, then you will never see this condition. > > The overly aggressive ESD circuit is tamed in the XC3S50 and XC3S1000 FPGAs > available today. There is no ramp limit for these devices. If the > ramp-rate is a concern in your design, the XC3S1000 is also available in a > pin-compatible FT256 package. > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > >Article: 73649
hol wrote: > One of our customers will be asking us to > implement a bunch of math functions on an FPGA-boards. > There are a lot of "decisions" that affect control > processing/algorithm selection, so they specifically > requested an FPGA with "PowerPC." (This immediately > tells me Xilinx's marketing has done an A+ job of getting > managers and other non-technical people to subconsciously > associate 'FPGA CPU' with Xilinx's Virtex2Pro product. :)) > > As an engineer, for me, the problem isn't the choice of > CPU; Any embedded CPU (OpenRISC, Microblaze, > Nios, etc.) would serve the purpose; as its only going > to read/write internal status/contorl registers > every few 10,000 cycles. The problem is 'how to run > the software app' on the CPU. I have to wonder if a DSP wouldn't be a better and cheaper solution. > Now for my awkward question. I've never done this kind of > 'embedded' development before, so I have no clue as to > the normal development flow. > > In digging around a few enthusiast websites, I think I > the normal flow requires > a) 'embedded O/S' (running on the embedded CPU target) > b) development tools (C-compiler to target the CPU) > c) your own custom files (for defining I/O ports, > application hardware, etc.) > > It sounds all very complicated to me. Can I "skip" the > embedded O/S? I'm just read/writing some registers, not > trying to access a TCP/IP network or USB-filesystem. > > I'm an ASIC engineer (mostly RTL Verilog coder) by training, > so I know my way around hardware development. > > So, what do you guys recommend to the novice embedded engineer? > Is the Xilinx EDK a good choice? What about the 'OpenRISC' > CPU on opencores.org?
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