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Is there some article about the competing timeline story between xilinx and altera?Article: 73976
> However, the board and the documentation is fine. It took me only half
a
> day to port JOP (a Java processor) from the Altera Cyclone to the
Spartan
> (thanks to Ed Anuff who did the hard part and wrote a memory generator
> for Xilinx). Just two Xilinx specific files for the top-level and the
> memory interface. You can find a Xilinx ISE project under xilinx/s3sk
for
> JOP on this board.
>
For those who are interested in a short comparison between Cyclone and
Spartan-3:
Cyclone EP1C6Q240C6:
fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
Spartan-3 XC3S200-5
fmax: 82 MHz, 2015 LC/Es (52% out of 3840)
I mean a 4 input LUT with register for the LC/E comparison. The CLB or
slice numbers are just confusing. We can see that JOP needs about the
same resources in the A and X devices.
Both devices used are the fastest speed grade available. Is the Cyclone,
although 'older', faster than the Spartan-3?
It's interesting when we compare the two devices with respect to LC/Es
and memory (In case of memory I count K-Bytes (not bits) and don't care
about a 9th parity bit... Why do I need a parity bit for the block RAM?
Is there also a parity protection for the SRAM based configuration?):
XC3S50: 1536 LC/Es, 4*2KB=8KB, 4 HW multiplier
EP1C3: 2910 LC/Es, 13*0.5KB= 6.5KB
XC3S200: 3840 LC/Es, 12*2KB=24KB, 12 HW multiplier
EP1C4: 4000 LC/Es, 17*0.5KB= 8.5KB
EP1C6: 5980 LC/Es, 20*0.5KB= 10KB
XC3S400: 7168 LC/Es, 16*2KB=32KB, 16 HW multiplier
EP1C12: 12060 LC/Es, 52*0.5KB= 26KB
XC3S1000: 15360 LC/Es, 24*2KB=48KB, 24 HW multiplier
EP1C20: 20060 LC/Es, 64*0.5KB=32KB
XC3S1500: 26624 LC/Es, 32*2KB=64KB, 32 HW multiplier
When we order the parts with respect to LC/E count they alternate in a
nice way. Does that mean that our design complexity determines the
choice?
Not that easy. The X parts have more memory per LC and additional
multipliers. However, I don't have prices, a very important 'feature',
handy for all these devices :-)
Martin
Article: 73977> Do FPGAs typically have significant 'hidden' test structures on board? > Did they in the past? There are hidden test structures. But they are not very significant at all. There is some extra goo that makes it cheaper/faster to test the chip and to hit full coverage of some circuitry. But that's about it. > I'm pretty much Xilinx in my DNA, but as I recall Altera used to > advertise a spare-column arangement to improve yield, as in DRAM. > I guess this would be more or less impossible with ASICs, and maybe > impossible with modern FPGAs. Probably impossible (or too costly) with irregular ASICs. Not impossible with modern FPGAs (see USPO). We still use redundancy technology in our FPGAs, and it helps reduce our costs and improve our margins. The cost is some increased complexity and silicon area, but we pay this in exchange for repairability and thus enhanced yield. Depending on the incremental silicon cost, die size of the product, and assumed yield, the exact benefit of redundancy changes. But it is pretty tricky to reliably ship big (500 um^2?) devices or on brand-new processes without yield-enhancing technology. As far as timing models go, any implication that redundancy affects quality of timing models is pure FUD. So long as the max and min delays reflected within the software are an upper-bound and lower-bound on the delay that can be seen in any repaired part, then everything's cool. Regards, Paul Leventis Altera Corp.Article: 73978
Martin Schoeberl wrote: > I got the Spartan-3 Starter Kit yesterday from Xilinx. This board is a > really good bargain: A XC3S200 and 1MB SRAM for just $ 99,-. This board > makes it hard for guys like Tony Burch or me to sell FPGA boards ;-( > Only the Flash is a little bit small.... Not too much space left for > application data. However, the board and the documentation is fine. > Good to know that people like it, because I'm also "seriously buying" it! However, being a complete newbie to FPGA's, I would like to know what range of applications this "DO-SPAR3-DK with XC3S200 FT256 Xilinx Spartan-3 FPGA" (just to make sure that we are speaking of the same device!) is good for. For example, at Xilinx's site there is a list of various (mainly third party) processor cores, starting from MC68000 and ending to Z80: http://www.xilinx.com/xlnx/xebiz/search/searchresult.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-538081125&iLanguageID=1&_ResultsView=Standard&_IPSubcategory=Processor+Core&_IPCategory=Microprocessor+Controller+and+Peripheral&_IPProducts=Core And for example, in CAST Inc.'s C68000's Data Sheet http://www.xilinx.com/bvdocs/ipcenter/data_sheet/CAST_C68000.pdf there is "Table 1: Example Implementation Statistics", where the most low-end device listed is Spartan-IIE XC2S400E-7. Does this mean that it is impossible to fit C68000 into XC3S200 which has only half of the system gates of XC2S400E-7 ? (I don't know whether the gate counts between Spartan-IIE and Spartan-3 series compare linearly.) Same problem with many other CAST's processor cores mentioned: 80C51, TMS32025 and "Z80 Compatible Microprocessor" CZ80CPU, the data sheets mention only Spartan-3 XC3S400-4 and Spartan-IIE XC2S300E-7 and some larger Virtex-II's as Example Devices on which to implement them. Does this mean that XC3S200 has not enough logic to implement ANY of these or just that CAST Inc. didn't have XC3S200-device at hand, and thus haven't tested their designs on it? Also, most of the games and platforms mentioned at: http://www.fpgaarcade.com/ seem to be implemented on at least 300K gate device. So is this 200K-gate XC3S200 thus just a little bit too small for them? (Hmm... although on "Space Invaders" page: http://home.freeuk.com/fpgaarcade/spc_main.htm it mentions: "As so few of the available logic elements are used, a much cheaper FPGA could be used along with external memory device(s)." So there is some hope.) Also, one important question: What is the maximum speed this XC3S200 can be clocked with? Yours, Antti.Article: 73979
Hi Peter, I've got one thing to add to Subroto's posting. The reason you don't know the exact breakdown of blocks before fitting begins is that Quartus is automatically deciding the best way to pack your memory bits into memory blocks. This is a very tricky algorithm to get right (getting good packing, not screwing up performance, etc.) and a few good friends of mine lost half a year of their life to it. But the result is that our users get the benefits of the "TriMatrix" memory in Stratix & Stratix II without having to worry about the details. That said, you can always force Quartus to use a particular RAM type if you instantiate an altsyncram directly and specify the RAM_BLOCK_TYPE primitive. I believe there is also some sort of assignment you can make in the assignment editor, but I cannot recall the details. BTW, you should not be having issues with using the 9th bit. Please send me a design example of you are finding that Quartus is not working the way you expect it to. Regards, Paul Leventis Altera Corp.Article: 73980
A quick follow-up to my previous post
> There is a tool called Design Space Explorer including in the full
> version of Quartus that automates the process of running seed sweeps (and
> farms out to multiple machines, etc). That tool will also play with
Quartus
> settings to try to achieve the best performance. For example, it will try
> Speed vs. Balanced (and other various knobs) to see what works best for
your
> design.
It turns out DSE is also in Web Edition. Just type quartus_sh --dse at the
command line, or select DSE from the GUI under Tools/Tcl Scripts..., or pick
it from the Windows Start Menu. The Web Edition does not include the
Physical Synthesis Optimizations which are one of the big hammers you (and
DSE) have to improve design performance. As an example, I did a quick run
at work on this design in Stratix II 2S15C3 device w/200 Mhz clock
constraint:
Push-button (Auto Fit, Balanced Mapping): 130.2 Mhz
Physical Synthesis Extra-Effort + Speed Mapping + Synthesis Netlist
Optimizations: 178.5 Mhz
That's a +37% using non-default options. DSE will find the right set of
options for your design, at the expense of run-time. But it sure beats
hand-optimizing for weeks when you need that extra few %!
> I'll give this one a whirl when I get into work. One possibility is
somehow
> the register packer has chosen not to pack some registers in with luts in
> the C6 case. The delays the fitter sees are different for a C6 than for a
> C8, and all optimizations are heuristics so if the inputs change, the
> outputs usually do too.
Fitter guys confirmed it. Likely causes are register packing, as well as
how we pack ALUTs into ALMs. The results of these operations can be
randomly perturbed by changes in the timing model.
> > EP1S10F484C5 Balanced 2931 90.88 MHz
> > EP2S15F484C3 Balanced 2504(?!) 126.04 MHz
>
> And I will take this opportunity to point out that Stratix II was ~39%
> faster than Stratix I on this particular compile. That's for the
naysayers
> out there who disregard our 50% average performance improvement as
marketing
> b.s. Again, to get a true comparison, we'd have to run multiple seed
sweeps
> on the base Stratix compile and the Stratix II compile.
>
> Paul Leventis
> Altera Corp.
>
>
Article: 73981> Good to know that people like it, because I'm > also "seriously buying" it! yes the board is cool, it's just incredible cheap... > Does this mean that it is impossible to fit C68000 > into XC3S200 which has only half of the system gates > of XC2S400E-7 ? > (I don't know whether the gate counts between > Spartan-IIE and Spartan-3 series compare linearly.) The simplest way to check it out is to donwload Xilins ISE software (it's free) and compile your design. You will see how it fit's and if there are some resources left. > > Same problem with many other CAST's processor cores > mentioned: 80C51, TMS32025 and "Z80 Compatible Microprocessor" > CZ80CPU, the data sheets mention only Spartan-3 XC3S400-4 and > Spartan-IIE XC2S300E-7 and some larger Virtex-II's as Example > Devices on which to implement them. > > Does this mean that XC3S200 has not enough logic > to implement ANY of these or just that CAST Inc. > didn't have XC3S200-device at hand, and thus > haven't tested their designs on it? I expect the XC3S200 should do it, since I can easily fit a 32-bit CPU in it. > Also, one important question: > What is the maximum speed this XC3S200 can > be clocked with? That depends really on your design. As above, run it through the (free) synthesizer and you will get the numbers. MartinArticle: 73982
I recommend that you read the postings on the http://verificationguild.com/ and in particular, "Cost of ABV insertion vs Traditional verification methods" http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=564 That posting had 700 views, and has useful info about assertion-based verification vs traditional methods discussed by engineers. Ben ----------------------------------------------------------------------------- Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com 3107214830@mobile.att.net for Wireless messages < 110-char Author of following textbooks: * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn 0-9705394-6-0 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------ "Hans" <hansydelm@no-spam-ntlworld.com> wrote in message news:<W8Q6d.526$DL6.418@newsfe5-win.ntli.net>... > Hi KVM, > > From my limited exposure to the language (I've just done an introduction > course), > > Pros: > 1) Very powerful formal language, or assert statement on steroid for > hardware engineers :-) > 2) Easy to learn, most of the constructs are logical. > 3) Most EDA vendors seem to support it. > 4) There are even some vendors which can translate your embedded PSL > constructs into hardware monitor. > 5) PSL can be embedded in your code (hardware engineer) or put into a > separate vunit (verification engineer). > 6) PSL is a full formal language, a subset can be used in dynamic > simulation. > > Cons: > 1) Only supported by high-end $$$ EDA tools (like Modelsim SE) which will > limit its uptake. > 2) During my PSL course I felt that I needed another language to check my > PSL. > 3) Easy to create spaghetti code (unreadable constructs). > 4) Requires a different mindset, i.e. engineer who do not use assert > statements (other than to stop the simulator) or never heard of OVL will not > use it. > 5) They created different flavoured version for VHDL and Verilog, so you can > not write generic PSL. It shouldn't be too difficult to write a translator > between the two flavours but I have seen it yet. > 6) Some EDA vendors only support the Verilog flavour > > If you want to learn language, get yourself onto a PSL course to make sure > you learn how to think in PSL, secondly get yourself a tool which can > generate VHDL from a drawn waveform, this will enable you to create simple > stimulus for your PSL assertions. Get Ben Cohen's book, > > I definitely like the language and will use it for my next design, > > Regards, > Hans. > www.ht-lab.com > > > "Kumar Vijay Mishra" <vizziee@yahoo.com> wrote in message > news:889cd7c9.0409290603.252ba577@posting.google.com... > > Hi. > > > > I would like to know the pros and cons of having Property > > Specification Language now offered with ModelSim 6.0. What is its > > future? In this respect, what is assertion-based verification (ABV)? > > And why all this now? > > > > Thanx in advance. > > > > KVM.Article: 73983
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0410010514.6fa501a@posting.google.com... > > # Xilinx benefit if MicroBlaze is in the news > > > > # Such efforts expand usage of, and research in, MicroBlaze > > > > # It can be a usefull second opinion / benchmark > > > > # Xilinx will have trademark rights to MicroBlaze, so they can > > restrict use of the name. Other examples of this are 6805 uC and i2c > > instances. > > > > # The open source core is only a tiny portion of system development: > > you also have compilers/SWdebuggers/HWDebuggers/Libraries, and all of > > those will have Xilinx license restrictions for Xilinx FPGAs. > > Actully, the compiler & I believe the debugger are open source. This > means that people are very close to having everything for free. 1) The compiler and binutils are GPL GNU stuff - that is Xilinx *must* provide the source of the those GNU tools in source code form at no charge, what they are doing, the gnu source of the tools is freely available from Xilinx. And due to the GPL licensing they can not limit the access to that source code. 2) It is not of big news yet, but the new EDK software ide is based on Open-Source Eclipse Platform as well, but Eclipse licensing is different so using Xilinx Eclipse tools is possible not free, but as Eclipse itself is free and Open-Source there are no limitations for 3rd parties to develop Eclipse based IDE for the Open-Source M*Blaze 3) uCLinux is Open-Source and free so if there is enough interest to get the OpenSource M*Blaze to be able to be used in uCLinux, then we could have truly open multi-vendor environment for FPGA+SoftCore+OS antti http://uclinux.openchip.orgArticle: 73984
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:OCl7d.329123$vG5.190330@news.chello.at... [snip] > Both devices used are the fastest speed grade available. Is the Cyclone, > although 'older', faster than the Spartan-3? As a quick aside, Cyclone has three speed grades, Spartan-3 only two. In general, a speed grade represents about a 15% difference in performance. Slowest vs. slowest speed grade would be interesting. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73985
"Michael Dales" <mwd24@thompson.cl.cam.ac.uk> wrote in message news:yqm4qleo2j7.fsf@thompson.cl.cam.ac.uk... > Hi there, > > We have a design that uses 3 MGTs, which we use 16 bits wide. To > ensure we have byte alignment properly, we set the ALIGN_COMMA_MSB to > true on the GT_CUSTOM instances. When not sending any data, we simply > send comma signals over the line. > > However, it would appear that something is wrong. When we start the > system, the MGTs seem to be aligned only to 8 bits, so 50% of the time > the data is a byte out of phase. I can see this by dumping the output > of the MGT over the serial line (as past as it copes) - for each MGT > it's either consistantly the comma value or consistantly the comma > value rotated 8 bits. small hint, just connect ChipScope the rocketio outputs and you an analyzer at no extra cost :) > To make things more confusing, when we send packets (as delimited by a > start and end packet symbol) on the MGTs that aren't aligned will > ignore/lose/drop the first packet, and then subsequently by correctly > byte aligned, and all subsequent packets get through perfectly. > > Does anyone have any suggestions to what might be causing this? Losing > the first packet really isn't tollerable, as in our system the lines > will run through a switch which will mean that the MGTs will have to > clock synchronise/detect alignment on a very regular basis, and losing > the first packet will cause problems. are you sure that MGT should be capable to correctly receive first packet after regaining lock (after loss of signal) - as soon as there ar 75 non transition data bits the lock is lost, and locking again takes time, so you need to supply some valid stream for lock-in before the first packet there are some weirdos with RocketIO, as example an open input (also in case of short circuit of the input connectors) the MGT will receive a garbage with 4 bit repeating pattern. This is not only my observation but others have seen it as well. Also if the input DC balance is not kept constantly then after a DC balanced stream starts there maybe quite a large time for the input AC coupling caps to restore DC balance, during that time either constant 0 or 1 will be received. I have used GT_CUSTOM in Serial ATA OOB testing, as much as I remember it locked and aligned ok, but there quite long repetive pattern for sync-in > In case it's of relevance, the component decleration of the GT_CUSTOM > part species the generic parameter ALIGN_COMMA_MSB as boolean, > defaulting to true, and in the instantiation this is overridden with > the value true as well. > > Cheers, > > -- > Michael Dales > University of Cambridge Computer Laboratory > http://www.cl.cam.ac.uk/~mwd24/Article: 73986
Hi Martin, > Cyclone EP1C6Q240C6: > fmax: 98 MHz, 2066 LC/Es (34% out of 5980) > Spartan-3 XC3S200-5 > fmax: 82 MHz, 2015 LC/Es (52% out of 3840) By turning on Minimize Area w/Chains under Fitter Settings/More Settings.../Auto Packed Registers - Cyclone you can cut the LE count to 1868 LEs (from 2066). Quartus doesn't try too hard to put registers & LUTs together unless it runs out of room (or you tell it to with this setting). In my compile, this didn't hurt Fmax (Fmax was 99 Mhz). On average, aggressively packing can slightly hurt performance and cause an increase in wiring. By turning on "Area" mapping option in synthesis (instead of Balanced), this drops further to 1775 LEs. Fmax = 95 Mhz. Just pointing out that without even looking at the HDL, there are ways to tweak the LE/Fmax trade-off. I'm sure there are some such tricks for Xilinx too. To automatically try-out the area optimization tricks in Quartus, run the Design Space Explorer tool, and select "Area Optimization" mode under the Advanced settings. It'll take a while, but this will find you the best settings (for area) for your design. > Both devices used are the fastest speed grade available. Is the Cyclone, > although 'older', faster than the Spartan-3? Yes. This performance result is actually pretty poor as far as Cyclone vs. Spartan-3 goes. We see an average of 80% better performance -- yes, that's 1.8X Fmax -- when comparing the fastest speed grades of the two chips with default "push-button" results from Quartus & ISE over a suite of 49 designs. Another way of looking at it is the slowest Cyclone speed-grade out-performs the fastest Spartan-3 speed-grade by a considerable margin. See http://www.altera.com/products/devices/performance/lowcost_performance/per-lowcost_performance_fpga.html for details. In this particular case, your critical path appears to stretch from a RAM to a RAM (configured as a ROM) with little logic in-between. Logic + routing-rich paths tend to accentuate the speed differences between the two devices, while RAM-heavy paths show a smaller advantage. > When we order the parts with respect to LC/E count they alternate in a > nice way. Does that mean that our design complexity determines the > choice? > Not that easy. The X parts have more memory per LC and additional > multipliers. However, I don't have prices, a very important 'feature', > handy for all these devices :-) And it also depends on which speedgrade you need to buy to meet your performance -- can you get by with a slower speed-grade in Cyclone than you'd need in Spartan-3? Or maybe with the faster Cyclone chips you may be able to get away with a wider bus (less demultiplexing) resulting in fewer LEs but a higher clock speed.. Picking a chip ain't easy... so just go with Altera ;-) Regards, Paul Leventis Altera Corp.Article: 73987
>As far as timing models go, any implication that redundancy affects quality >of timing models is pure FUD. So long as the max and min delays reflected >within the software are an upper-bound and lower-bound on the delay that can >be seen in any repaired part, then everything's cool. How much trouble do you get from customers who are right at the edge and have a design that works most of the time but is flaky on chips which happen to use the redundancy path on a critical signal? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73988
Alex Gibson wrote: > Restore ? Yep. The README that is included in the example code speaks of an explicit ``restore''. It goes on to state that merely unzipping the archive and adding the files to the project does _not_ do it. Pretty lame, if you'd ask me ;) Cheers, ChrisArticle: 73989
B. Joshua Rosen wrote: > You can put a constraint from anything to anything in the UCF file. Not quite. I had a similar problem with a high frequency clock input that is divided down inside the CPLD and the low freq clock distributed to all flipflops on a global clock net. Added a NET "<low-freq-clock-name>" BUFG = CLK; constraint to the UCF but it's appily ignored and doesn't even appear in the constraints editor (the comments, however, do appear). I am using the ``free'' tools that come with the ISE 6.2i WebPack, BTW. > You can also put period constraints on all of your clocks. Read the CGD manual. I did but that did not help too much as explained above. Cheers, ChrisArticle: 73990
Hi Hal, > How much trouble do you get from customers who are right at the edge > and have a design that works most of the time but is flaky on chips > which happen to use the redundancy path on a critical signal? None. I am responsible for timing modeling of all families from Stratix on (Stratix, Stratix II, Cyclone, Cyclone II, and Max II). I have not seen a single case of a design that has failed due to a core timing modeling bug, let alone a redundancy issue. We have seen a couple timing issues pop up in the past relating to PLL or I/O timing, usually due to our biggest nemisis... a C coding or data entry error. One way of looking at things is that the worst-case is a critical path criss-crossing back and forth over the disabled logic. This is highly unlikely. And even if this does occur, we'd still get the delay right because we analyse each routing path so that even with a worst-case location of disabled logic, we are always slightly conservative. When we correlate and compare the predictions of the Quartus timing model to silicon, we see a bias towards overpredicting delay, particularly for resources that could be affected by redundancy. And these tests are performed on silicon at the hairy edge of the binning limits, with minimum voltage and maximum temperature. Redundancy timing is a solved problem. Regards, Paul Leventis Altera Corp.Article: 73991
"Roger Planger" <ernte23@gmx.at> wrote in message news:2s5ao4F1hc430U1@uni-berlin.de... > Hello > > I have added manually the Peripherial described in the following document to > my system. > And there were really output results, so it worked quite good. > > http://direct.xilinx.com/bvdocs/appnotes/xapp529.pdf > > The next step was, that I altered the entity iDCT, so that it only performs > a simple xor operation.This was the only change! hm not sure if it would help http://xilinx.openchip.org there in file download is simplest FSL peripheral example, its working and tested, and some users have said it been useful for them, so please take a look :) anttiArticle: 73992
Antti Lukats wrote: > http://uclinux.openchip.org/forum/viewtopic.php?t=4 > > here is proof :) > > the opensource version as available from opencores is not yet good enough to > run uCLinux - well lets see if that will change, > I think there is a wish to have an open-souce multi-vendor FPGA softcare > capable to run uCLinux inside many people :) And this is what irks me...if you "need" a "free" FPGA cpu core, there are already several to choose from (www.opencores.org.) One of them even has a full GNU-tool chain. So what makes the Microblaze so special? Is it because it has some industry recognition, better performance/functionality, or is it simply because more people have already used it, and want to continue use what they're familiar with? Maybe it's because Xilinx poured in a lot of R&D into Microblaze, proved the design, and are committed to future support of it. Enough customers haved used the design that people in the industry collectively 'know' its strengths/weaknesses. Sorry I went off on a rant...I'm struggling to understand why OpenRISC 1k, despite being 'proven' for more than a year, isn't really showing up anywhere. For ASICS, the answer is obvious -- just the mask-order (for 0.18u standard cell) is $300,000USD -- big enough that no sane engineer will 'sign-off' on a free design with no proven track record. For FPGAs, well there's the Xilinx Microblaze at $500 USD (and the Altera Nios for similar cost) -- an insignificant fraction of a US engineer's salary. I suppose the upside is that old engineering saying: "copying is the highest form of flattery." :)Article: 73993
In article <HZCdnbCLRZsnmsPcRVn-uw@megapath.net>, Hal Murray <hmurray@suespammers.org> wrote: >>As far as timing models go, any implication that redundancy affects quality >>of timing models is pure FUD. So long as the max and min delays reflected >>within the software are an upper-bound and lower-bound on the delay that can >>be seen in any repaired part, then everything's cool. > >How much trouble do you get from customers who are right at the edge >and have a design that works most of the time but is flaky on chips >which happen to use the redundancy path on a critical signal? That will only be a problem if the (emm, I guess the only word thats polite is) customers rely on empirical measurements rather than the static timing analysis. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 73994
You may be convinced, but that is not the same as having facts. The simple fact that you "reconfigure tens and hundreds of times" means you take a lot of time just loading your tests into the chip before you can run them on the chip. The test methods for ASIC testing has been around for a long time, it is the details of a particular test that is unique for a given ASIC. This is not a new science, it is well understood and largely automated. Which question is meaningless and cute? I didn't ask a question. I was responding to *your* statements about total costs. I believe your point was about the silicon area not being the sole or possibly even the largest part of chip costs. Non-recurring costs can be large, but their per-unit cost depends on the volume. However, the testing and silicon per-unit costs are the same regardless of volume. So they are more important as the volume increases. Peter Alfke wrote: > > I doubt that very much. I am convinced that FPGA testing is simpler and > cheaper than ASIC testing. The secet is in the reconfigurability. We do not > just apply external test vectors. We reconfigure tens and hundreds of times, > and we have a lot of self-test engines that run in parallel inside the chip. > And we can afford to spend a lot of engineering on our generic test > methodologies, since they are amortized across >1 billion dollars in annual > sales. ASICs have to develop new test methods for each design. > > But: > What was the original question really about ? > I think it was a meaningless "cute" question. > Peter Alfke > > > From: rickman <spamgoeshere4@yahoo.com> > > Reply-To: john@bluepal.net > > Newsgroups: comp.arch.fpga > > Date: Thu, 30 Sep 2004 16:54:28 -0400 > > Subject: Re: FPGA vs ASIC area > > > > > > Another large hunk of chip cost is testing. And lets face it, testing a > > large, complex FPGA takes time on an expensive tester. An ASIC that > > would fit on an FPGA will be a lot cheaper to test. Of course Xilinx > > has that program that only tests FPGAs to the users test vectors, so I > > guess that can help limit that part of the total cost. > > > > -- > > > > Rick "rickman" Collins > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73995
Austin Lesea wrote: > > Jon, > > Peter is right: ASIC testing rarely gets more than 95% coverage. The > best is about 98% coverage. > > We can get an arbitrarily high coverage by just increasing our patterns > (99.9%+) for 0 added silicon cost. ASICs can not do that. But as Peter pointed out, silicon cost is not the only variable cost. The longer testing adds to the unit cost just as larger silicon does. > To get any better, they either have to add more logic for BIST (30%+ of > a Pentium IV is BIST logic) which increases area and cost and decreases > yield, or just be happy with the coverage of the scan chain (which is > not all that good). Nonsense. There are design techniques to measure testability to allow as high testing coverage as is required by improving the test. If there is no way to determine a fault in a node, then by definition, it won't affect the operation of the chip! Any fault that makes a difference in chip operation is observable, the only question is how to stimulate the chip to detect it. That is a well understood problem. > Each BIST or scan chain is unique, and software, test vectors, etc. muct > be developed each time anything is new or different. Yes, but that does not mean excess test development time. Much of this process is automated. > FPGAs have 0% extra area for BIST (they are 100% BIST with a different > bitstream!). No, by definition an FPGA has extra area for BIST, that is what makes it an FPGA, all the *extra* stuff in it!!! What is the area overhead for an FPGA vs. an ASIC; 10X, 20X? Even if you build an ASIC that is two generations back such as 150 nm vs. 90 nm, the ASIC will be smaller, faster and therefore cheaper. > You must understand that the 405PPC, MGT, DCM, and other "hardened IP" > are just like ASICs, so we already know everything there is to know > about ASICs, their design, and testing. In fact Xilinx the 3rd largest > 'ASIC' manufacturer in the world (behind IBM and NEC -- > Gartner/Dataquest 'ASIC/FPGA Vendor Ranking 2003'). > > FPGA vendors may be the last stronghold of full custom ASIC design left > in the world. ASIC houses are mostly standard cell, or structured > (basically same thing), with little or no full custom. > > Our customers tell us that if they want to play with the latest and > greatest technologies and designs (like 10 Gbs MGTs), they need to use > our FPGAs, because the ASIC cells are a generation behind. How is using the "latest and greatest technologies" an advantage when it comes with a 10X area premium??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73996
Austin Lesea wrote: > > Often assumptions about yield are made to justify redundancy. That is > one of the most dangerous gambles you can take, as foundries are highly > motivated to improve their yields. So if the method of redundancy is > improving yields when intrinsic yield is poor, it turns out it is > decreasing yield (because of the wasted space) when yields become good. What you say it true, but the reduction in yield in the case of good yield numbers will be very small while the improvement in yield in the case of poor yield can be significant. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73997
Followup to: <XLydneAzkfI2ccDcRVn-gQ@rogers.com> By author: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> In newsgroup: comp.arch.fpga > > BTW, you should not be having issues with using the 9th bit. Please send me > a design example of you are finding that Quartus is not working the way you > expect it to. > Will do. -hpaArticle: 73998
Hal Murray wrote: > > >That makes it much *less* useful. When a CPU is put into an FPGA, it is > >a real encumbrance to use external memory and the internal FPGA memory > >is often not large enough for program storage. Having a hunk of NV > >*rewritable* (such as flash) memory would be very useful for this sort > >of app. When are SW programs *ever* mature??? My network router > >already has a code update waiting to go into the Flash. > > But why is NV more interesting than general purpose SRAM? > > Are you looking for something big enough so that the normal > config loading mechanism can't handle the extra load? (Say > 10 times the config size.) > > My straw man to compare with would be lots more RAM on the FPGA, > using current technology. (My guess is the market isn't there > or somebody would have done it by now.) RAM would be ok, but I am assuming that NV is cheaper than RAM. But there are multiple ways that adding NV memory affects chip costs and area is just one. BTW, that brings up the issue of RAM cell size. I recall that Mosys has a 1T sram cell using a single transistor and a capacitor. This sounds like a DRAM to me. Anyone know how this works? To the best of my knowledge it does not require any refreshing or is that somehow done invisibly? They don't call this peusdo-SRAM and I believe they have some patents on it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73999
Paul Leventis (at home) wrote: > Hi Martin, > > >>Cyclone EP1C6Q240C6: >> fmax: 98 MHz, 2066 LC/Es (34% out of 5980) >>Spartan-3 XC3S200-5 >> fmax: 82 MHz, 2015 LC/Es (52% out of 3840) > <snip> > To automatically try-out the area optimization tricks in Quartus, run > the Design Space Explorer tool, and select "Area Optimization" mode under > the Advanced settings. It'll take a while, but this will find you the best > settings (for area) for your design. Can you try that, and report back the speed gain, and how long it took to find this ? ( IIRC you mentioned +37% in another post ?) <snip> > In this particular case, your critical path appears to stretch from a RAM to > a RAM (configured as a ROM) with little logic in-between. Logic + > routing-rich paths tend to accentuate the speed differences between the two > devices, while RAM-heavy paths show a smaller advantage. Do you have tips for Martin on how to improve this for Cyclone specific cases ? - ie should the ROM change to logic-based, rather than RAM based, or would a pipeline stage help ? -jg
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