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Dear all; Please tell me if I'm wrong. A typical design cycle for FPGA is to use the IEEE and Unisim libraries and their primitives (if you wish) and run the functional simulation with Modelsim and after that you go for some synthesis tool like LeonardoSpectrum or Precision RTL. Am I right? ps. I know, that in case you don't want to sue the primitives as IPs in your design, the synthesis tool will extract them automatically if you restrict yourself to some kind of standard templates. I know that I might be missing a lot. Give me directions please. Thank you.. ps. in what way can I use SIMPRIM library?Article: 72876
On Mon, 06 Sep 2004 23:50:03 +0200, "Christian E. Boehme" <boehme@os.inf.tu-dresden.de> wrote: >Hello all, > >I am making a PCI add-in card using a Xilinx Spartan II device >which provides IOB configurations for nearly all PCI signals. >The implemented agent is also supposed to generate PCI interrupts >which, electrically, are Open Drain/Open Collector outputs for >which I could not find an appropriate IOB configuration. > >Is anyone out there successfully generating PCI interrupt signals >with a Spartan II and willing to let me in on the secret IOB config ? >Am I missing something obvious here ? It's obvious, after someone tells you the solution. Open Collector (TTL terminology) / Open Drain (CMOS terminology) Has the following characteristics: Drives Low for logic low, typically for a signal that is asserted low. This allows multiple drivers on the same line, and the effect is wired OR of the asserted signal sources. Does not drive high for logic high, which for a signal that is asserted Low, means that the signal is de-asserted. Requires a pull-up resistor to establish logic high. The output buffers of the Xilinx FPGAs can be configured for tri-state control. Drive high, Drive low, and don't drive. The "don't drive" state is generated by having a logic high on the tristate control pin of the output buffer. If this signal is low, then the output is driven, and the drive level depends on the other internal signal that goes to the output driver. Physical output pin is named "O", the tri-state control is named "T", and the pin that has the signal from the guts of the chip that you want to send out is called "I". Look in the online docs at OBUFT. When am I ever going to answer you??? Now. Solution 1. Connect "I" to ground, and connect your interrupt signal to "T". The O pin will have the desired behavior. When T is high, O is tri-stated, and either some other driver pulls the line low, or the pull up resistor pulls the line high. Solution 2. Connect your interrupt signal to both I and T. The O pin will still do what you want. Note: Do not use the on-chip pull-up resistor to establish your logic high. Use an external resistor (probably in the rang 1K to 5K) for the pull-up. Why? because the on-chip pull-up has too high a resistance. >Thanks and regards, >Christian Boehme You are welcome. Philip Philip Freidin FliptronicsArticle: 72877
Thomas Rudloff <thomasREMOVE_rudloffREMOVE@gmx.net> wrote in message news:<413C9CB7.7000101@gmx.net>... > ALuPin wrote: > > >Hi VHDL folks, > > > >does somebody know if there are VHDL models available for > >USB devices ? A simple model (behavioral) would do the > >job. > > > >Any hints are appreciated. > > > >Thank you for your help. > > > >Rgds > > > > > Look at > > http://www.opencores.org/ > > Regards > Thomas Hi Thomas, there only seems to exist a Verilog core (?)Article: 72878
On Mon, 06 Sep 2004 16:20:07 -0700, S. Daniel <azdunes@cox.net> wrote: >Hello, > >I am a third year computer engineering student and have been given the >task of completing an FPGA based project utilizing a Xilinx Spartan 3 >FPGA and VHDL. It just happens to be my luck that I have limited >experience with FPGA architecture or VHDL however I do no intend to >let this stop me from achieving this projects requirements. I am >looking for experienced individuals of the FPGA development community >that would be willing to aid me as mentors or technical advisors >during the development of my project. >The project is strictly academic and unfortunately the only thing that >I can offer for any assistance is my gratitude. > >The proposed project has the following requirements: >Must utilize a Spartan 3 FPGA >Must be described using VHDL >Must provide an accurate simulation of a 1980's era Pacman machine. >Must be completed in 15 weeks. > >I have searched the net and discovered that this project has already >been done by several clever individuals, however simply imitating >their efforts will not further my education and I fear that using >source code that has been produced by one group of individuals may >limit my view on coding/design options. > >Please contact me if you feel that you can provide any assistance. >Any assistance will be greatly appreciated. On Tue, 07 Sep 2004 00:22:13 GMT, Phil Hays <Spampostmaster@comcast.net> wrote: >Generally this is a bad place to ask for help with homework questions. Which I think is a bit harsh, as S. Daniel does seem to indicate that he/she wants to further their education. So this is not our typical lazy homework hunter. >But here are some hints. Which are all pretty good, except maybe the following: >Keep at it. We should not hear from you for the next 15 weeks. I think better guidance is that if you come to this news group looking for a solution on a plate, you will get ridiculed pretty strongly. On the other hand, if you demonstrate you have thought about the problem, have some tentative solutions, and would like some guidance in better focussing on the trade offs, then we tend to be a pretty helful bunch. Here's my thoughts on the requirements: >The proposed project has the following requirements: >Must utilize a Spartan 3 FPGA Order the Xilinx $99 eval board right away, so you have something to play with. >Must be described using VHDL Get a book or two and start reading. I learn't VHDL from "A VHDL synthesis Primer" by J. Bhasker: ISBN 0-9650391-9-6 and "A VHDL Primer" by J. Bhasker: ISBN 0-13-096575-8 which didn't kill me. And I found HDL Chip Design by Douglas J. Smith: ISBN 0-965-1934-3-8 has lots of examples, and comparison to Verilog >Must provide an accurate simulation of a 1980's era Pacman machine. The issue of "how" accurate is going to affect all other decisions. If the screen has to look just like ANSI standard xxxyyyzzz Pacman, and the behavior has to be exact, then about the only way to do this is to run the Pacman program on hardware that emulates every function that the program tries to use. An example of a software only solution to this problem is the MAME project, that actually emulates the CPU, and all peripherals, and runs copies of the original Pacman ROMs (as well as hundreds of other 1970s, 80's and 90's arcade games). Note that the use of these ROM images is a copyright violation in almost all circumstances (Unless you have a physical original pacman machine, and you are using the ROMs from that machine). If accurate means Pacmanesque, and it just needs to look a bit like Pacman, and have a chompy character, and wiggly skirt monsters, and the occasional flying cherry, then there is a bit more room to move. Regardless, this all implies you need to design and build a CPU, a color video controller, a way to load and test programs running on your CPU, a way to write programs for your CPU, some button inputs, and since sound is part of the game, there is that too. >Must be completed in 15 weeks. You won't be getting any sleep. Maybe before you jump off this cliff you might want to ask you lecturer for an existence proof that this can be done in this amount of time by someone without prior FPGA and VHDL experience. Plus you probably have other subjects running concurrently, which you probably don't want to fail. The Spartan-3 on Xilinx's $99 eval board may not be big enough. I would suggest something that might be somewhat lighter, but still have some good educational experience: Design a CPU with an instruction set that is not identical to any existing CPU, 16 or 32 bit. Port LCC to your CPU. Compile and run a hello world, and prime number program for your CPU. All the best, Philip Philip Freidin FliptronicsArticle: 72879
Hi *, does anyone have any experience with DDR2 SDRAM-controllers in a Virtex2Pro? There's of course a bunch of ready-to-use controllers for DDR1 SDRAM, but for DDR2 it only says in Xilinx' "Memory Corner" that "The Virtex-II Pro built-in capabilities enable DDR2 SDRAM interfacing at data rates of 533 Mbps." But there's no examples, and in the usual xapps concerning DDR SDRAM DDR2 is not even mentioned. Has anyone tried this so far? Any pointers, hints, suggestions, caveats? Theoretically, not much changed from DDR1 -> DDR2, but I bet there's a bunch of problems I'm not seeing... cu, SeanArticle: 72880
hello friends, I am doing project in college. i want to know how to get the digital data from the ADC and store in the fpga Ram (say spartan II). pls give me some suggestions. actually, the design connected with the analog part. the analog part end will have ADC. how to get the data from the ADC.. regards senthil.RArticle: 72881
Hi, all, How to purposely make pipelining in Handel-C? Say, I need to read in a lot of 64-bit numbers using Celoxica's DSM (Data Stream Manager). Since DsmWord is 32-bit in length, two DsmRead and one assignment are needed. Can I pipeline these two DsmRead and the assignment statement? Hopefully, I can just maintain 4 32-bit variables (temp1 to temp4) for DsmRead. When I concatenate temp1 and temp2 and assign the value to a 64-bit variable v1, I can read in 2 DsmWords to temp3 and temp4. Then, while do concatenation on temp3 and temp4 to assign to v2, I can read into temp1 and temp2, and will concatenate them to v3 in the next clock cycle. To achieve the above, how to write the handel-C code? By the way, is there any means to directly assign a 32-bit value read from DSM to a portion of a 64-bit variable? Thanks a lot! Best regards, PeggyArticle: 72882
I'm new to VHDL and I want to learn as with examples.
I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie
A,B signals).
Can someone help me how to create following functionality in VHDL ?
Inputs are
(1,2) A, B = A,B quadrature signals (from encoder)
( 3) IDX = Index (from encoder)
( 4) RST = Reset (Low->Reset counter)
( 5) S/P = Serial/Parallel output select (High->Serial output,
Low->Parallel output)
(6,7) A1,A0 = Output byte selector A1,A0
([A1,A0] --> [0,0] ->Counter byte0 output,
[0,1]->Counter byte1, [1,0]->Counter byte 2, [1,1]->Counter byte3)
( 8) OE = Output Enable (Low->Enabled, High ->High state output)
( 9) SCLK = Serial out clock (If S/P is high (ie serial out selected)
then Low to High transition output one bit of the counter value starting
from LSB to MSB)
Outputs are
(1,2,3,4,5,6,7,8) D0..D7 = Counter value output (A1,A0 selects which
byte will be output)
(1) = Serial output (if serial output selected on S/P )
Article: 72883Patrick Harold wrote: > I'm new to VHDL and I want to learn as with examples. > I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie > A,B signals). > Can someone help me how to create following functionality in VHDL ? > > Inputs are > (1,2) A, B = A,B quadrature signals (from encoder) > ( 3) IDX = Index (from encoder) > ( 4) RST = Reset (Low->Reset counter) > ( 5) S/P = Serial/Parallel output select (High->Serial output, > Low->Parallel output) > (6,7) A1,A0 = Output byte selector A1,A0 > ([A1,A0] --> [0,0] ->Counter byte0 output, > [0,1]->Counter byte1, [1,0]->Counter byte 2, [1,1]->Counter byte3) > ( 8) OE = Output Enable (Low->Enabled, High ->High state output) > ( 9) SCLK = Serial out clock (If S/P is high (ie serial out selected) > then Low to High transition output one bit of the counter value starting > from LSB to MSB) > > Outputs are > (1,2,3,4,5,6,7,8) D0..D7 = Counter value output (A1,A0 selects which > byte will be output) > (1) = Serial output (if serial output selected on S/P ) > > Taking a VHDL class are we?Article: 72884
<Patrick Harold> wrote in message news:413db1b1$0$19870$afc38c87@news.optusnet.com.au... > I'm new to VHDL and I want to learn as with examples. > I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie > A,B signals). > Can someone help me how to create following functionality in VHDL ? > > Inputs are > (1,2) A, B = A,B quadrature signals (from encoder) > ( 3) IDX = Index (from encoder) > ( 4) RST = Reset (Low->Reset counter) > ( 5) S/P = Serial/Parallel output select (High->Serial output, > Low->Parallel output) > (6,7) A1,A0 = Output byte selector A1,A0 > ([A1,A0] --> [0,0] ->Counter byte0 output, > [0,1]->Counter byte1, [1,0]->Counter byte 2, [1,1]->Counter byte3) > ( 8) OE = Output Enable (Low->Enabled, High ->High state output) > ( 9) SCLK = Serial out clock (If S/P is high (ie serial out selected) > then Low to High transition output one bit of the counter value starting > from LSB to MSB) > > Outputs are > (1,2,3,4,5,6,7,8) D0..D7 = Counter value output (A1,A0 selects which > byte will be output) > (1) = Serial output (if serial output selected on S/P ) > You may also need an input to "freeze" the count before you read it. In other words a register to save all bytes of the present count, while allowing the counter to continue. However, I did one design that automatically latched all bytes when reading the Least Significant byte leaving you free to read the other bytes at will. Sorry I can't help with the VHDL, I've done the same design many times using Schematic and/or vendor specific generated macros. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email)Article: 72885
Patrick Harold wrote: > I'm new to VHDL and I want to learn as with examples. > I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie > A,B signals). > Can someone help me how to create following functionality in VHDL ? > > Take a google for Opencores. They've got an example there. Examine it closely, or you'll learn nothing from it. Paul BurkeArticle: 72886
To get the data from the ADC, read the data sheet on the ADC available from the manufacturer's website which includes the signal states and transitions needed to get a value. Connect these signals to the FPGA in a way that you reproduce those signals. To get the data into the BlockRAM, read the description of the BlockRAM's operation and the signal states and transitions needed to write that data in the Libraries Guide in the Xilinx Software manuals ( http://www.xilinx.com/support/software_manuals.htm ). Apply those signals in your FPGA. "senthil" <bhuvasen@hotmail.com> wrote in message news:3045a319.0409070139.1fc9f3a4@posting.google.com... > hello friends, > > I am doing project in college. i want to know how to get the digital > data from the ADC and store in the fpga Ram (say spartan II). pls give > me some suggestions. > actually, the design connected with the analog part. the analog part > end will have ADC. how to get the data from the ADC.. > > regards > > senthil.RArticle: 72887
bhuvasen@hotmail.com (senthil) wrote in message news:<3045a319.0409070139.1fc9f3a4@posting.google.com>... > hello friends, > > I am doing project in college. i want to know how to get the digital > data from the ADC and store in the fpga Ram (say spartan II). pls give > me some suggestions. > actually, the design connected with the analog part. the analog part > end will have ADC. how to get the data from the ADC.. > > regards > > senthil.R Hi, Obviously no one is going to do your homework for you. Anyway, this is a basic suggestion for proceeding : - First select an ADC, either serial (often SPI) or parallel access, depending on your requirements in terms of precision etc.. - Study the possible interfaces -- Serial is less consuming in terms of pins, but more difficult to develop in VHDL, since you will have to control serial clock, chip select and serial data in/out ; and serialize/deserialize the data for storage into the FPGA memory. You will find a lot of serial ADC's. -- Parallel is easier to describe in VHDL, but needs more interface lines Once you made up your mind, carefully study the selected interface (SPI for instance or parallel). Also study the interface to the synchronous dual port rams. Then devise a state machine that shall do the work . You of course need a clock to control your state machines. I hope this can help a bit. NOTE: an experienced VHDL programmer would require something like between two hours and six hours to do the job, assuming a good knowledge of the Spartan II, of the SPI bus and state machines. So, do not expect to make your homework in just a few days, because you start from scratch.Article: 72888
On Tue, 07 Sep 2004 07:03:44 -0700, Patrick Harold wrote: > I'm new to VHDL and I want to learn as with examples. I want to build a > 16,24 or 32 bit counter for quadrature encoder signals (ie A,B signals). > Can someone help me how to create following functionality in VHDL ? > > Inputs are > (1,2) A, B = A,B quadrature signals (from encoder) ( 3) IDX = > Index (from encoder) > ( 4) RST = Reset (Low->Reset counter) ( 5) S/P = > Serial/Parallel output select (High->Serial output, > Low->Parallel output) > (6,7) A1,A0 = Output byte selector A1,A0 > ([A1,A0] --> [0,0] ->Counter byte0 output, > [0,1]->Counter byte1, [1,0]->Counter byte 2, [1,1]->Counter byte3) > ( 8) OE = Output Enable (Low->Enabled, High ->High state output) ( > 9) SCLK = Serial out clock (If S/P is high (ie serial out selected) > then Low to High transition output one bit of the counter value > starting from LSB to MSB) > > Outputs are > (1,2,3,4,5,6,7,8) D0..D7 = Counter value output (A1,A0 selects which > byte will be output) > (1) = Serial output (if serial output selected on S/P ) One thing you might consider is to use a smaller counter that is automatically cleared when read. The count thats read (delta) can then be added to a software maintained count of any size. This is often faster on systems with slow I/O but fast CPUs (micros with SPI or PCs for example) I have an example of a dual 12 bit quadrature counter that will fit in a XC95C72Xl CPLD (~2.00) that uses this delta counter design. Too big to post here but I can email it if you are interested. Peter WallaceArticle: 72889
On Tue, 7 Sep 2004 23:03:44 +1000, <Patrick Harold> wrote: >Can someone help me how to create following functionality in VHDL ? I imagine if you'd ask a more specific question regarding some attempt you've made in VHDL, you might get some better help. Or do you have no idea at all where to start? JonArticle: 72890
Hi,
I'm writing this newsgroup because i'm facing a stange problem while
simulating a ppc system for V2PRO generated with EDK 3.2.
Indeed, the PPC doesn't start correctly.
I've generated a behavioural simulation model with EDK wich I'm including
in a top level and then in a bench, all of them in VHDL.
modelsim seems to load correctly the swift model and the simulation starts
correctly.
After reset with a proc_sys_reset instance, the ppc model issues the
correct adress to the i-ocm at boot (FFFFFFFC translated to the iocm
adress). The ocm returns an opcode and the ppc stalls, the adress doesn't
change and the instruction doesn't seem to be executed.
What kind of problem could it be ?
Did I forget something in my system.mhs file ?
I've started from a generated one which I modified by hand. The original
had a system_dcm which I suppressed because I had trouble to simulate it.
Did I forget something ?
Thanks a lot for your help
Note : i'm using modelsim on a sun workstation
For your info, here is the system.mhs ....
# #############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.2 Build EDK_Gm.11
# Modified by hand
# Target Board: Avnet Avnet Virtex-II Pro Development Board Rev 1.0
# Family: virtex2p
# Device: XC2VP7
# Package: FF896
# Speed Grade: -5
# Processor: PPC 405
# Processor clock frequency: 100 MHz
# Bus clock frequency: 100 MHz
# Debug interface: No Debug
PARAMETER VERSION = 2.1.0
PORT RS232_TX = RS232_TX, DIR = O
PORT RS232_RX = RS232_RX, DIR = I
PORT SDRAM_RASn = SDRAM_RASn, DIR = O
PORT SDRAM_DQ = SDRAM_DQ, VEC = [0:31], DIR = IO
PORT SDRAM_Clk = SDRAM_Clk, DIR = O
PORT SDRAM_CSn = SDRAM_CSn, DIR = O
PORT SDRAM_CASn = SDRAM_CASn, DIR = O
PORT SDRAM_BankAddr = SDRAM_BankAddr, VEC = [0:1], DIR = O
PORT SDRAM_Addr = SDRAM_Addr, VEC = [0:11], DIR = O
PORT SDRAM_DQM = SDRAM_DQM, VEC = [0:3], DIR = O
PORT SDRAM_WEn = SDRAM_WEn, DIR = O
PORT SDRAM_CKE = SDRAM_CKE, DIR = O
PORT SRAM_A = SRAM_A, VEC = [0:31], DIR = O
PORT SRAM_DQ = SRAM_DQ, VEC = [0:31], DIR = IO
PORT SRAM_CEN = SRAM_CEN, VEC = [0:1], DIR = O
PORT SRAM_OEN = SRAM_OEN, VEC = [0:1], DIR = O
PORT SRAM_WEN = SRAM_WEN, DIR = O
PORT SRAM_QWEN = SRAM_QWEN, VEC = [0:3], DIR = O
PORT SRAM_BEN = SRAM_BEN, VEC = [0:3], DIR = O
PORT SRAM_RPN = SRAM_RPN, DIR = O
PORT SRAM_CE = SRAM_CE, VEC = [0:1], DIR = O
PORT SRAM_ADV_LDN = SRAM_ADV_LDN, DIR = O
PORT SRAM_LBON = SRAM_LBON, DIR = O
PORT SRAM_CKEN = SRAM_CKEN, DIR = O
PORT SRAM_RNW = SRAM_RNW, DIR = O
PORT sys_irq = sys_irq, VEC = [0:0], DIR = I, LEVEL=HIGH, SIGIS = INTERRUPT
PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK
PORT sys_rst = sys_rst_s, DIR = IN
PORT SDRAM_Clk_in = SDRAM_Clk_in, DIR = IN
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE DPLB = plb
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DSOCM = docm
BUS_INTERFACE ISOCM = iocm
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT CPMC405JTAGCLKEN = net_vcc
PORT MCPPCRST = net_vcc
PORT BRAMDSOCMCLK = sys_clk_s
PORT CPMC405CPUCLKEN = net_vcc
PORT PLBCLK = sys_clk_s
PORT EICC405EXTINPUTIRQ = opb_intc_0_irq
PORT EICC405CRITINPUTIRQ = net_gnd
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT CPMC405TIMERCLKEN = net_vcc
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CORECLKINACTIVE = net_gnd
PORT CPMC405TIMERTICK = net_vcc
PORT BRAMISOCMCLK = sys_clk_s
PORT CPMC405CLOCK = sys_clk_s
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Bus_Struct_Reset = sys_bus_reset
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT Dcm_locked = net_vcc
END
BEGIN isocm_v10
PARAMETER INSTANCE = iocm
PARAMETER HW_VER = 1.00.b
PARAMETER C_ISCNTLVALUE = 0x85
PORT sys_rst = sys_bus_reset
PORT ISOCM_Clk = sys_clk_s
END
BEGIN isbram_if_cntlr
PARAMETER INSTANCE = iocm_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xfffff000
PARAMETER C_HIGHADDR = 0xffffffff
BUS_INTERFACE DCR_WRITE_PORT = isocm_porta
BUS_INTERFACE INSTRN_READ_PORT = isocm_portb
BUS_INTERFACE ISOCM = iocm
END
BEGIN bram_block
PARAMETER INSTANCE = isocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = isocm_porta
BUS_INTERFACE PORTB = isocm_portb
END
BEGIN dsocm_v10
PARAMETER INSTANCE = docm
PARAMETER HW_VER = 1.00.b
PARAMETER C_DSCNTLVALUE = 0x85
PORT DSOCM_Clk = sys_clk_s
PORT sys_rst = sys_bus_reset
END
BEGIN dsbram_if_cntlr
PARAMETER INSTANCE = docm_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xffff0000
PARAMETER C_HIGHADDR = 0xffff1fff
BUS_INTERFACE PORTA = dsocm_porta
BUS_INTERFACE DSOCM = docm
END
BEGIN bram_block
PARAMETER INSTANCE = dsocm_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = dsocm_porta
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 1
PORT OPB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.00.b
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_ADDR_RNG = 2
PARAMETER C_RNG0_BASEADDR = 0x00000000
PARAMETER C_RNG0_HIGHADDR = 0x1fffffff
PARAMETER C_RNG1_BASEADDR = 0x20000000
PARAMETER C_RNG1_HIGHADDR = 0x2000ffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
PORT OPB_Clk = sys_clk_s
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x20000000
PARAMETER C_HIGHADDR = 0x200000ff
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 66000000
BUS_INTERFACE SOPB = opb
PORT TX = RS232_TX
PORT OPB_Clk = sys_clk_s
PORT RX = RS232_RX
END
BEGIN opb_sdram
PARAMETER INSTANCE = opb_sdram_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x10000000
PARAMETER C_HIGHADDR = 0x11ffffff
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
PARAMETER C_SDRAM_TMRD = 2
PARAMETER C_SDRAM_TCCD = 1
PARAMETER C_SDRAM_TRAS = 50000
PARAMETER C_SDRAM_TRC = 100000
PARAMETER C_SDRAM_TRFC = 100000
PARAMETER C_SDRAM_TRCD = 20000
PARAMETER C_SDRAM_TRRD = 20000
PARAMETER C_SDRAM_TRP = 20000
PARAMETER C_SDRAM_TREF = 64
PARAMETER C_SDRAM_CAS_LAT = 2
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_SDRAM_AWIDTH = 12
PARAMETER C_SDRAM_DWIDTH = 32
PARAMETER C_OPB_CLK_PERIOD_PS = 15000
BUS_INTERFACE SOPB = opb
PORT SDRAM_RASn = SDRAM_RASn
PORT SDRAM_DQ = SDRAM_DQ
PORT SDRAM_Clk = SDRAM_Clk
PORT SDRAM_CSn = SDRAM_CSn
PORT SDRAM_CLK_in = sys_clk_s
PORT SDRAM_CASn = SDRAM_CASn
PORT SDRAM_BankAddr = SDRAM_BankAddr
PORT SDRAM_Addr = SDRAM_Addr
PORT SDRAM_DQM = SDRAM_DQM
PORT OPB_Clk = sys_clk_s
PORT SDRAM_WEn = SDRAM_WEn
PORT SDRAM_CKE = SDRAM_CKE
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.a
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0x30010000
PARAMETER c_highaddr = 0x30013fff
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
BUS_INTERFACE SPLB = plb
PORT PLB_Clk = sys_clk_s
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN opb_emc
PARAMETER INSTANCE = opb_emc_0
PARAMETER HW_VER = 1.10.b
PARAMETER C_OPB_CLK_PERIOD_PS = 15000
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x000001ff
PARAMETER C_NUM_BANKS_MEM = 2
PARAMETER C_MEM0_BASEADDR = 0x00100000
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_SYNCH_PIPEDELAY_0 = 2
PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000
PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000
PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000
PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000
PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000
PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000
PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000
PARAMETER C_SYNCH_MEM_1 = 0
PARAMETER C_SYNCH_PIPEDELAY_1 = 2
PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 150000
PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 55000
PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 70000
PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 155000
PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 55000
PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 15000
PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 35000
BUS_INTERFACE SOPB = opb
PORT Mem_A = SRAM_A
PORT Mem_DQ = SRAM_DQ
PORT Mem_CEN = SRAM_CEN
PORT Mem_OEN = SRAM_OEN
PORT Mem_WEN = SRAM_WEN
PORT Mem_QWEN = SRAM_QWEN
PORT Mem_BEN = SRAM_BEN
PORT Mem_RPN = SRAM_RPN
PORT Mem_CE = SRAM_CE
PORT Mem_ADV_LDN = SRAM_ADV_LDN
PORT Mem_LBON = SRAM_LBON
PORT Mem_CKEN = SRAM_CKEN
PORT Mem_RNW = SRAM_RNW
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x03000000
PARAMETER C_HIGHADDR = 0x030000ff
BUS_INTERFACE SOPB = opb
PORT Intr = sys_irq
PORT Irq = opb_intc_0_irq
END
Article: 72891"colin" <colin_toogood@yahoo.com> wrote in message news:885a4a4a.0409030335.2914c7ea@posting.google.com... > Hi all > > I am interfacing a spartan 3 to a device that happens to use PCI. As > the two devices will be about an inch apart with a point to point bus > I'm curious about the right buffer to instantiate, particularly as > bandwith calculations suggest that I need to run this bus at about > 50MHz and the datasheet says that only pci_3v_33 exists in the IOB > when pci_3v_66 exists for virtex 2. > > Presumably on a standard PCI card the requirements for clock, req and > the other few point to point signals also aren't electrically PCI. In > particular clock is almost certainly provided by a standard LVCMOS > clock driver so what IOB settings to people use? > > Thanks in advance for any suggestions. > The Spartan-3 family is fully compliant with the 33 MHz PCI specifications for both 32-bit and 64-bit busses. The PCI core for Spartan-3 is available from the Xilinx web site. The associated reference design targets the XC3S1000-4FG456C FPGA although the design can be adapted to other part/package combinations. Xilinx Real-PCI Web Site http://www.xilinx.com/products/design_resources/conn_central/grouping/pci.htm Although Spartan-3 FPGAs easily perform at 66 MHz clock rates and beyond in most applications, Spartan-3 FPGAs do not meet _all_ the electrical and timing requirements of the 66 MHz PCI specification. The PCI specification defines a specific timing budget for 66 MHz operation over a PCI backplane loaded with other PCI-compliant cards. In open systems, full compliance with the PCI specification is required to ensure interoperability. However, in embedded designs, it is possible to create custom PCI timing budgets. Custom timing budgets enable system designers to reduce cost by using less expensive FPGA devices like the Spartan-3 family. For Spartan-3, a 66 MHz PCI implementation is possible simply by "borrowing" from one timing parameter to meet another. For example, PCI is a common chip-to-chip communications protocol. If the two PCI end points are co-located on the same board, the design does not need to account for signal propagation over the backplane and through the PCI connectors. A reasonable board layout can reduce the board propagation delay from the allotted 5 ns to an actual value of 2 ns or less, in order to meet the Spartan-3 FPGA setup time requirement. The system designer would need to verify that their custom timing budget meets all the requirements of his or her embedded application. I have a separate document that I will send you that includes all the relevant PCI 3.0 timing and which parameters that you can ignore if you're on the same PC board. In summary, you likely can use the Spartan-3 33 MHz PCI design at 50 MHz if you're not traversing bus sockets, etc. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72892
Hello!, The book you are reading is the best of the best in that topic. The question about pros and cons is a hot question til now. You'll find people that will like more PDSPs than FPGAs. To me there are a couple things to take in consideration. 1.- Paralellism. If your algorithm is such that you can divide it in small parts to execute it in parallel, them FPGA is great. 2.- Custom precision. If you need to work with an specific number of bits, say 17 (whatever), then is better to implement it on FPGA than a PDSP since you won't find one with the precision you want. 3.- However, if you don't need that much speed, or an special requirement on precision, then use PDSP, it's easier and probably cheaper. In general, I'll use FPGA when my application is very demanding in terms of speed and customization. If not, it is probably cheaper and easier to use a PDSP. hope it helps, alnz. "Orbit" <orbit@dunno.net> wrote in message news:<muqdnUbIbuMmhKbcRVn-oA@giganews.com>... > Hi, > > I am reading Uwe Meter-Baese's book "DSP with FPGAs" and am trying to gain > some perspective here. FWIW, I develop embedded apps on the Atmel 8 bit AVR > platform with CodeVision C compiler. > > What are the pros and cons of going PDSPs vs. FPGAs to implement DSP for my > 8 bit apps? > > This book favors Altera and VHDL ( which I don't even know) > > Help me out here...Article: 72893
So, BaseX has arrived, but it won't install on Fedora core 2: [root@atlantis cdrom]# ./setup /mnt/cdrom/xilsetup: relocation error: /mnt/cdrom/bin/lin/libwinsock44.so: symbol h_errno, version GLIBC_2.0 not defined in file libc.so.6 with link time reference so after a bit of googling, I tried the LD_ASSUME_KERNEL=2.4.1 trick, and got: [root@atlantis cdrom]# setenv LD_ASSUME_KERNEL 2.4.1 [root@atlantis cdrom]# ./setup Wind/U Error (294): Unable to install Wind/U ini file (/mnt/cdrom/data/WindU). See the Wind/U manual for more details on the ".WindU" file and the "WINDU" environment variable. Wind/U X-toolkit Error: wuDisplay: Can't open display This was a bit of a puzzle because I was running it from a terminal window on a Gnome desktop. Just to check I did: [root@atlantis /]# echo $DISPLAY :0.0 So nothing wrong there. I decided I'd post a plea for help on news, switched to my mac (I use a mac for mail & news so I don't have to care about virii or outlook worms etc.), ssh'd into the linux box and ran the program, so I could cut'n'paste the errors. The damn thing worked. Up comes the Xilinx install screen, although it didn't manage to call up the web-browser for online registration it *did* run. I stopped it, and typed: [root@atlantis ~]# echo $DISPLAY localhost:10.0 (which is the standard ssh route-X-protocol DISPLAY variable). So was there something wrong with :0.0 on its' own ? Apparently so, because if you do: [root@atlantis /]# setenv DISPLAY :0 [root@atlantis /]# /mnt/cdrom/setup ... it works just fine and dandy, so I now have BaseX installed and (apparently, I haven't fully tested it yet) working on a fedora core 2 box. Hopefully the above will allow others to more-easily install it... The DISPLAY variable *cannot* be the default value ":0.0", it *must* be either a "hostname:x.y" or ":0" SimonArticle: 72894
sd wrote: > > Hello, > > I am a third year computer engineering student and have been given the > task of completing an FPGA based project utilizing a Xilinx Spartan 3 > FPGA and VHDL. It just happens to be my luck that I have limited > experience with FPGA architecture or VHDL however I do no intend to > let this stop me from achieving this projects requirements. I am > looking for experienced individuals of the FPGA development community > that would be willing to aid me as mentors or technical advisors > during the development of my project. > The project is strictly academic and unfortunately the only thing that > I can offer for any assistance is my gratitude. > > The proposed project has the following requirements: > Must utilize a Spartan 3 FPGA > Must be described using VHDL > Must provide an accurate simulation of a 1980's era Pacman machine. > Must be completed in 15 weeks. > > I have searched the net and discovered that this project has already > been done by several clever individuals, however simply imitating > their efforts will not further my education and I fear that using > source code that has been produced by one group of individuals may > limit my view on coding/design options. > > Please contact me if you feel that you can provide any assistance. > Any assistance will be greatly appreciated. You state four requirements. The first requirement is more of a hardware issue than anything else. You don't say if you have to build the hardware or if you can use or may even already have a prototyping board with a Spartan 3 on it. I assume you can buy or have available a suitable prototyping board. The second requirement simply means that you need to learn VHDL. I have found that learning an HDL involves two parts. The first is learning the language itself, which is not really similar to learning a programming language. The second is learning to design hardware in effective ways using the language. Both of these would be much easier in a VHDL class. Are you taking a VHDL class? If not, I suggest that you find some tutorials and start learning. Practice with small examples and work your way up to a larger project like this one. Also, try not to get too complicated with the features that you use. You will do much better to use the straight forward features and leave the more complex ones for later, after you have completed your project. The third requirement is the one you need to deal with first. I suggest that you create a written description of everything the Pacman game does in a heirarchical document. You will use this as a template for designing your machine. The clearer this document is written, the easier it will be to design the machine. Next you should translate this description of the machine to a design of registers and logic. This can be done in an informal manner. Translating this to VHDL will create the formal version of the hardware. The fourth requirement will dictate how much of the design you will actually be able to complete. I suggest that you plan your design efforts to get some functionality working initially and add details as you procede. This will provide for a partly working version if you don't complete the design by the end of the 15 weeks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72895
I got a mail that SP1 of the Quartus2 V4.1 was available for download. After a few unsuccesfull login attempts, partly due to the overloaded server partly due to me not knowing the login parameters, my motivation to download the 120MB or so vanished. Anyone knows whether the paying users get this update on CD mailed home ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 72896
ajholme@hotmail.com (Andrew Holme) wrote > under Assignments (menu) / Device (menu > option) / Device & pin options (button) / Unused pins (tab) - I am > concerned that "reserve all unused pins" is set to "as outputs that > drive an unspecified signal" which seems to be the defualt. Does this > setting get overridden? More info: Clicking OK on the "unused pins" tab adds a set_global_assignment -name reserve_all_unused_pins command to the "fitter assignments" section of the .QSF file. This assignment was not there before. After recompiling, the unused pins were listed as RESERVED. The only way I've found to get the project options back to their original state is to delete the set_global_assignment command using Notepad. Is there a way to do it using the GUI? The default fitter behaviour (i.e. GND*) and the default setting displayed by the GUI (output driving an unspecified signal) are inconsistent when the global assignment does not exist.Article: 72897
"jamie" <jamie@noway.com> wrote in message news:vSi%c.11928$lP4.871282@news20.bellglobal.com... > Patrick Harold wrote: > > I'm new to VHDL and I want to learn as with examples. > > I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie > > A,B signals). > > Can someone help me how to create following functionality in VHDL ? <snip> > > > > Taking a VHDL class are we? What difference does it make if he is taking a VHDL class and needs help. He seems honest, and forthcoming. "I'm new to VHDL...." etc. Bro, if I knew VHDL I would personally help you, but last time i saw VHDL was in college about 11 years ago. Yall should help the guy, ESPECIALLY if he is a student.Article: 72898
Hi, -> how to get the data from the ADC <- This depends on what type of adc(serial, parallel, ....) are you using. The best thing is go through the datasheet of adc that you are going to use. Regards pablo ---------------- bhuvasen@hotmail.com (senthil) wrote in message news:<3045a319.0409070139.1fc9f3a4@posting.google.com>... > hello friends, > > I am doing project in college. i want to know how to get the digital > data from the ADC and store in the fpga Ram (say spartan II). pls give > me some suggestions. > actually, the design connected with the analog part. the analog part > end will have ADC. how to get the data from the ADC.. > > regards > > senthil.RArticle: 72899
Mukesh, Try running 'clean up project files' from ISE then delete any .XML files that may be remaining in that project directory. The .XML file contains toggle and frequency data and can conflict with the VCD simulation file if they don't happen to target the same device. (For example, you target a Spartan-IIe then save the settings file and then retarget to Virtex-II and accidentally load the .XML file for the Spartan-IIe design) If that doesn't help, send the design into Xilinx for analysis. They can take a look at it and let you know what the problem is. Regards, Arthur
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