Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I would like to make a simple PCI device. I already own an FPGA evaluation board and I also own a blank PCI prototyping card. I was planning on connecting the FPGA board to the PCI prototyping card via ribbon cables. Would this cause problems with noise? Would it help if I kept the ribbon cables quite short. Thanks for any info,Article: 72851
"Ted" <ted@ted.com> wrote in message news:chf9eq$frj$1@newsg2.svr.pol.co.uk... > Hi, > > I would like to make a simple PCI device. I already own an FPGA evaluation > board and I also own a blank PCI prototyping card. I was planning on > connecting the FPGA board to the PCI prototyping card via ribbon cables. > Would this cause problems with noise? Would it help if I kept the ribbon > cables quite short. They'd have to be very short. 8-) LeonArticle: 72852
Ted wrote: > I would like to make a simple PCI device. I already own an FPGA evaluation > board and I also own a blank PCI prototyping card. I was planning on > connecting the FPGA board to the PCI prototyping card via ribbon cables. > Would this cause problems with noise? Well, what's noise ;-) There's more to the PCI signaling environment than you may be aware of. I strongly suggest obtaining the PCI spec or if that isn't feasible this one may be of considerable (but not complete) help: http://www.aw-bc.com/catalog/academic/product/0,1144,0201309742,00.html Cheers, ChrisArticle: 72853
generous coupling to ground with frequency matched capacitors will help you lengthen signal lines without noise degradation.Article: 72854
"Orbit" <orbit@dunno.net> wrote in message news:ANydnUUxBYdvzabcRVn-tw@giganews.com... > generous coupling to ground with frequency matched capacitors will help you > lengthen signal lines without noise degradation. The lengths of the lines from the PCI bus connector are critical, and are quite short. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 72855
"Orbit" <orbit@dunno.net> wrote in message news:ANydnUUxBYdvzabcRVn-tw@giganews.com... > generous coupling to ground with frequency matched capacitors will help you > lengthen signal lines without noise degradation. ??? Please enlighten us. BobArticle: 72856
I had a silimar problem in a different area (DDS's and A/D converters). The only solution was to throw away the ribbon and make a small pc board that interconnects the two eval boards, using a group plane beneth signal trance wires, and the approapriate connectors "Ted" <ted@ted.com> wrote in message news:chf9eq$frj$1@newsg2.svr.pol.co.uk... > Hi, > > I would like to make a simple PCI device. I already own an FPGA > evaluation > board and I also own a blank PCI prototyping card. I was planning on > connecting the FPGA board to the PCI prototyping card via ribbon cables. > Would this cause problems with noise? Would it help if I kept the ribbon > cables quite short. > > Thanks for any info, > >Article: 72857
"Ted Lechman" <eastwood132@yahoo.com> wrote in message news:CaednQ1g-ZMpPqbcRVn-hw@adelphia.com... >I had a silimar problem in a different area (DDS's and A/D converters). The >only solution was to throw away the ribbon and make a small pc board that >interconnects the two eval boards, using a group plane I meant "ground plane" beneath the signal trace lines beneth signal trance > wires, and the approapriate connectors > > "Ted" <ted@ted.com> wrote in message > news:chf9eq$frj$1@newsg2.svr.pol.co.uk... >> Hi, >> >> I would like to make a simple PCI device. I already own an FPGA >> evaluation >> board and I also own a blank PCI prototyping card. I was planning on >> connecting the FPGA board to the PCI prototyping card via ribbon cables. >> Would this cause problems with noise? Would it help if I kept the ribbon >> cables quite short. >> >> Thanks for any info, >> >> > >Article: 72858
http://tinyurl.com/42x6o as to the construction of the ribbon cable - you must solder your connections and wash the board of any flux and keep the length as short as practically possible. Have I done it with PCI? no. Is is possible? probably. Does it meet IEE standards? of course not, but this is a one-off board. good luck.Article: 72859
Hi, Anyone would like to send me a copy of cypress's pci32 target reference design? (it seems to be written in vhdl) thanks a lot! Regards rattt@col.edu.cnArticle: 72860
On Fri, 03 Sep 2004 12:02:36 +0200, Rune Christensen wrote: >> >Does anyone know if it's possible to build a VGA to ethernet converter? A >> >device that converts a VGA signal to a digital videostream. >> >I want to be able to operate a computer from a remote position also when > the >> >computer boots. So I will be able to change bios settings, starting mode > of >> >Windows, etc. some 'server' type computers have a BIOS that will allow you to do the basics over a serial port. After the computer comes up you can run something like windows' RDP or VNC for a remote desktop. >> Some "server management" cards do just this. Needs to either snoop the bus > for VGA >> accesses or fully emulate a VGA adapter (i.e. they /are/ the VGA adapter > for the >> machine). Quite expensive to buy, quite hard to make... >> >> >> -- >> Ian >> >> 'Milk below!' > > I think that this must the easiest solution to the problem. Create a VGA > card that transfer the screen to ethernet instead of a screen. Maybe a PCI > FPGA card could be used to do this. > > To the people on comp.arch.fpga have anyone tried to create a VGA card on a > PCI FPGA card? > This isn't all that simple - assume your video stream is 800x600x8bits per pixel x 60 hz (~230 mbits/sec). To make it work, you'll have to run gigabit ethernet, drop bits or frames, compress or some mixture of these. Next problem is how to get at the screen data - you could implement a whole vga subsystem (don't forget BIOS and drivers), snoop the PCI bus (need to track the state of a real vga chip which can be tricky), get a digital copy of the VGA output data (not all vga chips have digital out) or recapture the data from an analog copy (probably don't have access to the pixel clock, so you need PLLs to recapture the data).Article: 72861
hi !
(1) untill which stage does SOC development and FPGA development is
common ?(i.e. design entry,simulation,synthesis,implementation).
(2) Are there any tools available for SOC development like those
available for FPGA development by xilinx and altera on their
respective websites?
Regards
ved
Article: 72862Hi, It's not the first time this question has been asked, but I'd like to know todays state of art: Are their any devices at Altera, Xilinx or others, capabable of handling the fast throughput of high-speed ADCs (1 GS), such as Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external DMUX-device... Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines per channel. Thanks, AlexArticle: 72863
On 6 Sep 2004 02:35:03 -0700, A_Ungerer@netcourrier.com (Alex) wrote: >Hi, > >It's not the first time this question has been asked, but I'd like to >know todays state of art: >Are their any devices at Altera, Xilinx or others, capabable of >handling the fast throughput of high-speed ADCs (1 GS), such as >Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external >DMUX-device... >Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines >per channel. 500Mbps per LVDS pair doesn't sound too fast. I'd be interested in knowing whether there are any recent FPGAs that *can't* handle that speed. Xilinx XAPP622 shows how it can be done: http://www.xilinx.com/bvdocs/appnotes/xapp622.pdf Regards, AllanArticle: 72864
Hi VHDL folks, does somebody know if there are VHDL models available for USB devices ? A simple model (behavioral) would do the job. Any hints are appreciated. Thank you for your help. RgdsArticle: 72865
ALuPin wrote: >Hi VHDL folks, > >does somebody know if there are VHDL models available for >USB devices ? A simple model (behavioral) would do the >job. > >Any hints are appreciated. > >Thank you for your help. > >Rgds > > Look at http://www.opencores.org/ Regards ThomasArticle: 72866
Hello, I am a third year computer engineering student and have been given the task of completing an FPGA based project utilizing a Xilinx Spartan 3 FPGA and VHDL. It just happens to be my luck that I have limited experience with FPGA architecture or VHDL however I do no intend to let this stop me from achieving this projects requirements. I am looking for experienced individuals of the FPGA development community that would be willing to aid me as mentors or technical advisors during the development of my project. The project is strictly academic and unfortunately the only thing that I can offer for any assistance is my gratitude. The proposed project has the following requirements: Must utilize a Spartan 3 FPGA Must be described using VHDL Must provide an accurate simulation of a 1980's era Pacman machine. Must be completed in 15 weeks. I have searched the net and discovered that this project has already been done by several clever individuals, however simply imitating their efforts will not further my education and I fear that using source code that has been produced by one group of individuals may limit my view on coding/design options. Please contact me if you feel that you can provide any assistance. Any assistance will be greatly appreciated. S. DanielArticle: 72867
Dear Xilinx (and others with RocketIO/X, PCIe experience), I am very interested to know how the Xilinx PCIe Solution works. As far as I have been able to determine there are several problems: 1) Rocket IO does not have direct control of TX enable, PCIe TxElecIdle is specified as Vdiff<20mv during rocketIO TXINHIBIT there is maximum Vdiff that doesnt settle to idle in required time as the PCIe compliant AC decoupling caps (75..200nF) are relativly large. Also from PCIe required recovery from TxIdle to normal differential receive in no more than 20 UI, as of my real experiments with rocketio this will not work (the AC caps are not discharged fast enought) and the recovery takes >50 UI Xilinx PCIe documentation (at least all the documentation what is available) does not indicate that any external "helper-workaround" electrical hardware is required to make the rocketio PCIe compliant. So the question is how does it work ? 2) PCIe specification requires the clock tolerance (for transmit) to be no more than +-300ppm, that means of course that on the receive side the CDR has to lock to signal that has worst case error of +-300ppm But that is outside the lock range for rocketio CDR ? Both rocketIO and X specify that offset to be in range +-100ppm, the PCIe requirement to accept +-300ppm is way beyound that! So the question is how does it work ? >From Xilinx PCIe IP Core datasheet: "The core design is verified using the Xilinx proprietary test bench." Does the test bench really model the transmition line electrical characterisctics - including the AC capacitors, and does it test with worst case +-300ppm offset clock rates ? NiTal has PCIe development boards that all use Virtex2Pro, so I assume the PCIe can be implemented with RocketIO, question is what tricks are used to make the rocketIO PCIe compliant? /Antti LukatsArticle: 72868
Hello all, I am making a PCI add-in card using a Xilinx Spartan II device which provides IOB configurations for nearly all PCI signals. The implemented agent is also supposed to generate PCI interrupts which, electrically, are Open Drain/Open Collector outputs for which I could not find an appropriate IOB configuration. Is anyone out there successfully generating PCI interrupt signals with a Spartan II and willing to let me in on the secret IOB config ? Am I missing something obvious here ? Thanks and regards, Christian BoehmeArticle: 72869
To all,
I am currently using an example from a book which codes a simple
FSM. The code is seen below. I simulate the following FSM obtained
from a text book under Quartus 4.0 with the condition that "in1"
signal is low for one clock-cycle commencing at the negative edge of
the clock for an entire period. During this time, the state machine
is in the "START" state, and the output changes to sequence =
"continue" and the output changes immediately given a small delay
(less than 1/2 clock period). I have sketched out the timing diagram
as it appears in the simulation from the text book. For some reason,
when I simulate this same state machine in Quartus with the same 10 ns
clock period, I end up getting "out1" delayed by more than half the
clock period. I'm simulating using a stratix chipset speed grade -6.
Unbelievably long time of a propagation delay, so does this sound
right to anyone?
---- ----- -----
| | | | | <= clock
| | | | |
---- ---- ----
---- --------------
| | <= in1
| |
---------
---------
| | <= out1
| |
----------- ---------
---------
| | <= out2
| |
--------------------- ---------
ENTITY Test IS
PORT(
clk, in1 :IN STD_LOGIC;
out1, out2 :OUT STD_LOGIC
);
END ENTITY Test;
ARCHITECTURE a OF Test IS
TYPE PULSER IS (start, continue);
SIGNAL sequence: PULSER;
BEGIN
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
CASE sequence IS
when start=>
IF in1 = '1' THEN
sequence <= start;
out1 <= '0';
out2 <= '0';
ELSE
sequence <= continue;
out1 <= '1';
out2 <= '0';
END IF;
when continue=>
sequence <= start;
out1 <= '0';
out2 <= '1';
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE a;
Article: 72870Dear Michal and Hans; That was greate and I just did what you both told me and I got the link to Unisim and SimPrim libraries to my Simulator (Modelsim_SE). Thank you so much. I just used to be an ASIC Designer and that was my first time dealing with FPGAs, I'm trying to get now all components that I can use and design cycle that should run between ModelSim, Leonardo, and Xilinx. If you can give me some directions, I will be thankful again. MohmaedArticle: 72871
I want the unused pins on my EPM7128S to be inputs so I can ground them. After compiling my project, in the pin out file, all unused pins show up as GND* = "Unused I/O pin. This pin can either be left unconnected or connected to GND. Connecting this pin to GND will improve the device's immunity to noise." That's what I want, however, under Assignments (menu) / Device (menu option) / Device & pin options (button) / Unused pins (tab) - I am concerned that "reserve all unused pins" is set to "as outputs that drive an unspecified signal" which seems to be the defualt. Does this setting get overridden?Article: 72872
Hello, I am a third year computer engineering student and have been given the task of completing an FPGA based project utilizing a Xilinx Spartan 3 FPGA and VHDL. It just happens to be my luck that I have limited experience with FPGA architecture or VHDL however I do no intend to let this stop me from achieving this projects requirements. I am looking for experienced individuals of the FPGA development community that would be willing to aid me as mentors or technical advisors during the development of my project. The project is strictly academic and unfortunately the only thing that I can offer for any assistance is my gratitude. The proposed project has the following requirements: Must utilize a Spartan 3 FPGA Must be described using VHDL Must provide an accurate simulation of a 1980's era Pacman machine. Must be completed in 15 weeks. I have searched the net and discovered that this project has already been done by several clever individuals, however simply imitating their efforts will not further my education and I fear that using source code that has been produced by one group of individuals may limit my view on coding/design options. Please contact me if you feel that you can provide any assistance. Any assistance will be greatly appreciated.Article: 72873
sd wrote: >I am a third year computer engineering student and have been given the >task of completing an FPGA based project utilizing a Xilinx Spartan 3 >FPGA and VHDL. Generally this is a bad place to ask for help with homework questions. But here are some hints. Get software and documentation (if you don't already have them) for Spartan 3 FPGA from www.xilinx.com Use one clock. It would be easier if the clock was some multiple of the dot rate that the display is drawn. Write code, simulate, build and test. Repeat as needed. Start at the output, and then improve backwards. Write code to produce a video signal, then produce a display that is like the background, then add one moving part. After that works, add a control. If something doesn't work the way you expect, think about why. Keep at it. We should not hear from you for the next 15 weeks. -- Phil Hays Phil-hays at posting domain should work for emailArticle: 72874
To all,
Does anyone have a good document that describes the design of a
Master Peripheral using the Avalon Bus for Altera Stratix Edition? I
read in detail the Avalon Bus specification sheet, and when I try to
develop the state machine to match the timing diagrams within the
specification sheet, I manage to obtain significant delays (~ 10-11
ns) as a result of tpd within the chip, and therefore cannot align my
waveforms as it is described in the document. The clock frequency I
am using is 100 MHz, since I want to interface with the SDRAM
controller and the NIOS development kit 16MB SDRAM. Does anyone know
if this matters for the Avalon Bus? I mean does a timing
misalignment in sending READ_N, ADDRESS, and BYTEENABLE_N for the read
operation for instance matter greatly to the Avalon interface? Do I
need to slow the interface down, and not use 100 MHz? Any suggestions
on whether this sounds correct would be appreciated.....thus far, I
wish there was better documentation on this so I had a better gutt
feel on whether I'm implementing this correctly. Unfortuantely I
only have the Quartus Environment as a simulator, and can't invoke
Modelsim due to some license issues, I'm currently trying to get over.
Cheers,
Pino
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z