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Hi, I am trying to use hard macros in my design but somehow Xilinx PAR tool goes in an infinite loop during placement when hard macros are used. Here are the steps that I did: 1. Implemented a standalone multiplier with tight timing constraints on the Virtex 4 sx55 device and with stepping level 2. The "Add IO buffers" option was disabled during synthesis. 2. In FPGA editor, a. The extra global signals (of the form XIL_ML_PMV) were trimmed from the multiplier design. b. The remaining design is bounded using "bind" button. (This step does not affect final problem, though) c. The multiplier design is then saved as a hard macro to create an nmc file. 3. Wrote a simple Verilog file that used the above created macro name to define a multiplier which is connected to an adder. 4. Copied the macro file created in step 2.c to the project directory of second design. 5. On implementation of second design, synthesis, translate, and mapping stages run fine. The placer then takes up the full CPU and does not go beyond the following stage even after running for 3-5 hours. ******************* Phase 3.2 (Checksum:1c9c37d) REAL time: 9 secs Phase 4.30 Phase 4.30 (Checksum:26259fc) REAL time: 9 secs Phase 5.3 Phase 5.3 (Checksum:2faf07b) REAL time: 10 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 10 secs Phase 7.8 ........... ******************** The design contains only an adder and multiplier and would otherwise finish in 3-4 minutes. Am I missing something in the flow or am I doing it wrong? Thanks in advance, Love SinghalArticle: 88551
Hello all,
I've futzed around with this enough--time to ask the experts!
I am working on a design for a Spartan 3 FPGA but that isn't that
important. This is the same discussion (I think) for every FPGA family
that doesn't have built-in tri-state buffers.
What I am trying to do is to hookup multiple peripheral modules that
have all functionality and address decoding contained in separate trees
in the hierarchy. The ides is that I can add a uart, digital io, ...
peripherals at the top level and none of the logic for the other modules
needs to change. All the modules can just hook up to the data bus and
the peripheral I/O as need be. All modules would be memory mapped and
would connect to the system data bus for uc control.
How I intended to implement this is with a tri-state like bus knowing
that the synthesizer would replace the tri-state bus with a mux. That
is actually what I want but I'm not sure how to get it.
Below is one such peripheral VHDL module. This is a really simple
module but just picture many of these all instantiated on the same bus.
Other modules would be things like a UART,...
The problem I am having right now is that XST thinks that there are
multiple sources for some of the data bits. There are but I want them
all muxed together.
I'd be ecstatic if someone could point me in the right direction.
TIA,
James.
-------------------
entity dig_io is
generic
(
ADDR_WIDTH : integer := 4;
ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0) := "0000";
DATA_WIDTH : integer := 16;
IO_WIDTH : integer := 4
);
port
(
-- System Control
Rst_i : in std_logic;
-- Data Bus
nMs_i : in std_logic;
nRd_i : in std_logic;
nWr_i : in std_logic;
Addr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0);
Data_io : inout std_logic_vector(DATA_WIDTH-1 downto 0);
-- Peripheral Interface
Dig_i : in std_logic_vector(IO_WIDTH-1 downto 0);
Dig_o : out std_logic_vector(IO_WIDTH-1 downto 0)
); end dig_io;
architecture Behavioral of dig_io is
signal LOW : std_logic;
signal HIGH : std_logic;
signal HIZ : std_logic;
signal data_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal data_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal data_oe : std_logic;
signal dig_in_reg : std_logic_vector(IO_WIDTH-1 downto 0);
signal dig_out_reg : std_logic_vector(IO_WIDTH-1 downto 0);
begin
----------------------------------------------------------------------------
-- Write from processor to this peripheral
----------------------------------------------------------------------------
data_in <= Data_io when (nMs_i = LOW) else (others=>LOW);
--
-- Address decoding of write
--
process( Rst_i, nWr_i, LOW, HIGH )
begin
if( Rst_i = HIGH ) then
dig_out_reg <= (others=>LOW);
elsif( rising_edge(nWr_i) ) then
if( (Addr_i = ADDR) and (nMs_i = LOW) ) then
dig_out_reg <= data_in(7 downto 4);
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Read from processor of this peripheral
----------------------------------------------------------------------------
Data_io <= data_out when (data_oe=HIGH) else (others=>HIZ);
data_out( DATA_WIDTH-1 downto (2*IO_WIDTH)) <= (others=>LOW);
data_out( (2*IO_WIDTH)-1 downto IO_WIDTH) <= dig_out_reg;
data_out( IO_WIDTH-1 downto 0) <= dig_in_reg;
--
-- Address decoding of read
--
process( Addr_i, nMs_i, nRd_i, nWr_i, LOW, HIGH )
begin
-- decode read access
if( (Addr_i = ADDR) and (nMs_i = LOW) and (nRd_i = LOW) ) then
data_oe <= HIGH;
else
data_oe <= LOW;
end if;
end process;
----------------------------------------------------------------------------
-- Connect I/O Pins
----------------------------------------------------------------------------
dig_in_reg <= Dig_i;
Dig_o <= dig_out_reg;
----------------------------------------------------------------------------
-- Generic signals
----------------------------------------------------------------------------
LOW <= '0';
HIGH <= '1';
HIZ <= 'Z';
end Behavioral;
Article: 88552On Fri, 19 Aug 2005 10:58:28 +1000, Mark McDougall <markm@vl.com.au> wrote: >+<fahadislam2002 wrote: >+< >+<> Hi... first thanks for responding........ 1- From time slicing u >+<> mean slicing between rows and colums or between a fixed no of pixels >+<> ? 2- I m using HM62256ALP-8 ... and its speed is 80ns :( ... >+< >+<For 640x480, scanline time is 31.77us. At 4 bits/pixel, you need to >+<fetch 320 bytes in that time, which gives you ~100ns per byte. You'd >+<also need to pre-fetch a scanline on-chip since the actual dot clock is >+<around 25.175MHz (2 pixels = 79ns). >+< >+<But then your SRAM bandwidth utilisation is approaching 100%, which >+<leaves no time for the CPU to update the video memory. I suppose it >+<would be possible to output interleaved VGA, and use every other >+<scanline to allow the CPU to update video RAM, but that has other design >+<implications. >+< >+<Not ideal... :( >+< >+<Regards, >+<Mark ******** You can set the sram up in two banks of 8 bit width each. So that when the video controller reads the sram it reads two bytes at a time, even and odd address. The CPU can write to the ram in either 8 or 16 bit mode. Then use IDMA. When the uP clock is low then the video circuit accesses ram. When the uC clock is high then the uC acesses the ram. This works well with processor speeds up to about 25 MHz. When using dram you need to consider the dram cycle time, not access time, needs to be half the CPU cycle time max. An old technique used in 8 bit computers from the 80's. 80nS cycle time ram will put a maximum of 12.5 Mhz CPU speed. In reality it would be better to run the CPU at 12 MHz for better margin. This adds more complex circuits in addressing the ram. One needs to multiplex the video and cpu addresses as well as data buss. Nothing really to difficult that can't be done in a FPGA though. jamesArticle: 88553
I know have a working IDE interface utilizing the PIO transfer mode. I'm only concerned with writing data so it is only using the 30h write sectors command and it is working well with an old 4gb drive I have. I've been trying to write some VHDL code for the dma start, sustain, and end sequences but its really not going smoothly. I have multiple programs writen in vhdl and then I create symbols for them and wire them together in a schematic. Problem is I can't get anything to simulate now at all no matter what I do I'm kind of a newbie to vhdl, as I'm only a student and only started with this stuff a few months ago but is their a better way to connect these programs together than the schematic that will simulate or is it not simulating likly because the code is written badly? I know its not much to go on but any help would be apperciated Keith WakehamArticle: 88554
James Morrison wrote:
> This is the same discussion (I think) for every FPGA family
> that doesn't have built-in tri-state buffers.
The discussion's over.
There haven't been any real
internal tri-buffs for many years.
It's actually a good thing.
> All the modules can just hook up to the data bus and
> the peripheral I/O as need be. All modules would be memory mapped and
> would connect to the system data bus for uc control.
This is a very good idea. When the IO registers are
all in one module, changes are painful.
> How I intended to implement this is with a tri-state like bus knowing
> that the synthesizer would replace the tri-state bus with a mux. That
> is actually what I want but I'm not sure how to get it.
Consider modeling what's really there --
gates and clock-enabled flops.
Separate writedata from readdata signals.
Write regs are clock enabled for the correct address in write mode.
Read regs drive readdata for the correct address in write mode.
Nothing to it.
Here's a cpu_reg example procedure.
It is intended to be called from a synchronous process.
-- Mike Treseler
---------------------------------------------------
procedure cpu_regs is -- CPU registers
-- this procedure does some post processing on the rx and tx
-- state variables and must *follow* those procedures.
begin
W : if write_stb = '1' then
case address is
when '0' =>
TXQ : Tx_v := writeData; -- grab a byte
kick : TxState_v := START; -- kick off tx
when others => -- nop for cpu write to unused address
end case;
end if W;
-- +----------------------------------------+
-- | Table 1 UART Memory Map |
-- +------+-----+-----+----------+----------+
-- |Name |Add |R/W |Data |Comment |
-- +------+-----+-----+----------+----------+
-- |TXQ |0 |W |7_downto_0| Transmit |
-- | | | | | Data |
-- +------+-----+-----+----------+----------+
-- |RXQ |0 |R |7_downto 0| Receive |
-- | | | | | Data |
-- +------+-----+-----+----------+----------+
-- |StatQ |1 |R |2->TxReady| Status |
-- | | | |1->RxError| Data |
-- | | | |0->RxReady| |
-- +------+-----+-----+----------+----------+
R : if read_stb = '1' then
case address is --
when '0' => -- Collect a byte from the input shifter
RXQ : read_data_v := Rx_v;
RxState_v := IDLE; -- restart the read cycle
when '1' =>
StatQ: if RxState_v = FULL then -- Update rx status:
RxReady : read_data_v(0) := '1'; -- data ready
elsif RxState_v = ERR then
RxError : read_data_v(1) := '1'; -- bad stop
RxState_v := IDLE; -- restart
end if;
if TxState_v = IDLE then
TX_Ready : read_data_v(2) := '1'; -- Update tx
end if;
when others =>
end case;
end if R;
end procedure cpu_regs;
-- For details see http://home.comcast.net/~mike_treseler/
Article: 88555
>
> What I am trying to do is to hookup multiple peripheral modules that
> have all functionality and address decoding contained in separate trees
> in the hierarchy. The ides is that I can add a uart, digital io, ...
> peripherals at the top level and none of the logic for the other modules
> needs to change. All the modules can just hook up to the data bus and
> the peripheral I/O as need be. All modules would be memory mapped and
> would connect to the system data bus for uc control.
>
> How I intended to implement this is with a tri-state like bus knowing
> that the synthesizer would replace the tri-state bus with a mux. That
> is actually what I want but I'm not sure how to get it.
How is this for an idea : (Some examples from www.fpgaarcade.com.)
This is in the Bally code top level. It intantiates a cpu and number of
peripherals. I bring out of each peripheral an "output enable" signal and
the data bus, then build a mux to to the biz at the top level. Big
multiplexers are expensive (you are building a priority mux so be careful -
if you preserve the hierarchy in the synthesis tool it won't spot they are
exclusive) but for an 8 bit data bus you can get away with it. If nobody is
enabled I return a "floated high" bus, but you can do a bus hold by
registering the muxer result, and returning that as the default. The vic-20
does that I think.
Cheers,
MikeJ
peripheral instantiation :
u_data : BALLY_DATA
port map (
I_MXA => cpu_addr,
I_MXD => cpu_data_out,
O_MXD => mx_data,
O_MXD_OE_L => mx_data_oe_l,
-- cpu control signals
I_M1_L => cpu_m1_l,
I_RD_L => cpu_rd_l,
etc
I
mux :
cpu_src_data_mux : process(rom_dout, sys_cs_l, I_CAS_DATA, cas_cs_l,
I_EXP_OE_L, I_EXP_DATA, exp_buzoff_l,
mx_addr_oe_l, mx_addr, mx_data_oe_l, mx_data,
mx_io_oe_l, mx_io)
begin
-- nasty mux
if (I_EXP_OE_L = '0') or (exp_buzoff_l = '0') then
cpu_data_in <= I_EXP_DATA;
elsif (sys_cs_l = '0') then
cpu_data_in <= rom_dout;
elsif (cas_cs_l = '0') then
cpu_data_in <= I_CAS_DATA;
elsif (mx_addr_oe_l = '0') then
cpu_data_in <= mx_addr;
elsif (mx_data_oe_l = '0') then
cpu_data_in <= mx_data;
elsif (mx_io_oe_l = '0') then
cpu_data_in <= mx_io;
else
cpu_data_in <= x"FF"; -- emulate floating bus pulled hi
end if;
end process;
Article: 88556Hello, I have some design with regular structure (i.e. resembling 2D array), synthesizing in ISE 6.3 (for Spartan 3).And I experiencing following problem: Assume the there is simple 3-level hierarchy A |_B |_C The synthesis results for Unit "C" gives me implementation in X slices; in B - X+1. OK I assume that due to complex routing it is a predictable result (yet hesitating). But when I try to place and route unit A - it gives me X+2 slices, which conflicts with my area constraints. The problem is that "A" is simply an implementation of B (for debugging purposes). So I guess there are some differences in synthesis process. The constraints files, as well as Synth., Map, and PAR options are the same. So probably I am missing something. Maybe someone can give some tips how to resolve this really annoying problem. Thanks. -- AlexArticle: 88557
james wrote: > You can set the sram up in two banks of 8 bit width each. So that > when the video controller reads the sram it reads two bytes at a > time, even and odd address. I got the impression (either rightly or wrongly) that the original poster only has a single 8X256KB SRAM to play with, most likely he's doing this on an eval board of some sort?!? > An old technique used in 8 bit computers from the 80's. Yeah, I've seen an 80's arcade game time multiplex RAM access to two 6809 processors using a similar method - from memory the two cpu clocks were 180 deg out of phase?!? Clever. Regards, MarkArticle: 88558
Terradestroyer@gmail.com wrote: > Problem is I can't get anything to > simulate now at all no matter what I do I'm not really sure what you mean by "won't simulate"? > I'm kind of a newbie to vhdl, as I'm only a student and only started > with this stuff a few months ago but is their a better way to connect > these programs together than the schematic that will simulate or is > it not simulating likly because the code is written badly? There's no reason to use schematics in the design at all (though I'd argue that a top-level schematic can show a design hierarchy very nicely). You can replace your schematic with the equivalent in VHDL to connect your modules together. Regards, MarkArticle: 88559
Alex wrote:
> So probably I am missing something.
> Maybe someone can give some tips how to resolve this really annoying
> problem.
It may be unexpected, but it's only a problem
if you are out of slices. If that's the case
you could try your own synthesis with instances
of primitive elements or get a bigger part.
-- Mike Treseler
Article: 88560
The two designs are not equivalent; they will create functionally different
hardware, hence the performance difference. The designer is getting tripped
up by a common Verilog gotcha, using a value "1" when he really meant to set
a bit to 1. The problem is this line of test2.v:
{index3, value3} <= {index2, value2 + 1};
This is *not* equivalent to index3 <= index2; value3 <= value2 + 1. The
constant "1" is treated as a 32-bit wide quantity (as specified in the
Verilog LRM), so "value2 + 1" is a 32-bit quantity. The RHS ends up being 37
bits wide with the top 5 bits being index2 and the bottom 32 having the
value "value2 + 1". The LHS is only 6+5 = 11 bits wide, so the result of the
assignment is that index3[0] gets the carry bit from value2 + 1, and the
other bits of index[3] become zero.
Quartus gives a warning on this line to tell you that you might have done
something wrong:
Warning: Verilog HDL assignment warning at test2.v(19): truncated value with
size 37 to match size of target (11)
If you change the offending line to
{index3, value3} <= {index2, value2 + 1'b1};
... now the RHS will be 11 bits wide like the LHS and the two designs are
functionally equivalent, and Quartus will give the same hardware and the
same performance numbers.
Hope this helps,
Subroto Datta
Altera Corp.
"Tommy Thorn" <foobar@nowhere.void> wrote in message
news:kc6Oe.10090$p%3.39138@typhoon.sonic.net...
> My mind is boggling.
>
> Experimenting with Quartus 5.0 SP1 (targeting an EP1C20F400C7) I was quite
> puzzled to find that test1 can run at 189.83 MHz, while test2 maxes out at
> 156.25 MHz. Aren't the two fragments logically exactly the same?
>
> Tommy
>
>
> module test1(clk, index, value2);
> parameter N = 5; // Word size-1
> parameter M = 4; // Entries log2-1
>
> input wire clk;
> input wire [M:0] index;
> output reg [N:0] value2;
>
> reg [N:0] counters[(1 << (M + 1)) - 1:0];
> reg [M:0] index1, index2, index3;
> reg [N:0] value3;
>
> always @(posedge clk) begin
> index1 <= index;
> index2 <= index1; value2 <= counters[index1];
> index3 <= index2; value3 <= value2 + 1;
> counters[index3] <= value3;
> end
> endmodule
>
> module test2(clk, index, value2);
> parameter N = 5; // Word size-1
> parameter M = 4; // Entries log2-1
>
> input wire clk;
> input wire [M:0] index;
> output reg [N:0] value2;
>
> reg [N:0] counters[(1 << (M + 1)) - 1:0];
> reg [M:0] index1, index2, index3;
> reg [N:0] value3;
>
> always @(posedge clk) begin
> {index1} <= {index};
> {index2, value2} <= {index1, counters[index1]};
> {index3, value3} <= {index2, value2 + 1};
> {counters[index3]} <= {value3};
> end
> endmodule
Article: 88561Yes, I had that problem. I presume you meant a .coe file. Turns out this is a simulation problem when using that particular core (version 6.2 I believe). In my case, I reverted back to the ver 6.1 core and was able to input a .coe file. After that, simulation worked fine. On 22 Aug 2005 04:59:41 -0700, "alpha" <zhg.liu@gmail.com> wrote: >Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual >port block ram core generated by Coregen does not contain the >initialization data defined in a .ceo file. The simulation using >Modelsim is OK after I modified .v file to specify the correct .mif >file. > >Anyone has same problem and how to solve? >ThanksArticle: 88562
Yes version 6.2 core has problem. Not only for Simulation, but also for real implementation. You can modify paremeter c_has_default_data(=0) and c_mem_init_file(=your .mif file name) in generated .v file. This will allow Modelsim work. But still has issue to generate .bit file. I have to switch to single port memory. It works. So I believe it is a tools' bug. Do not know why Xilinx's software has so many problems? Marko wrote: > Yes, I had that problem. I presume you meant a .coe file. Turns out > this is a simulation problem when using that particular core (version > 6.2 I believe). In my case, I reverted back to the ver 6.1 core and > was able to input a .coe file. After that, simulation worked fine. > > > On 22 Aug 2005 04:59:41 -0700, "alpha" <zhg.liu@gmail.com> wrote: > > >Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual > >port block ram core generated by Coregen does not contain the > >initialization data defined in a .ceo file. The simulation using > >Modelsim is OK after I modified .v file to specify the correct .mif > >file. > > > >Anyone has same problem and how to solve? > >ThanksArticle: 88563
im planing to buy digilent spartan3 starter kit with a 1M gate device together with digilent USB2 accessory module. If some one got any experiance on these devices please let me know. are there better alternatives for this combination? Is this module support high speed data rate of USB2? thank you CMOSArticle: 88564
I've gone to the www.systemc.org and downloaded the offical LRM (language reference manual.) I tried to read it, but I'm sorry to say I need more of a 'tutorial' guide to learn the basics. Does anyone have good links or know of good introductory books to SystemC?Article: 88565
I believe there is some stuff like that on the fraunhoffer site and doulos.Article: 88566
Hi all, I am interfacing LAN91C111 chip with NIOS II processor in an Altera Stratix device. After I finish generating my system in SOPC Builder, I create the bdf file (or an hdl file) of the system in order to examine the INs and OUTs of the system. I observed that for lan91c111, the only outputs generated were IO RD and WR, ADS, WEN, BE, IRQ, Reset etc. I checked the schematic of the NIOS Development Board (1S10ES), where there are many more signals going to lan91c111 chip from the FPGA (eg. CYCLE, LCLK etc.). However my NIOS design doesn't generate all the signals of the lan91c111 inputs. From where do I get these signals? I noticed that whichever signal port was not generated in the bdf, should be high for asynchronous operation of the Ethernet. This is the case with NIOS development kit as well, in my opinion. Are these signals tristated from FPGA. In that case, can I do the same outside the FPGA chip using some high resistance (and hence save some of the FPGA pins) since I may never use sync mode of operation in my design.Article: 88567
wolf359mmcb@gmail.com wrote: > but i have have this problem and think that a small change somewhere > will fix it. > i have been using xilinx system generator to design a neural network > for FPGA. it seems to synthesize and download properly. i have added > a chipscope cores to check if it runs as expected on the FPGA however > it complains when run that it has a slow or stopped clock. i interpret > this to mean that system generator has not correctly generated the VHDL > file or i have missed a step somewhere. please any pointers you have > for this problem are appreciated. I am using xilinx system generator, > Ise and chipscope Pro version 6.3i with updated ip. the device i am > developing for is the virtex 2 pro XCV2p50. > Hi, I ran into the same problem a few days ago. In my case the problem was that the ADC which provided the clock signal to the FPGA didn't get enough power. I.e. the FPGA didn't get any clock signal at all. Check your clock circuitry, is it working correctly? regards johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 88568
I just generated a design with XPS, using edk 6.3i. It had a DDR controller, and a bus speed 4x lower than the 100Mhz CPU. The problem is, when I try to simulate this design, nothing happens, since the second DCM in the chain does not generate ANY output signals. I cannot find any cause of this. I didn't modify any of the settings, I just generated and then went straigt to simulation in modelsim. The chain is as follows: DCM1 : clk divider, from 100 to 25 mhz DCM2 : clk shifter, generates shifted signals <= DOES NOT WORK DCM3 : DDR feedback shifter (uses external feedback loop) Any thoughts on this one? I put the simulation resolution on 1PS etc. All other systems simulate just fine. ThanksArticle: 88569
Hallo, I have a spartan 3 starter board. I have implemented a small microcontroller based on microblaze. I would use the rs232 of the board as stdin and stdout. I have configured it into edk. What software should I use into pc to send/ receive datas? I have tried Hyperterminal, but it seems it doesn't connect. Many Thanks MarcoArticle: 88570
What about Xilinx place and route cost table mean ? Or someone can give any information not just a number ? Thank you!Article: 88571
On 2005-08-10, fahadislam2002 <fahadislam2002@hotmail-dot-com.no-spam.invalid> wrote: > today i feel my mathamatics is also weak 8) ... Actually my question > was just that is it possible by using some kind of techniques like > compression etc /// and if possible then how and by using which > techniques 8) ... thanks 8) It depends on what you want to achieve. A regular bitmapped display is out of the question since you don't have enough memory. If you need to show simple images only with large fields of the same color you could use some sort of RLE compression to dramatically reduce the memory requirements. However, if you want to show mostly text you could create a character generator hardware. You have one memory with information about what characters you want to show and one memory with information about how the characters look. Say that each character is 8x8 pixels large. If you want to store 256 different characters this will take 2048 bytes. With 8x8 pixel large characters you can store up to 80x60 characters on a standard VGA sized screen. (4800 bytes) See http://www.fpga4fun.com/GraphicLCDpanel3.html for some inspiration. By drawing characters in a clever fashion you could even include some graphics on your display. It is also possible to include colors in the characters if you increase the size of the font rom. This is basically how the graphics worked on old video game consoles such as the NES and SNES. /AndreasArticle: 88572
Marco wrote: > What software should I use into pc to send/ receive datas? > I have tried Hyperterminal, but it seems it doesn't connect. Have you checked the settings for the OPB_UART-component or whatever you use for the RS232? The settings for baudrate, partity and stop bits have to be identical in EDK and Hyperterminal, otherwise it won't work. cu, SeanArticle: 88573
That's the thing I can't be out of slices on level A, as it is only a wrapper for element "B" - so logically it is exactly the same. However the result is different. I normally don't tend to blame software :) but so far I can't really find the reason. Any other guesses. > Alex wrote: > >> So probably I am missing something. >> Maybe someone can give some tips how to resolve this really annoying >> problem. > > It may be unexpected, but it's only a problem > if you are out of slices. If that's the case > you could try your own synthesis with instances > of primitive elements or get a bigger part. > > -- Mike Treseler -- AlexArticle: 88574
Alex wrote: > That's the thing I can't be out of slices on level A, as it is only a > wrapper for element > "B" - so logically it is exactly the same. However the result is different. > I normally don't tend to blame software :) but so far I can't really find > the reason. Howdy Alex, The various report files should show what elements (MUXF's, LUTs, FF's, slices, CLB's, etc) are being used differently across your different hieractical locations. What do they tell you? Have you tried compiling both with and without flattening of hierachy? I find it a bit surprising that A and B produce different results - but synthesis tools can be finicky sometimes. Marc > > Alex wrote: > >> Assume the there is simple 3-level hierarchy > >> A > >> |_B > >> |_C > >> So probably I am missing something. > >> Maybe someone can give some tips how to resolve this really annoying > >> problem. > > > > It may be unexpected, but it's only a problem > > if you are out of slices. If that's the case > > you could try your own synthesis with instances > > of primitive elements or get a bigger part. > > > > -- Mike Treseler
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