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> See if you can use simple concatenation instead of most of your > computations... > > /Mikhail Howdy Nick, In case you didn't understand what Mikhail is suggesting, concatenation for this type of thing would look something like this: address(34 downto <something>) <= page_group; address(<something-1> downto <something_else>) <= page_number; address(<something_else-1> downto 0) <= index; You can control or increment each one as needed, and independantly. Marc > "Nick" <nick@no-domain> wrote in message > news:luoig1d0a1qrlj95qflg0tvqnck7g5nidr@4ax.com... > > Sorry about the lack of details :) > > > > I need to compute an adress in a RAM given the following parameter : > > page group, page number and offset (so typically it's > > PG*page_size*number_pages + page_number*page_size + offset) > > The size of the page is 833 850. > > A group of page contains 16 pages, and there are up to 1024 pages. > > > > This computation does not work simply using Quartus (the output is too > > large) > > > > Then I split this adress in two, take the most significants bits to > > adress the RAM (in 8*64 bits) and the 9 less significants bits to > > adress in the data block (take one bit from the 8*64) > > > > The speed is not really an issue. The design works at 50 MHz, but I > > could use several clocks ticks to do this (actually I already use 4 > > for smaller size), but I could go to up to 20 without drawback. > > > > The design is supposed to work on a Cyclone EP1C20, speed grade 7 > > > > The solution I identified would be use megafunctions allowing more > > than 32 bits for the operands so I could do my computation and split > > without problem. But then I concerned with portability of the design > > > > A later solution would be to compress the data so the size of the page > > is smaller (at least 2 times) but it wouldn't be enough to come under > > the 32 bits limit. > > > > Thanks > > Nick > > > > On 21 Aug 2005 05:30:53 -0700, "Marc Randolph" <mrand@my-deja.com> > > wrote: > > > > >Nick wrote: > > >> Hello, > > >> > > >> I need to use large number (up to 12 774 182 400) in my design, bigger > > >> than a typical long. > > >> The question is : how can I do it ? And efficiently ? > > >> > > >> I could split the number in two parts, do the computations and the > > >> carry-bits, but i'm afraid it would be to much of a pain and I bet > > >> somebody already did it... > > > > > >Howdy Nick (although this reply would help mikelinyoho/frankgerlach22 > > >as well), > > > > > > The quality of the answers you get in comp.arch.fpga are usually > > >proportional to the amount of detailed information included in the > > >question. > > > > > >In your case, you have provided only two (mostly insignificant) pieces > > >of info: you have a single largish number and you want to do something > > >to it that might or might not involve some carry bits. > > > > > >To get a good answer, you'll need to explain what you are trying to do, > > >and if possible, why you are trying to do it. There are lots of very > > >sharp people in this newsgroup, and for open-ended questions like > > >these, they often identify solutions that the OP never even considered. > > > > > >In short, when asking a question in this newsgroup, you need to include > > >as much detail as possible: > > > > > >1. What's the 10,000 foot (high-level) view of what you're trying to > > >do? > > >2. What are the details (low-level view) of what you're trying to do? > > >3. What solution(s) have you already identified? > > > > > >4. What function(s) surround this one? > > >5. What's the interface to the surrounding functions > > >(speed/width/protocol)? > > > > > >6. Which vendor/part number/speed grade are you trying to use? > > >7. What clock speed(s) are being fed to the FPGA pins? > > >8. Is there a limit to the amount of time it can take to perform the > > >function? > > > > > >Have fun, > > > > > > Marc > >Article: 88576
"Sean Durkin" <smd@despammed.com> wrote in message news:430b026d$1@news.fhg.de... > Marco wrote: >> What software should I use into pc to send/ receive datas? >> I have tried Hyperterminal, but it seems it doesn't connect. > Have you checked the settings for the OPB_UART-component or whatever you > use for the RS232? The settings for baudrate, partity and stop bits have > to be identical in EDK and Hyperterminal, otherwise it won't work. > > cu, > Sean Baudrate, parity and stop bits are identical, but I don't see nothing written into hyperterminal console, and I'm not able to write in it.Article: 88577
Hallo, I have made a small microcontroller based on microblaze, with a Spartan 3 starter board. At power on, I would load bitstream into fpga and my software into board ram. I have programmed using impact the board flash rom with file: download.bit (generated with edk). (49% occupied). Before uploading I have updated it with bootloader (it should be loaded into block ram). When I power on the board, now the fpga is configured by itself. Now I should copy my software into flash rom. Bootloader, at boot, should copy it into board ram and execute, but I'm not able. I have tried with Program Flash Memory tool, without obtaining any result. It writes: Processor started. Type "stop" to stop processor And I can't write like into xmd consolle. What could I do? Many Thanks MarcoArticle: 88578
Hi Marc,
I have checked the MAP reports of both design and here is the difference:
For the Element B:
AREA_GROUP AG_CU
RANGE: SLICE_X6Y2:SLICE_X8Y1,SLICE_X5Y1:SLICE_X5Y1
COMPRESSION: 100
AREA GROUP Logic Utilization:
Total Number of Slice Registers: 6 out of 14 42%
Number used as Flip Flops: 2
Number used as Latches: 4
Logic Distribution:
Number of occupied Slices: 7 out of
7 100%
Number Slices used containing only related logic: 4 out of
7 57%
Number Slices used containing unrelated logic: 3 out of
7 42%
*See NOTES below Design Summary for an explanation of the effects of
unrelated logic
Total Number 4 input LUTs: 12 out of 14 85%
Number used as logic: 12
For the element A:
AREA_GROUP AG_P00__CU
RANGE: SLICE_X6Y2:SLICE_X8Y1,SLICE_X5Y1:SLICE_X5Y1
COMPRESSION: 100
AREA GROUP Logic Utilization:
Total Number of Slice Registers: 6 out of 14 42%
Number used as Flip Flops: 2
Number used as Latches: 4
Logic Distribution:
Number of occupied Slices: 8 out of 7 114% (OVERMAPPED)
Number Slices used containing only related logic: 4 out of
8 50%
Number Slices used containing unrelated logic: 4 out of
8 50%
*See NOTES below Design Summary for an explanation of the effects of
unrelated logic
Total Number 4 input LUTs: 13 out of 14 92%
Number used as logic: 13
So now we can see that the amount of unrelated logic has increased!!
For the element C itself with the same constraints the data is:
Logic Distribution:
Number of occupied Slices: 7 out of
13,312 1%
Number of Slices containing only related logic: 5 out of
7 71%
Number of Slices containing unrelated logic: 2 out of
7 28%
I don't really see the the reason for appearing of the additional logic at
the "A"
level of hierarchy. The PLACE constrainis is set to CLOSED.
:(
Alex
Article: 88579Ah, be careful with Hyperterminal, It's not the greatest. Make sure (if this is the case for you) that you have the flow-control set correctly... "None" means that it doesn't use any protocol to ensure the terminals at either end of the line are alive and synchronised etc etc. I normally find this the best way to go. (ie. the only wires used in the cable are Tx and Rx) Also make sure you check the box that says "echo typed characters locally" if you want to see what you're typing. But by far the best is to write a tiny VB script, using MSComm1.OnComm to grab data from the PC UART and send it back. Lets you rapidly develop some interesting debug stuff! HTH Ben "Marco" <marcotoschi@nospam.it> wrote in message news:def7pg$6qg$1@news.ngi.it... > > "Sean Durkin" <smd@despammed.com> wrote in message > news:430b026d$1@news.fhg.de... >> Marco wrote: >>> What software should I use into pc to send/ receive datas? >>> I have tried Hyperterminal, but it seems it doesn't connect. >> Have you checked the settings for the OPB_UART-component or whatever you >> use for the RS232? The settings for baudrate, partity and stop bits have >> to be identical in EDK and Hyperterminal, otherwise it won't work. >> >> cu, >> Sean > > > Baudrate, parity and stop bits are identical, but I don't see nothing > written into hyperterminal console, and I'm not able to write in it. > >Article: 88580
are there any warnings about unmapped blocks in modelsim? I had it once where it failed to wire up one of the primitives because i'd not read the Xilinx doc properly. Ben <zoinks@mytrashmail.com> wrote in message news:1124791832.379516.148920@g44g2000cwa.googlegroups.com... >I just generated a design with XPS, using edk 6.3i. > It had a DDR controller, and a bus speed 4x lower than the 100Mhz CPU. > > The problem is, when I try to simulate this design, nothing happens, > since the second DCM in the chain does not generate ANY output signals. > I cannot find any cause of this. I didn't modify any of the settings, I > just generated and then went straigt to simulation in modelsim. > > The chain is as follows: > > DCM1 : clk divider, from 100 to 25 mhz > DCM2 : clk shifter, generates shifted signals <= DOES NOT WORK > DCM3 : DDR feedback shifter (uses external feedback loop) > > Any thoughts on this one? I put the simulation resolution on 1PS etc. > All other systems simulate just fine. > > Thanks >Article: 88581
Is it adding an IO Buffer or something like that? "Alex" <al.lopich@gmail.com> wrote in message news:opsvyrpqwuuctc33@d48mko2.ee.umist.ac.uk... > Hi Marc, > > I have checked the MAP reports of both design and here is the difference: > For the Element B: > > AREA_GROUP AG_CU > RANGE: SLICE_X6Y2:SLICE_X8Y1,SLICE_X5Y1:SLICE_X5Y1 > COMPRESSION: 100 > AREA GROUP Logic Utilization: > Total Number of Slice Registers: 6 out of 14 42% > Number used as Flip Flops: 2 > Number used as Latches: 4 > Logic Distribution: > Number of occupied Slices: 7 out of > 7 100% > Number Slices used containing only related logic: 4 out of > 7 57% > Number Slices used containing unrelated logic: 3 out of > 7 42% > *See NOTES below Design Summary for an explanation of the effects of > unrelated logic > Total Number 4 input LUTs: 12 out of 14 85% > Number used as logic: 12 > > For the element A: > > AREA_GROUP AG_P00__CU > RANGE: SLICE_X6Y2:SLICE_X8Y1,SLICE_X5Y1:SLICE_X5Y1 > COMPRESSION: 100 > AREA GROUP Logic Utilization: > Total Number of Slice Registers: 6 out of 14 42% > Number used as Flip Flops: 2 > Number used as Latches: 4 > Logic Distribution: > Number of occupied Slices: 8 out of 7 114% (OVERMAPPED) > Number Slices used containing only related logic: 4 out of > 8 50% > Number Slices used containing unrelated logic: 4 out of > 8 50% > *See NOTES below Design Summary for an explanation of the effects of > unrelated logic > Total Number 4 input LUTs: 13 out of 14 92% > Number used as logic: 13 > > > So now we can see that the amount of unrelated logic has increased!! > > For the element C itself with the same constraints the data is: > Logic Distribution: > Number of occupied Slices: 7 out of 13,312 > 1% > Number of Slices containing only related logic: 5 out of > 7 71% > Number of Slices containing unrelated logic: 2 out of > 7 28% > > I don't really see the the reason for appearing of the additional logic at > the "A" > level of hierarchy. The PLACE constrainis is set to CLOSED. > :( > > > AlexArticle: 88582
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:defake$igo$1@sunnews.cern.ch... > Ah, be careful with Hyperterminal, It's not the greatest. > Make sure (if this is the case for you) that you have the flow-control set > correctly... > "None" means that it doesn't use any protocol to ensure the terminals at > either end of the line are alive and synchronised etc etc. I normally find > this the best way to go. > (ie. the only wires used in the cable are Tx and Rx) > Also make sure you check the box that says "echo typed characters locally" > if you want to see what you're typing. > But by far the best is to write a tiny VB script, using MSComm1.OnComm to > grab data from the PC UART and send it back. Lets you rapidly develop some > interesting debug stuff! > HTH > Ben > I'm using the core uart lite, it functions as core uart? I don't know VB, could you tell me some (free) software? MarcoArticle: 88583
Hmm, free I don't know, I use Visual Studio 6.0, I see that they released a 2005 beta version - see if you can try it! Ben "Marco" <marcotoschi@nospam.it> wrote in message news:defb1q$7q4$1@news.ngi.it... > > "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> > wrote in message news:defake$igo$1@sunnews.cern.ch... >> Ah, be careful with Hyperterminal, It's not the greatest. >> Make sure (if this is the case for you) that you have the flow-control >> set correctly... >> "None" means that it doesn't use any protocol to ensure the terminals at >> either end of the line are alive and synchronised etc etc. I normally >> find this the best way to go. >> (ie. the only wires used in the cable are Tx and Rx) >> Also make sure you check the box that says "echo typed characters >> locally" if you want to see what you're typing. >> But by far the best is to write a tiny VB script, using MSComm1.OnComm to >> grab data from the PC UART and send it back. Lets you rapidly develop >> some interesting debug stuff! >> HTH >> Ben >> > > I'm using the core uart lite, it functions as core uart? > > I don't know VB, could you tell me some (free) software? > > Marco >Article: 88584
In fact you can try it here: http://lab.msdn.microsoft.com/express/vbasic/default.aspx "Marco" <marcotoschi@nospam.it> wrote in message news:defb1q$7q4$1@news.ngi.it... > > "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> > wrote in message news:defake$igo$1@sunnews.cern.ch... >> Ah, be careful with Hyperterminal, It's not the greatest. >> Make sure (if this is the case for you) that you have the flow-control >> set correctly... >> "None" means that it doesn't use any protocol to ensure the terminals at >> either end of the line are alive and synchronised etc etc. I normally >> find this the best way to go. >> (ie. the only wires used in the cable are Tx and Rx) >> Also make sure you check the box that says "echo typed characters >> locally" if you want to see what you're typing. >> But by far the best is to write a tiny VB script, using MSComm1.OnComm to >> grab data from the PC UART and send it back. Lets you rapidly develop >> some interesting debug stuff! >> HTH >> Ben >> > > I'm using the core uart lite, it functions as core uart? > > I don't know VB, could you tell me some (free) software? > > Marco >Article: 88585
"Marco" <marcotoschi@nospam.it> wrote in message news:def8gn$711$1@news.ngi.it... > Hallo, > I have made a small microcontroller based on microblaze, with a Spartan 3 > starter board. > > At power on, I would load bitstream into fpga and my software into board > ram. > > I have programmed using impact the board flash rom with file: download.bit > (generated with edk). (49% occupied). > > Before uploading I have updated it with bootloader (it should be loaded > into block ram). > > When I power on the board, now the fpga is configured by itself. > > Now I should copy my software into flash rom. > > Bootloader, at boot, should copy it into board ram and execute, but I'm > not able. > > I have tried with Program Flash Memory tool, without obtaining any result. > > It writes: > > Processor started. Type "stop" to stop processor > > And I can't write like into xmd consolle. > > > What could I do? > > Many Thanks > Marco > I'm using a 2 Mbit flash and fpga code is 1 Mbit. I would write my software after the fpga code. I have read also XAPP482, but I don't have understood the way to write after 1 Mbit. It tells to: 1)convert the elf file into mem with data2mem 2)use pc_ublaze.pl to add software to prom. MarcoArticle: 88586
No, no errors whatsoever, except some warnings about X/U/W/Z's in arithmetic operands, but those are only the first few ns. The only difference with other ocm systems I made is that this is the first time I use clock divider, so I'm running on 25Mhz, instead of 100, but the parameter CLKIN_PERIOD is set accordingly... I read there are bugs with some values of CLKIN_PERIOD, could this be one of them?Article: 88587
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:defb8s$jvm$1@sunnews.cern.ch... > In fact you can try it here: > http://lab.msdn.microsoft.com/express/vbasic/default.aspx > > "Marco" <marcotoschi@nospam.it> wrote in message > news:defb1q$7q4$1@news.ngi.it... >> >> "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> >> wrote in message news:defake$igo$1@sunnews.cern.ch... >>> Ah, be careful with Hyperterminal, It's not the greatest. >>> Make sure (if this is the case for you) that you have the flow-control >>> set correctly... >>> "None" means that it doesn't use any protocol to ensure the terminals at >>> either end of the line are alive and synchronised etc etc. I normally >>> find this the best way to go. >>> (ie. the only wires used in the cable are Tx and Rx) >>> Also make sure you check the box that says "echo typed characters >>> locally" if you want to see what you're typing. >>> But by far the best is to write a tiny VB script, using MSComm1.OnComm >>> to grab data from the PC UART and send it back. Lets you rapidly develop >>> some interesting debug stuff! >>> HTH >>> Ben >>> >> >> I'm using the core uart lite, it functions as core uart? >> >> I don't know VB, could you tell me some (free) software? >> >> Marco >> > > Sorry for my bad english. I would know if there are other softwares like hyperterminal, but that work better. MarcoArticle: 88588
What I mean by won't simulate is I can't get a waveform back with the Xilinx ISE simulator once I have turned all my vhdl into symbols and wired them in a schematic. Once I use the create symbol command on the vhdl and then use the symbol in a schematic it doesn't seem to allow me to run a simulation, everything just goes unintialized This is likely all just because I'm unexperienced with using schematics. Has anyone else had this issue when translatting a vhdl to symbol?Article: 88589
It seems that problem has been solved. Problem was that in "A" I have one element unconstrained (unlike in B) however I thought MAPer will fit it onto free slices. When I placed back that constrain, everything seemed to work ok (the synthesis results are the same). I can't really explain such behaviour, but it works. So now the question is why it has been changed from the unit C. Unit B(simple asynch processor) is combined from different modules, every of which is strictly constrained (by area). In unit B all the units are simply interconnected (i.e. no additional logic used), so there again no reason for logic elements increase. > Alex wrote: >> That's the thing I can't be out of slices on level A, as it is only a >> wrapper for element >> "B" - so logically it is exactly the same. However the result is >> different. >> I normally don't tend to blame software :) but so far I can't really >> find >> the reason. > > Howdy Alex, > > The various report files should show what elements (MUXF's, LUTs, FF's, > slices, CLB's, etc) are being used differently across your different > hieractical locations. What do they tell you? Have you tried > compiling both with and without flattening of hierachy? > > I find it a bit surprising that A and B produce different results - but > synthesis tools can be finicky sometimes. > > Marc > >> > Alex wrote: >> >> Assume the there is simple 3-level hierarchy >> >> A >> >> |_B >> >> |_C >> >> So probably I am missing something. >> >> Maybe someone can give some tips how to resolve this really annoying >> >> problem. >> > >> > It may be unexpected, but it's only a problem >> > if you are out of slices. If that's the case >> > you could try your own synthesis with instances >> > of primitive elements or get a bigger part. >> > >> > -- Mike Treseler > -- AlexArticle: 88590
Generally there are 100 variations of the place and route algorithm otherwise known as cost tables. Which one is better for any given design varies with the design. Unless you have an issue meeting timing, or want to try down the speed grade of a design, then you don't need to bother with them and just use the default single run setting. The ISE tools support multiple place and route (MPPR) which uses a number of these cost tables and tells you which it thinks did best. As far as I am aware the details of the tables are not public domain although Peter or Austin may say otherwise. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <huangjielg@gmail.com> wrote in message news:1124793870.960302.79760@g14g2000cwa.googlegroups.com... > What about Xilinx place and route cost table mean ? > Or someone can give any information not just a number ? > Thank you! >Article: 88591
Hey, I've got 3 ebooks about systemc: -Synopsis rtl systemc -systemc from the ground, and -SoC design and verification using systemc Just drop me an email at dima_turbiner[at]yahoo.com and I'll send them to you (about 25 MB). Good luck, DimitriArticle: 88592
"Marco" <marcotoschi@nospam.it> wrote in message news:defcnq$8cm$1@news.ngi.it... > I would know if there are other softwares like hyperterminal, but that work > better. TeraTerm is much better. Get it here: http://hp.vector.co.jp/authors/VA002416/teraterm.html . Unfortunately, it hasn't been updated since 1999 (!), but it works fine under all Windows OSes. The main limitation is that it only knows about Com1:-Com4: . Personally, I'm surprised Microsoft included the piece of junk that is Hyperterminal in Windows; there were far better choices! I also find it incredible that Hilgraeve had the audacity to stick an advertisement for the full version of their product into it -- yeah, if the stripped-down version works so poorly, I'd really want to risk using a full blown version!Article: 88593
On 23 Aug 2005 05:34:00 -0700, "Marc Randolph" <mrand@my-deja.com> wrote: > >> See if you can use simple concatenation instead of most of your >> computations... >> >> /Mikhail > >Howdy Nick, > >In case you didn't understand what Mikhail is suggesting, concatenation >for this type of thing would look something like this: > >address(34 downto <something>) <= page_group; >address(<something-1> downto <something_else>) <= page_number; >address(<something_else-1> downto 0) <= index; > >You can control or increment each one as needed, and independantly. > > Marc I did understand what he said, but if I do this I'll waste most of the space in ram (833 850 isn't nicely divided by 2 ...) NickArticle: 88594
On Tue, 23 Aug 2005 10:29:51 +1000, Mark McDougall <markm@vl.com.au> wrote: >+<Yeah, I've seen an 80's arcade game time multiplex RAM access to two >+<6809 processors using a similar method - from memory the two cpu clocks >+<were 180 deg out of phase?!? Clever. ***** 6800 was 180 out of phase,the 6809 uses a quadrature phased clock, 90 degrees. Does nice, the internal logic machine now has four transistions or states for every clock cycle. The 68HC11 also uses the same clock scheme. jameArticle: 88595
Terradestroyer@gmail.com wrote:
> What I mean by won't simulate is I can't get a waveform back with the
> Xilinx ISE simulator once I have turned all my vhdl into symbols and
> wired them in a schematic.
It's easier to "wire" the sub entities into
top.vhd with an instance like this:
uart_1: entity work.UART -- using default generic constants
port map (
clock => clk_s, -- [in]
reset => rst_s, -- [in]
address => address_s, -- [in]
writeData => writeData_s, -- [in]
write_stb => write_stb_s, -- [in]
readData => readData_s, -- [out]
read_stb => read_stb_s, -- [in]
serialIn => serialIn_s, -- [in]
serialOut => serialOut_s -- [out]
);
Then instance top into your testbench.
-- Mike Treseler
Article: 88596Representing a manufacturer of development boards I am going offer you all the chance to have your say on what is goes into our new product Raggedstone1 and it's supporting modules. What I can tell is that the board is very cheap and takes what we think are some of the best attributes of the our existing Broaddown2 and MINI-CAN products. Like them it is also a Spartan-3 board (why another! - well you just have to wait and see when we start revealing features in about 4 weeks time). We have also included ideas based on existing customer feedback on the Broaddown2 and MINI-CAN products. We are now in the last week of layout and have found some small areas of board space that we might stick something on. So do your worst and suggest (politely please) what we might give you in features. Even if your idea is too big, or expensive, for Raggedstone1 itself then it may make our add-on module list or even the next higher end Broaddown3/4 product launches. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.ukArticle: 88597
I am trying to use chipscope to debug a simple design on the digilent spartan 3 starter board I insert a chipscope core using ISE 7.1 i synthesize my design and download it to the board via impact. now when I do analyze design using chipscope from within ISE chipscope starts, and I click the open cable icon in the upper left corner and the machine just sits for awhile, searching each LPT port (yes the parallel jtag cable is connected to the machine and the board) each of them time out i guess, and chipscope tells me: ERROR: Socket Open Failed. localhost/127.0.0.1:50001 localhost java.net.ConnectException: Connection refused: connect ERROR: Socket communication not open. any ideas? do i need to have the full version of chipscope for this to work? (i may have an evaluation version) thanks, -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 88598
We are looking at some research prototyping of IDS work. We are currently doing 1 Gbps prototyping on a current board, but are looking at 10 Gbps prototyping. Are there any FPGA boards available with: SRAM (a few MB minimum) A large FPGA 2 or more! 10 Gigabit ethernet interfaces. As a bonus, 2 10-GigE plus a PCI slot would be ideal. We MIGHT be able to get away with a single 10 GigE interface, but that would be far, FAR from ideal. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 88599
geoffrey wall wrote: > I am trying to use chipscope to debug a simple design > on the digilent spartan 3 starter board > I insert a chipscope core using ISE 7.1 > i synthesize my design and download it to the board > via impact. > now when I do analyze design using chipscope from within ISE > chipscope starts, and I click the open cable icon in the upper left corner > and the machine just sits for awhile, searching each LPT port > (yes the parallel jtag cable is connected to the machine and the board) > each of them time out i guess, and chipscope tells me: > > ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > localhost > java.net.ConnectException: Connection refused: connect > ERROR: Socket communication not open. > > any ideas? > Did you first close impact? Only one can be open at a time; they apparently compete for the port.
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