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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
About a year and a half ago I came across a book on digital systems design that I liked. I can't remember the title or the authors but in one of the last chapters it had an example of JPEG/MPEG codec. I didn't buy it because I was short on cash at the time, I think it was $130.00. Does anybody recognize the book I'm looking for? Thanks in advance, DerekArticle: 89426
Hi,
If all pwm are at same frequency, you need just one
pwm_cycle counter (8 mc) and 3 comparisons with
the desired PWM values (3 registers of 8 bit)
that makes a total of 32 mc just for that.
So... 32mc... forget nearly impossible !
64mc should be ok, (again not knowing what your state machine
will use ;).
About the code... if using one cycle counter, just pack all
the 3 pwm together it will be more straightforward...
if (clock='1' and clock'event) then
counter := counter +1;
if (counter>pwm_val_a) then pwm_a <= '1'; else pwm_a <='0'; end if;
if (counter>pwm_val_b) then pwm_b <= '1'; else pwm_b <='0'; end if;
if (counter>pwm_val_c) then pwm_c <= '1'; else pwm_c <='0'; end if;
end if;
very simple VHDL code for that, the pwm_* outputs will have the duty
cycle of the registers pwm_val_* / 255
...my view of the thing :)
---
my aplic. it was low QTY, I did not care about price etc.
lc.
"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> wrote
in message news:4kjgi15inu96ftvjg8hnl4tnh94q42d6o2@4ax.com...
> Based on your experience, do you think that three 8-bit PWMs could fit
> inside of a small CPLD (32 or 64 mcarocells)? The other funcionality
> that I plan to have in there is a state machine that drives the PWM
> inputs and perhaps some logic that detects the battery voltage level
> and chooses states accordingly. The more room that I have left over,
> the more involved I will make the state machine.
>
> The Max II that you used seems very similar to the Coolrunner II that
> I have been looking into. Was your project hi or low quantity? What
> was the cost of your MaxII at your quantity?
>
> thx again!
> frenchy
>
Article: 89427Eric - I hooked up some version of a Xilinx Spartan or Virtex part straight up to a USB 1.1 port and it worked fine over short distances. I didn't stress test it at all, I jsut got it working to the point that I could verify the USB peripheral code I was working on. So I think you should be able to get it to work. John ProvidenzaArticle: 89428
I have found a couple of books to be very good in learning VHDL and FPGA architecture, in general: 1. "VHDL Programming by Example" by Douglas L. Perry 2. "Circuit Design with VHDL" by Volnei A. Pedroni The former is a very good introduction to VHDL. It has a good referenece section in the back for later use, also. The latter is a more circuits oriented approach using VHDL. This concentrates more on circuit structures. Check the titles at Amazon or your favorite book outlet to get more detail on these and other books on the subject. Hope this helps. Dave "biot" <biot.spm@gmail.com> wrote in message news:1126712758.771274.22530@g44g2000cwa.googlegroups.com... > Thank you Vladislav !!! > My objective is to study both FPGA and computer architecture. I have > prelimnary knowledge about architecture and I am trying to design > simple 4-bit ALU /CPU using VHDL. I think i have virually completed it. > As a student I am in process of learing. I want to know more on FPGA, > Please suggest me where to start learning and also let me know your > recommendation. >Article: 89429
I have an FPGA design where the VHDL source code is a deliverable item
to the customer. One of the blocks in the FPGA must be protected so that
the customer can't see the source and modify it. The device is a
Virtex2-Pro.
I could obfuscate the VHDL identifiers, then generate a netlist, but
that doesn't seem to be very strong protection. I also have a picoblaze
processor in the design, so I'm not sure how well I can obfuscate the
block RAM contents. I could swizzle the address/data bits (as the TOCOM
5507VIP cable box did) when hooking up the block rom to picoblaze, then
write a script to convert the picoblaze object code to swizzled ROM init
files.
I heard a rumor (from a Xilinx FAE) that ISE 7 would have some facility
for protecting blocks of code in situations such as this, but I haven't
been able to find any info on the Xilinx website about this.
Peter Alfke, I know you have the answer :)
TIA
Urb
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Article: 89430Hi folks, I am starting to implement a simple PCI core using Spartan-II. I have already implemented the basic read and write transfer before I find this IDSEL signal which is used by PCI configuration transfers. My PCI board just needs to read and write data from/to a fixed address. There is no need for burst or back-to-back, nor plug-and-play. Do I need to implement the PCI configuration? How about plug-and-play? MikeArticle: 89431
Sorry about the format. I cut and paste from ISE into Xilinx's forum web site. Looks like it butchered the code. JTW "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3ore1nF7di2fU1@individual.net... > JTW wrote: >> Attached is my first cut at an address decoder. While it works I am not >> sure it's the best method. Also I am not sure why there are four 4:1 >> muxes in the design. >> >> Any help or ideas? > > Yes. Get a better text editor. > Need to eliminate the tabs and > add a few line feeds. > > -- Mike TreselerArticle: 89432
New Listing---
entity Decoder is
Generic ( ASIZE : integer := 32; BSIZE : integer := 12);
Port ( clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(ASIZE-1 downto 0);
reset_stb : out std_logic;
reg1_stb : out std_logic;
reg2_stb : out std_logic;
reg3_stb : out std_logic;
valid : out std_logic);
end Decoder;
architecture Behavioral of Decoder is
constant PMC_ADDR : std_logic_vector := X"00008";
constant RESET_ADDR : std_logic_vector := X"000";
constant REG1_ADDR : std_logic_vector := X"004";
constant REG2_ADDR : std_logic_vector := X"008";
constant REG3_ADDR : std_logic_vector := X"00C";
begin
process (clk, rst)
begin
if rst = '1' then
valid <= '0';
reset_stb <= '0';
reg1_stb <= '0';
reg2_stb <= '0';
reg3_stb <= '0';
elsif rising_edge(clk) then
valid <= '0';
reset_stb <= '0';
reg1_stb <= '0';
reg2_stb <= '0';
reg3_stb <= '0';
if (address(ASIZE-1 downto BSIZE) = PMC_ADDR) then
valid <= '1';
if (address(BSIZE-1 downto 0) = RESET_ADDR) then
reset_stb <= '1';
end if;
if (address(BSIZE-1 downto 0) = REG1_ADDR) then
reg1_stb <= '1';
end if;
if (address(BSIZE-1 downto 0) = REG2_ADDR) then
reg2_stb <= '1';
end if;
if (address(BSIZE-1 downto 0) = REG3_ADDR) then
reg3_stb <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
<JTW> wrote in message news:ee9048b.-1@webx.sUN8CHnE...
> Attached is my first cut at an address decoder. While it works I am not
> sure it's the best method. Also I am not sure why there are four 4:1 muxes
> in the design.
>
> Any help or ideas?
>
> Thanks, JTW
>
> entity Decoder is
>
> Generic ( ASIZE : integer := 32; BSIZE : integer := 12);
>
> Port ( clk : in std_logic; rst : in std_logic; address : in
> std_logic_vector(ASIZE-1 downto 0); reset_stb : out std_logic; reg1_stb :
> out std_logic; reg2_stb : out std_logic; reg3_stb : out std_logic; valid :
> out std_logic); end Decoder;
>
> architecture Behavioral of Decoder is
>
> constant PMC_ADDR : std_logic_vector := X"00008"; constant RESET_ADDR :
> std_logic_vector := X"000"; constant REG1_ADDR : std_logic_vector :=
> X"004"; constant REG2_ADDR : std_logic_vector := X"008"; constant
> REG3_ADDR : std_logic_vector := X"00C";
>
> begin
>
> process (clk, rst) begin if rst = '1' then
>
> valid <= '0'; reset_stb <= '0'; reg1_stb <= '0'; reg2_stb <= '0'; reg3_stb
> <= '0';
>
> elsif rising_edge(clk) then
>
> valid <= '0'; reset_stb <= '0'; reg1_stb <= '0'; reg2_stb <= '0'; reg3_stb
> <= '0';
>
> if (address(ASIZE-1 downto BSIZE) = PMC_ADDR) then valid <= '1';
>
> if (address(BSIZE-1 downto 0) = RESET_ADDR) then reset_stb <= '1'; end if;
>
> if (address(BSIZE-1 downto 0) = REG1_ADDR) then reg1_stb <= '1'; end if;
>
> if (address(BSIZE-1 downto 0) = REG2_ADDR) then reg2_stb <= '1'; end if;
>
> if (address(BSIZE-1 downto 0) = REG3_ADDR) then reg3_stb <= '1'; end if;
>
> end if; end if; end process;
>
> end Behavioral;
Article: 89433"Mike Zhang" <heibear@gmail.com> wrote in message news:9Z3We.933$Jm.252@newssvr27.news.prodigy.net... > Hi folks, I am starting to implement a simple PCI core using Spartan-II. I > have already implemented the basic read and write transfer before I find > this IDSEL signal which is used by PCI configuration transfers. My PCI board > just needs to read and write data from/to a fixed address. There is no need > for burst or back-to-back, nor plug-and-play. Do I need to implement the PCI > configuration? How about plug-and-play? If you're talking about some sort of embedded system where you know exactly what all the PCI devices in the system are and where they are in memory, I suppose you can "get away" with not bothering to implement configuration reads/writes. However, if this is supposed to be a standard plug-in PCI card for a PC, Mac, etc., you absolutely need to implement configuration reads/writes -- without them, the BIOS and OS will have no idea where you card is, so there's a chance some other card will overlay you card's address space and cause the system to malfunction, freeze, etc. Assuming you're getting paid for your engineering time, from what you're describing, I have a suspicion you'd be better off using some "off the shelf" PCI interface IC such as those from PLX or Cypress... or at least drop in Xilinx's (or someone else's) PCI core -- it'll quickly pay for itself! ---Joel KolstadArticle: 89434
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3or2mhF752qmU1@individual.net... > Remco wrote: > >> It is just that when they give you the freebie library of components >> why re-invent the wheel, right? > > Yes, the components are presented like > jelly beans in a candy store. > I didn't notice the handcuffs, the black box, > and the lawyer until the sugar wore off. > >> Of course, their %#$%$%$^@# component doesn't work for crap, so they >> basically steer you down a dark alley for a day or so. > > Even if they worked perfectly, > I don't need the complications of their > sim models and libraries. Running > synthesis and simulation using the > same code that I wrote and > understand is a huge advantage. > > Many of the components are one-liners anyway. > Even a fifo is just two counters > and a block ram template. > >> We had it integrated in a DMA mechanism and when stuff doesn't work, >> you don't immediately assume it is the commercially availbable >> component -- one would hope they test their junk before it is thrown >> over the wall (I guess they didn't). > > I don't doubt that some vendor testing is > done, but I don't have the source and I have > to redo it anyway in my own testbench. > >> So the first thing you assume is bad is your own code.. > > If I write my own code, I don't have to assume. > The problem is always in my own code, > but I am free to sim/edit/trace it as > much as I like. > >> I guess you get what you pay for. > > The only payment required is time and thought. > > -- Mike Treseler I haven't looked at their FIFO app note, but in general, the app notes are just that: notes to help you get an understanding of how to work with the device. Their IP (Coregen or $) will be expected to be more reliable and, presumably, application appropriate. For an asynchronous FIFO I need, I just ran Coregen and trust that it is doing it right. (Yes, I simulated it, and yes, I'll test it in the lab.) For another kind, where I need lots of FIFOs of varying sizes (perhaps dynamic), I need to create my own: and I've done it. Seems every application, though quite similar to a previous design, has some new quirks. JTW (Wright, not Weddick)Article: 89435
If you are not using the full resources of the APEX device then you will hopefully fit your design into a EP2C8 (8256 LEs). You should actually get better fitting with these newer devices due to more advanced routing. These have embedded multipliers too so if you use multiplication you'll save a ton of space. Hamish htoerrin wrote: > Eithout knowing anything about your application,... > > I believe that if you managed to run things in a 20KE, you will > definetly be able to run it in a CycloneII. My experience is that > CycloneII is more powerful than 20KE, although not as powerful as the > Stratix families. But as long as you don't intend to actively use the > DSP blocks, the large RAM's and lots of clocks, CycloneII will do the > job. > > HavardArticle: 89436
Terry Fowler wrote: > Has anyone had success in using the FSL Control bit? I have intermixed data read/write and control read/write with the FSL and it seems that once the FSL_Error bit is set in the MSR, it remains set even when the following accesses are matched. I have a design that uses 3 FSL M/S ports, and I use it without porblems. But yes, you *must* clear the FSL_Error bit. I use an instruction "msrclr r4,0x14" to read all flags into r4 and clear CY and FSL_error flags simultaneously ZaraArticle: 89437
Thank you DAVE Yeah I am following this book "VHDL Programming by Example" by Douglas L. PerryArticle: 89438
I'm designing a digital QPSK transmitter & receiver. At the transmitter, i'm using xilinx spartan3smb1500 to generate the QPSK samples. A DAC follows to give me a 1Vpp 1MHz signal. To transmit on my 2.4GHz antenna, i've used an rf upconverter board. At the receiver, the 2.4GHz antenna receives my signal and downconverts to 1Vpp 1MHz signal. An ADC samples at 50Msps, converts to 12-bit digital signal. This 12-bit input is splitted in two channels : one is fed to multiplier on channel I & another to multiplier channel Q. The other input of multiplier is a fixed NCO running at 1MHz sine for I-channel and 1MHz cosine for Q-channel. The output of the multiplier is fed to an FIR Filter to filter out the high frequency component and reveal the DC components. For the FIR filters, i'm using an MAC FIR Filter Core by xilinx. The coefficients are obtained from matlab fdatool. ; XILINX CORE Generator(tm) Distributed Arithmetic FIR filter coefficient (.COE) File ; Generated by MATLAB(R) 7.0 and the Filter Design Toolbox 3.0. Radix = 16; Coefficient_Width = 16; CoefData = 3b32,3ce5,3e3e,3f37,3fce,4000,3fce,3f37,3e3e,3ce5,3b32; Moving on, i need to design a Matched Filter to find the proper sampling instant for the symbols. Also, due to carrier offset, the phase is rotating. I understand that a phase detector, a loop filter and an NCO is required to recover the phase. Going one step at a time, Would appreciate if you can direct me to articles that explain practical implementations of a Matched Filter. Thanks, faaizal@gmail.comArticle: 89439
Thank you Joel! It sounds like there is no short-cut for me on this. Yes, I would have chosen another route had I not already spent so much time and effort on this one. I will stick with this plan and see what happen. Thanks! Mike Joel Kolstad wrote: > "Mike Zhang" <heibear@gmail.com> wrote in message > news:9Z3We.933$Jm.252@newssvr27.news.prodigy.net... > > Hi folks, I am starting to implement a simple PCI core using Spartan-II. I > > have already implemented the basic read and write transfer before I find > > this IDSEL signal which is used by PCI configuration transfers. My PCI board > > just needs to read and write data from/to a fixed address. There is no need > > for burst or back-to-back, nor plug-and-play. Do I need to implement the PCI > > configuration? How about plug-and-play? > > If you're talking about some sort of embedded system where you know exactly > what all the PCI devices in the system are and where they are in memory, I > suppose you can "get away" with not bothering to implement configuration > reads/writes. However, if this is supposed to be a standard plug-in PCI card > for a PC, Mac, etc., you absolutely need to implement configuration > reads/writes -- without them, the BIOS and OS will have no idea where you card > is, so there's a chance some other card will overlay you card's address space > and cause the system to malfunction, freeze, etc. > > Assuming you're getting paid for your engineering time, from what you're > describing, I have a suspicion you'd be better off using some "off the shelf" > PCI interface IC such as those from PLX or Cypress... or at least drop in > Xilinx's (or someone else's) PCI core -- it'll quickly pay for itself! > > ---Joel KolstadArticle: 89440
I'm beginning to question the organization of the fuse map in a HAL. It doesn't seem to be related to the datasheets. I've collected a lot of data so far and have outlined it below. Here is an x-ray of the actual package to show where the bond wires go: http://media.diywelder.com/images3/091405-HAL16R8chip2_Image412.jpg Here is the whole chip: http://media.diywelder.com/images3/091205-wholechip_IMGP2074.jpg Here is the map which is connected to "Pin 2", but the connections to the fusemap seem to indicate pin 3: http://media.diywelder.com/images3/091205-FusemapMap-IMGP2067.jpg Here is the fuse map schematic for pin 2. Note the locations of the input and feedback fuses. Can anyone give me any insight? Will I have to translate the location of the vertical fuse columns to what they "should be" in a GAL? Thanks, GrantArticle: 89441
I forgot to add the fuse map schematic for pin 2. Here it is: http://media.diywelder.com/images3/091105-PALdatasheetimage.jpgArticle: 89442
Terry Fowler wrote: > Has anyone had success in using the FSL Control bit? I have intermixed data read/write and control read/write with the FSL and it seems that once the FSL_Error bit is set in the MSR, it remains set even when the following accesses are matched. Hi Terry, The FSL Error bit in MSR is sticky and must be cleared if you want to reset it. GöranArticle: 89443
Hi Paul > Paul Hartke wrote: > You don't mention which specific OS version or windrvr you are trying to > use. As you probably know, only RHEL is officially supported. Various > folks--including myself--have played around and gotten FC and other > Linux distros to work. However, the further from RHEL the more likely > you are to have issues. I tried Centos 3 with ise71sp2 but i have got the same problems with undefined chips found. Since the automounter didn't work i switched back to debian sarge. > Just making sure you have seen Xilinx solution records 18612 and 20762. > Note that you certainly have to recompile the drivers as described for > any other version of Linux you are using. The problem with the version > numbers is discussed in SR2150 and has indeed been fixed in the latest > service packs. Ok, i have seen these, but 2150 isn't solved for me in sp4. I recompiled the whole drivers and tried even the jungo 7.0 version. I would be really interested which versions you have been using so i can rebuild it here. Thanks S.T.Article: 89444
they call me frenchy wrote: > On Wed, 14 Sep 2005 11:54:14 +1200, Jim Granville > <no.spam@designtools.co.nz> wrote: > > >>they call me frenchy wrote: >> >>>I am thinking of using a lowcost CPLD as a brain to do various logic >>>functions in addition to driving 3 separate PWM generators. The PWM >>>generators will receive their intputs from a state diagram that is >>>cycled through via a pushbutton. Sounds simple. Does anyone object >>>to using a very low cost CPLD for this? >>> >>>Obviously there are many more details involved, like the battery >>>powered, low power requirement (Coolrunner II, maybe)...but I just >>>wanted to have a general discussion at this point. >> >> The choice will depend on how many macrocells you actually need, >>and the cost relative to alternatives. eg there are many small >>uC that can handle 3 PWMs, but a CPLD might give speed or resolution or >>protection advantages. >> Lowest power 5V parts are Atmel ATF150xASL, and lowest power >>1.8V parts are Xilinx Coolrunner and Lattice Mach4000Z series. >>-jg > > > > Mr. Granville, > > Thank you very much for your response. Since this is my 1st > programmable logic project since college, I really dont know how many > macrocells I will need yet. I am in the process of learning VHDL > right now and coding the most efficient triple 8-bit PWM > imeplementation that I can. It is going well, but it will still be > 1-2 days before I can compile it and see how many macrocells are > required. (I am using Xilinx's free ISE 7.1 software). > > When you say there are many small uC that can handle 3 PWMs, can you > give me a couple of specific examples so that I can compare their > cost/functionality? I admit to you that although I graduated with an > EE degree, I have been a musician and running a recording studio for > the last several years. I am just now getting back into the EE loop, > but I love it and am moving forward quickly. Unfortunately, the fool > in me has no idea what you are referring to when you say uC. It > probably means microcontroller, but I have never used one and I dont > know if they are re-programmable like CPLDs are. The reason that I > was looking into the Xilinx Coolrunner II is because I need ultralow > power consumption and I found the price on their smallest one > (32macrocells) to be $0.85 at quantities of >100k. I hope I can fit > it into the smallest one! > > thx again, > frenchy Unless you have complex timing requirements, a small micro would be the best for making 3 PWMs. Get a small msp430 processor - they are cheap, easy to work with, and have good free tools (the gcc port is excellent, and there are free versions of ImageCraft and IAR tools for limited program sizes).Article: 89445
Yo there,
Me think if you close the if statement, you should be able to remove
the 4 to 1 Mux...
if (address(ASIZE-1 downto BSIZE) = PMC_ADDR) then
valid <= '1';
end if;
Article: 89446Hi all, I just received a copy of ISE7.1, I removed the old 6.3 and installed it. I also installed the service pack 1 I had downloaded months ago. Now I'm experimenting lots of problems (ISE7.1 is a very crap, it should be an alpha release, not a 'stable' version), so I think I'll try installing newer fix. I read that service packs are cumulative, can I install the last service pack even if I already installed service pack 1? do you reccomend this operation? (I had some problems with a 6.1 release, after installing service_pack/ip_update/mx_lib_update I couldn't simulate some projects.Article: 89447
Thanks, yes I installed the EDK and all the servicepacks. They didn't give me any trouble, luckely:)Article: 89448
Hi all, Does anyone has implemented a SATA link on Xilinx V2Pro to connect to a hard disk drive ? Indeed, we have the Xilinx XUP V2Pro Dev board from Digilent and it has a SATA connector. So I'm wondering if one can control a hard disk drive from this SATA connector. Furthermore, I would like to mount the disk on linux running on the PPC. I've already compiled and installed an own driver on linux and I'm wondering if it would be possible to mount a SATA hard disk drive. Do you have any information about such development ? Thanks a lot for your help StéphaneArticle: 89449
I heard quite a lot about the Viva development environment last week at the MAPLD 2005 conference in Washington DC. A lot of people had good things to say about it. It seemed to me like Starbridge are currently focussing on porting Viva to different hardware platforms. This leads to ask the question: are Starbridge no longer in the hardware business? What does this leave the Hypercomputer? What are people's experience of using either Viva or the Hypercomputer?
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