Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Ram wrote: > Hi, > > > Does ISE 7.1i use the same install code for Windows as it does for Linux? A > Xilinx rep told me they are the same. > Yes, they are the same.Article: 89326
Jon Schneider wrote: > Is Kingston SDRAM really that bad ? I agree with the other posters in this thread, and would tend to suspect my own design before suspecting the SDRAM... .. but ... A few weeks ago we bought three new PCs for the office. All with 2GB SDRAM, and all but one of the 1GB modules was some brand which I have never heard of, and can't recall (the last was a Corsair). I started having problems with my PC rebooting for no reason. Starting running a comprehensive memory test and it showed hundreds of bit errors overnight. The other guys here ran the same tests and, although not all quite as bad, all had bit errors in an overnight test. We went back and exchanged the RAM (including the Corsair, which did *NOT* fail) for another brand, and re-ran the tests. *Zero* errors on all 6 modules. Now that *could* be put down to crappy mobo design (they're identical machines) or bad SDRAM, but it is food for thought... Regards, MarkArticle: 89327
Hello, I bought this book "Verilog Computer-Based Training Course" CD-ROM and was trying to install Modelsim-Altera 5.5b. Exemplar LeonardoSpectrum and Quartus II 1.1 web edition tools that came with this book. The book description says the tools has 1 year licensing for modelsim and leonardo spectrum. Here is the link to book description. http://www.ece.neu.edu/info/verilog/vcbtc/Actual/product_description.htm The manual that came with the cd-rom says that I can get the license for the above tools from Altera's web-site. And author's website that has licensing instructions says that would be an option for Verilog CBT users for getting the license. but there is no option (may be the book's website needs to be updated...who cares I just want the solution as I spent money on this..!) Here is the link to the licensing info given in the webiste that supports this book. http://www.ece.neu.edu/info/verilog/vcbtc/Actual/licensing.htm Now Quartus II works with the license that I got from Altera webiste for Quartus II webedition free. (I dont need this, I can download it for free as a evaluation software from Altera, I dont need to spend money..) But I cannot run the modelsim-altera with the same license, and I am not sure how to obtain the license for 1 year. Can anyone please..please..let me know how can I obtain license for modelsim-altera and leonardo spectrum for one year? I spent lot of money on this book, and I am facing problems now, not good..!! I have emailed the author of the book whose email is in the support page of the book, but no use, and no reply. I also talked to the Mcgraw-hill book company's (the publisher) tech support. They said they will investigate and let me know, but I am not sure how much time they will take..! Finally I emailed the Altera. Lets see if they can help..!! But any help you can give me would be really appriciated OR if any one had similar problem and found a solution, please let me know..!! Thank you very very much. -VenkatArticle: 89328
FWIW, I had to use different registration code for windows and linux. Jim "Ram" <r_fpga_dev@yahoo.com> wrote in message news:AflVe.5881$Gh.4642@tornado.socal.rr.com... > Hi, > > I've read through the archives for notes and hints on installing ISE 7.1i > for Linux. > > I got curl, portmap, motif, etc all installed. The installer now comes up. > > However, when I enter in the Registration ID, it keeps telling me that it's > invalid. > > Does ISE 7.1i use the same install code for Windows as it does for Linux? A > Xilinx rep told me they are the same. > > Any help would be appreciated. This is very frustrating! > > Ram. >Article: 89329
Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would like to know how many months it will take me to fully design it. As a novice i would like to know few suggestions and references for my project. I need help. I don't know from where to start.Article: 89330
Synthesis tools have nothing to do with the number of IOBs. The number of I/Os is determined by your design. One way to reduce I/O count is multiplexing. HTH, Jim "geoffrey wall" <wallge@eng.fsu.edu> wrote in message news:dg4n2j$dqk$1@news.fsu.edu... > how can you reduce the number if IOBs a design uses > during synthesis? > > thanks > > -- > Geoffrey Wall > Masters Student in Electrical/Computer Engineering > Florida State University, FAMU/FSU College of Engineering > wallge@eng.fsu.edu > Cell Phone: > 850.339.4157 > > ECE Machine Intelligence Lab > http://www.eng.fsu.edu/mil > MIL Office Phone: > 850.410.6145 > > Center for Applied Vision and Imaging Science > http://cavis.fsu.edu/ > CAVIS Office Phone: > 850.645.2257 > >Article: 89331
I've had success reading the fuse map! :) It took 200x and a decent microscope. Still holding the cheap digital camera to the eye piece, but hey...it works. :) You can see in the images below that a HAL has all the fuses, but some have been cut. So my guess would be rather than them being manufactured with a pattern, they are manufactured 100% connected and then mechanically cut later? Here is a huge picture of the entire silicon. The fuse map is the big rectangle array to the left. 50x http://media.diywelder.com/images3/091205-wholechip_IMGP2074.jpg Here is a 20pin DIP with an arrow pointing to the map. Its amazing the scale inside these chips...and they're 30 years old! :) http://media.diywelder.com/images3/091205-HALchip_IMGP2078.jpg Here is one 8x32 256 fuse array with the inputs and flip flop results annotated. 200x http://media.diywelder.com/images3/091205-FusemapMap-IMGP2067.jpg A shot of the bond wires, 200x. http://media.diywelder.com/images3/091205-Pins_IMGP2070.jpg MMI logo 200x http://media.diywelder.com/images3/091205-MMILogo_IMGP2051.jpg Those pictures were of the ASG, Apple Sound Generator, in the 128k to Plus macintosh. I'm going to write a program to visually read the fusemap so that I don't have to. Pretty cheap, $45 for a chemical decap and then a few hours writing down 1s and 0s. ;)Article: 89332
Neil Glenn Jacobson wrote: (...)> The latest software will work with either the Xilinx Parallel Cable IV > or the Xilinx Platform Cable USB on Linux. As you might guess from the > names, the former is a parallel port connected cable and the latter a > USB port cable. The performance of either cable will be a substantial > improvement over the xchecker cable. > I am user of both cables, and I have to make a note: If you are not sure that your parallel port is 100% ECP compatible, go for the USB cable. It is more expensive, but it works everyhere ZaraArticle: 89333
biot wrote: > Hi members, > I am a student and completely new to FPGA. I am learning VHDL. My > objective is to implement FFT in spartan-3 starter kit. I would like to > know how many months it will take me to fully design it. As a novice i > would like to know few suggestions and references for my project. I > need help. I don't know from where to start. > The answer depends mainly on you and you ability to grab new tools and to analyse the problem. FFT is a repetitive design, but it consumes lots of FPGA resources. Now, what I think (worst case and the time schedule is not linear, every task is intermixed with the others): a) learning the tools (VHDL, ISE, and ModelSim) to get the profficicency required: 1.5 months b) dividng the FFT in separated design blocks: 0.5 months c) writing the VHDL models, analysing and correcting: 1 .5 months Important: you have to select the correct Sparatan 3 chip with enough resources for your task and with a footprint according to the PCB technology you have available (not everyone can use FPBGA) Finally, there is an optional step d): This Eureka! you find after doing most of the work, that makes you restart form scratch... 1.5 extra months Anyhow, I repeat this is a worst case evaluation. As you are a student, it should be easy for you to learn the use of VHDL withn Xilinx ISE and Modelsim faster than that. The rest depends on your talent and training, which I will judge by no means. zaraArticle: 89334
Hi,
I seem to be getting a higher P&R speed (I put a constraint on the only
clk I have in the design) than that I got from synthesis. Sometimes by up to
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2
1000 -4.
Thank you
Adrian
Article: 89335Philip Freidin <philip@fliptronics.com> writes: > The real speed killer for Anti-fuse is what they never talk about in > their comparisons. They always show the size of the Anti-fuse versus > the "SRAM" pass transistor (or pass gate) and say the far smaller > size leads to lower capacitance and therefore higher speed. This is > true. What they fail to mention is that to program the Anti-fuse > they need a pair of power transistors either side of the Anti-fuse > to sink enough current through the fuse to program it. They are big, > capacitive, at the end of long shared wires, and they are still there > after programming is done. The size of these transistors is so big, > that they kill most of the area advantage that came from the Anti- > fuses being small. Wow, thank you Philip; this was not only the information I was looking for, but the little-known reason why it is so. Thanks! - aArticle: 89336
Here's a benchmark for PAR (high effort level) running on two different CPUs. The design utilized about 40% of an XC2V4000-5 and had some difficult-to-meet timing constraints. PAR's peak memory usage was ~500 MB. Intel Pentium D 830 (3.0 GHz), 2 GB RAM: Total CPU time to PAR completion: 2 hours 32 mins AMD Athlon 64 4000+ (2.4 GHz), 2 GB RAM: Total CPU time to PAR completion: 1 hour 2 mins I was blown away by the result. I was expecting a modest speed increase with the AMD- maybe 1.3x, if you go by the model number- but certainly not 2.5x. Based on this benchmark, the AMD CPU should actually be called a 7500+. :) The Pentium is a dual core and the AMD is a single, but the Xilinx software utilizes only one core so this is a fair comparison of raw processor speed. The Pentium probably gets killed by its deep pipelines. I'd guess that PAR, like most real-world apps, consists mainly of spaghetti code rather than regular loops processing masses of similar data. So the Pentium spends a lot of its time flushing pipelines because of mispredicted branches and such. It probably suffers from its higher memory access latency as well. It sure would be nice if Xilinx could made their software multithreaded... then an Athlon X2 4800+ would really scream. As it is, I'd guess that an Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently possible. -PaulArticle: 89337
Ram wrote: > Hi, > > To get started with Microblaze, I'm attempting to do a simple filtering > application on audio, real-time. Audio is CD-quality, 44.1 kHz, 16-bits. > I'm trying to handle multiple audio streams (8 to start with). I'm > thinking about buffering 16 samples per channel. > > I'm trying to figure out what structures to use to facilitate data transfer > of the audio samples from on-board memory into the filtering structure I'm > trying to create. > > If this were a normal processor, I would use DMA to transfer from the > external memory to a FIFO and do the processing. > > What should I consider doing with Microblaze? Create an OPB master to > transfer from memory controller to an internal FPGA FIFOs? > > Use an FSL? > > Suggestions are appreciated. > > Ram. > > > Hi, 8 channels with 16 bits data at 44.1 KHz requires 8*(16/2)*44100 = 705600 Kbyte/s If you run your external memory as 32-bits you need 176400 transfer/s. If the system is running at 75 MHz, you need a transfer every 425 clock cycle. I doubt that the memory transfers gonna be your bottleneck in the system. More important is where is the processing done, in MB or in HW? What kind of processing of the audio data are you planning to do? If you would need more bandwidth, I would go for the MCH(FSL) that exists on our memory controller now. It's basically a pipe from your module to the external memory. MicroBlaze is using 2 of these for getting faster cachelines accesses. GöranArticle: 89338
Generally we use Athlon64 based machines and are very impressed. We have not done a comparision recently but we have found on previous benchmarking is that some parts of the process are better done on different processors. So if you have a really big design you may want to split the work better 2 machines with one being Intel based the other AMD. I'm sure that some you "geek" script writers could figure a script to automate this. It would be interesting to try a single core Pentium Extreme against the FX-57. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Paul Gentieu" <pg8192@yahoo.com> wrote in message news:ee900d0.-1@webx.sUN8CHnE... > Here's a benchmark for PAR (high effort level) running on two different > CPUs. The design utilized about 40% of an XC2V4000-5 and had some > difficult-to-meet timing constraints. PAR's peak memory usage was ~500 MB. > > Intel Pentium D 830 (3.0 GHz), 2 GB RAM: Total CPU time to PAR completion: > 2 hours 32 mins > > AMD Athlon 64 4000+ (2.4 GHz), 2 GB RAM: Total CPU time to PAR completion: > 1 hour 2 mins > > I was blown away by the result. I was expecting a modest speed increase > with the AMD- maybe 1.3x, if you go by the model number- but certainly not > 2.5x. Based on this benchmark, the AMD CPU should actually be called a > 7500+. :) > > The Pentium is a dual core and the AMD is a single, but the Xilinx > software utilizes only one core so this is a fair comparison of raw > processor speed. > > The Pentium probably gets killed by its deep pipelines. I'd guess that > PAR, like most real-world apps, consists mainly of spaghetti code rather > than regular loops processing masses of similar data. So the Pentium > spends a lot of its time flushing pipelines because of mispredicted > branches and such. It probably suffers from its higher memory access > latency as well. > > It sure would be nice if Xilinx could made their software multithreaded... > then an Athlon X2 4800+ would really scream. As it is, I'd guess that an > Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently > possible. > > -PaulArticle: 89339
Hello Everyone I am now trying to simulate gate level evolution in software. I was unsure about the formation of my chromosome string. I would be using an evolutionary approach to design a circuit. I have read documents on Multi Expression Programming(MEP) and Gene Expression Programming(GEP). The examples are quite good but still i feel its a challenege getting a valid equation from a random generated string like - "(a&b))|c!d(b)" I am currently generating a random string for the initial population of the chromosomes. but major problem is how can i make it valid. Someone suggested that i should use the concept of lexical analysis used with compiler design. I am really confused regarding what approach to adopt. It would be great if someone could guide me. I have read the MEP gate evolution example from C#corner I feel its very complicated. Ankit Parikh Manukau Institute of TechnoogyArticle: 89340
In my actual design I'm using an Altera APEX20KE with 200,000 gates. In my next (larger) design I want to use an newer and maybe cheaper FPGA. I don't want to change to an other vendor, I intend to use an Altera FPGA. Which one shall I use??? My first choice was a CYCLONE, which is much cheaper, but is this familie powerful enough compared to an APEX20KE??? My second choice was a STRATIX, which is rather expensive??? Thank you for your help, ManfredArticle: 89341
I also had similar problem before. Problem was not the design itself, but the 'test bench'. Maybe your problem is somewhere in test bench, for example, name of component, how to instantiate it.Article: 89342
Very interesting I really doubt its the branch behaviour even though the Athlon series has always been good on office type twisty apps. For branchy code segments that fit in the I cache, these days the branches almost come for free and guess right more often than not. I'd hazard a guess it has more to do with the data set being very large and missing the L1, L2 and TLBs way too often, "poor locality of reference" , even 1% misses, maybe less maybe enough to wreak havoc. It not difficult to create a simple data structure that holds millions of items in a hash table and see even an Athlon xp2400 give up 300ns avg accesses to each entry if all accesses appear random.rather than the naive 1ns its L1 cache can actually do. You can plot a graph of open random address width from 6bits to 24bits and watch execution time go from 1n to 4ns and then roughly stepping 30ns 100ns 300ns for x[i] when i is coming from any old random no generator and masked by width field. Measured on an xp2400. If this simple test were run on various cpus, we could see how the caching really works for graduating locality disaster cases and choose accordingly. Now EDA software doesn't deliberately do this, but might get some of the same effect unintended simply by having to walk immense graphs and trees. Think about it, draw a graph with millions of nodes and try to label in such a way that it can be traversed with mostly low address bit changes (high locality) when the nodes in the graph are allocated completely in random fashion. Then think, how many operations actually get performed on each link list traversal, a lot of the time it might be just passing through looking for something, the worst possible situation, all fetch no work. I don't imagine there is much EDA code that looks like beautiful DSP media codec stuff with super straight line high locality SSE tuned code. I could be all wrong, but I thinks it the Memory Wall effect and the Opteron maybe does a better job of recovering. That also means a cpu that concentrates on that aspect desn't even need a clock advantage as long as it tolerates poor locality better. I wonder if its possible to get stats from the cpu performance hardware that shows what the cpu is really doing in memory, bit out of my league. I wonder if the EDA guys just crank out code or do they ever measure algorithms on different x86 hardware at the cache level, curious? I also wonder how much FPU is actually used and how so?. On a threaded cpu designed to work with threaded memory where there is little memory wall (latency tolerence all around), it doesn't take much hardware to design a processor element in FPGA that can match Athlon xp300, and 10 or so ganged together can then match xp3000 but you get 40 odd threads to fill instead of waiting on cache misses. Me, I'd rather fill the threads (occam style) than wait, but most are not of that opinion (yet). Now if EDA ever becomes highly concurrent, (some have done this in VLSI EDA from simulation to P/R) it does make possible some real speed ups when real threading becomes pervasive in cpus (not this 2,4 thread nonsence). johnjakson at usa dot ... transputer2 at yahoo dot ...Article: 89343
Adrian wrote: > Hi, > I seem to be getting a higher P&R speed (I put a constraint on the only > clk I have in the design) than that I got from synthesis. Sometimes by up to > 10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2 > 1000 -4. > > Thank you > Adrian I have seen that too on occasion, usually the very next change to the code fixes it right away:-) JJArticle: 89344
Yes it's weird. I had three CD's: two of them said CD 1, and one said CD 2. The "second" CD1 was said to be the "international" version. However, it gave "missing file" errors when it started to install a certain part (can't remember what), but as far as I could see it was installing exactly the same things that the "other" CD1 already installed. So I only installed from the first CD1 and CD2. I'll try to reinstall when I have time. For the moment I gave up on 7.1 and I'm still working with the 6.3 version. Stupid that I didn't realize this before....ugh....got a lot on my mind lately :) Anyone else had this problem too? (Or at least could give me some info about those weird two CD1's) I would appreciate it.Article: 89345
Stephane wrote: > How to manage several ucf files when working with different projects on > the same chip? > > i.e. top_pads.ucf, that is always the same > and top_area_1.ucf or top_area2.ucf > > any 'include' directive? No, but you can just use your build script to concatenate them into a single file. The order doesn't matter. Regards, AllanArticle: 89346
Hi Biot, have a look at www.opencores.org The projects section contains different FFT implementations. It is up to you, whether you just copy it, or whether you regard it as a starting point for your own steps. Jens biot wrote: > Hi members, > I am a student and completely new to FPGA. I am learning VHDL. My > objective is to implement FFT in spartan-3 starter kit. I would like to > know how many months it will take me to fully design it. As a novice i > would like to know few suggestions and references for my project. I > need help. I don't know from where to start.Article: 89347
Thank you JARA and JensArticle: 89348
Hello, Adrian, Duane, Jim: Thanks for the info. So far the unofficial word is 2:1, Windows code Reg ID will work on Linux. To Xilinx guys here: Any official response? The Registration ID that I was given by the Xilinx FAE DOES work on Windows, but continues to fail with Linux. The FAE says the Windows codes should work on Linux but has no official experience with the Linux version. Any other things people suggest I look at? I'm using Kubuntu Linux (Ubuntu) with a custom 2.6.12.2 kernel with SMP. Thank you all. Ram.Article: 89349
Hello Adrian, and Göran, > If the system is running at 75 MHz, you need a transfer every 425 clock > cycle. > > I doubt that the memory transfers gonna be your bottleneck in the system. Agreed. > > More important is where is the processing done, in MB or in HW? > What kind of processing of the audio data are you planning to do? The current idea is completely in HW. Simple IIR filtering of each channel and programmable summing (similar to the mixer idea Adrian mentioned). MB is only involved in managing base memory pointers to audio streams, so if an audio stream is to be changed over, MB controls this. Some logic (DMA process?) monitors the base address and continues to fetch and fill the FIFOs. The main purpose of MB though is to make it easy to control/alter the coefficients and do other house keeping chores (display, control, etc). Getting uCLinux would be great as this adds a network stack and a whole host of possibilities. > If you would need more bandwidth, I would go for the MCH(FSL) that > exists on our memory controller now. It's basically a pipe from your > module to the external memory. MicroBlaze is using 2 of these for > getting faster cachelines accesses. As you pointed out, the bandwidth is probably not the critical issue. Really what I was getting at is, with a MB, OPB_Memory_Controller (SDRAM or DDR), how should I shuffle data from the external memory to my logic? At first glance, I did not see any traditional DMA type of logic which could be used to transfer from the external memory (via OPB_Memory_Controller) to internal FIFOs. Have I missed something? Thank you! Ram.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z