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Hi guy, where i can download the edk service pack never product registration? thanks bssArticle: 89376
I am thinking of using a lowcost CPLD as a brain to do various logic functions in addition to driving 3 separate PWM generators. The PWM generators will receive their intputs from a state diagram that is cycled through via a pushbutton. Sounds simple. Does anyone object to using a very low cost CPLD for this? Obviously there are many more details involved, like the battery powered, low power requirement (Coolrunner II, maybe)...but I just wanted to have a general discussion at this point. thx, frenchyArticle: 89377
Hello, I assume you are using an Apex 20K200E which has 8320 LEs. Both the Cyclone EP1C20 and EP2C20 have more than twice the number of LEs and RAM. The EP1C20 has slightly more resources but the EP2C20 has embedded multipliers. You will have to look at your other project requirements to see which is best. There are larger members of the Cyclone II family in case you need even more resources. Daniel Lang "Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message news:43268449$0$12642$3b214f66@tunews.univie.ac.at... > In my actual design I'm using an Altera APEX20KE with 200,000 gates. > In my next (larger) design I want to use an newer and maybe cheaper FPGA. > I don't want to change to an other vendor, I intend to use an Altera FPGA. > Which one shall I use??? > My first choice was a CYCLONE, which is much cheaper, but is this familie > powerful enough compared to an APEX20KE??? > My second choice was a STRATIX, which is rather expensive??? > > Thank you for your help, Manfred >Article: 89378
jai.dhar@gmail.com wrote: > Regarding the PC RAM issue, is anything being overclocked? That seems > really odd that they would mostly all fail... on all the PC's for > that matter. I would try the RAM in another PC and see what happens. No, these are office PCs so everything is factory settings on Gigabyte mobos. The RAM is long gone - returned to the shop for replacement. And going from 100+ errors overnight (6 modules on 3 mobos) to zero errors with the new RAM is pretty damning evidence IMHO. Regards, MarkArticle: 89379
Thanks a lot Valdislav and Sean. You people made my day. Regards WilliamsArticle: 89380
they call me frenchy wrote: > I am thinking of using a lowcost CPLD as a brain to do various logic > functions in addition to driving 3 separate PWM generators. The PWM > generators will receive their intputs from a state diagram that is > cycled through via a pushbutton. Sounds simple. Does anyone object > to using a very low cost CPLD for this? > > Obviously there are many more details involved, like the battery > powered, low power requirement (Coolrunner II, maybe)...but I just > wanted to have a general discussion at this point. The choice will depend on how many macrocells you actually need, and the cost relative to alternatives. eg there are many small uC that can handle 3 PWMs, but a CPLD might give speed or resolution or protection advantages. Lowest power 5V parts are Atmel ATF150xASL, and lowest power 1.8V parts are Xilinx Coolrunner and Lattice Mach4000Z series. -jgArticle: 89381
Hi everybody, I'm working on a small project in which we want basically to filter Input data (Input Data Rate = 105Mhz) with a FIR filter (64 coefficients). I've forseen to use the MAC FIR IP provided by Xilinx but there could be a problem in the way input data are sampled. Indeed, MAC FIR IP provides an output named RFD(Ready For Data) which indicates when the MAC FIR can accept new data. Does that mean ND (New Data signal) can't be stay at '1' to put new data in FIR at each rising edge of clock sample (105 MHz)? Since my Input data flow is unbroken, how can I do to process this flow in real time? Is there other free FIR IP more suitable for my application? Thank you in advance for your answers. PS: I'm a french guy, so I hope my english is not too bad and you will able to understand what I mean ... :oops:Article: 89382
I've done that 2 times already ! First was a dual stepper-motor controller (on a EPM7064), Second it was a GPS frequency control, dac output was a PWM filtered (on a EPM3064 and later on a MAXII) These are the kind of things that usually don't take a lot of LE's and fit well inside small CPLD's But of course I know little about what else you need besides the PWM... lc. "they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> wrote in message news:takei1lj59t5dd42nmhh85ajjlh4ka05ed@4ax.com... >I am thinking of using a lowcost CPLD as a brain to do various logic > functions in addition to driving 3 separate PWM generators. The PWM > generators will receive their intputs from a state diagram that is > cycled through via a pushbutton. Sounds simple. Does anyone object > to using a very low cost CPLD for this? > > Obviously there are many more details involved, like the battery > powered, low power requirement (Coolrunner II, maybe)...but I just > wanted to have a general discussion at this point. > > thx, > frenchyArticle: 89383
Hello all,
In my design there is a possibility (its dynamic) that a register
may get connect to inputs of 172 gates. Is this possible on Virtex E or
any other xilinx FPGA. And is it possible in the real silicon i am
asking about industry standards. Or is there any other way i can achive
this. By changing my design etc.
Sumesh V S
Article: 89384Hi All, i request some of you guys who worked or having knowledge on imlementation of ARM core with MBA bus in FPGA.Basically we are designing two FPGAs in single card with the functionality given below. we are are trying to implement ARM926 IP core and USB2.0 IP CORE in one of the Virtex4 FPGA. Due some constraints we are planning to implement some other IP CORES in an another FPGA with ARM interface to this IPCORE via AMBA bus from the 1st FPGA. Now the issue is that if there are any signals of AMBA bus which have any latency issues if we connect the AMBA bus from one FPGA to Other FPGA with some IP core(Like PCI express and ethernet MAC). please direct us in this issue. Feel free to ask if any other informaton is required from my side. regards, S.RANGA REDDYArticle: 89385
vssumesh wrote: > Hello all, In my design there is a possibility (its dynamic) that a > register may get connect to inputs of 172 gates. Is this possible on > Virtex E or any other xilinx FPGA. And is it possible in the real > silicon i am asking about industry standards. Or is there any other > way i can achive this. By changing my design etc. Sumesh V S I have a reset signal that is synchronised by 4 FF's with a fan-out of 2,700-odd. However this signal is used as an async reset so it's probably going to preset/clear rather than Din ports... I could imagine you could reduce the fan-out (if required) with a tree of FF's, if you can tolerate the added delay. Regards, MarkArticle: 89386
Mark McDougall wrote: > I have a reset signal ... Sorry, I'm using an Altera part... Regards, MarkArticle: 89387
Ankit, to be honest, i have not the slightest idea about MEP or GEP or the like. But at my university days i wrote a Pascal program that would take a input string like the one that you present and reduce it to a simpler form. The aim of the program was to find out whether a expression was a "Tautologie" (Always true, independand of the values of the input variables) or not. The program did this not by trying out all input variables settings but instead by symbolical manipulation according to rules like "a|!a may be reduced to TRUE" or "a&!a may be reduced to FALSE". I guess from that experience i have a certain understanding of what you are gaining for. And i guess the people who told you about parsing, lexical analysis and compiler design were quite right! If you have a totally random expression you will most probably need to perform lexical analysis to find out whether it is a valid expression. However, if i understand your question right it is not your true aim to make a random expression a valid expression. Instead it seems what you need is a valid random logic expression. I suggest, then that this is what you should do: Not use a random generator to generate character sequences but use a random generator to generate complicated logic expressions from simple logic expressions. This will need some programming stuff too but could be easier than analyzing a existing string. Best regards Ulrich Bangert <apsolar@gmail.com> schrieb im Newsbeitrag news:1126597459.316081.225600@z14g2000cwz.googlegroups.com... > Hello Everyone > I am now trying to simulate gate level evolution in software. I was > unsure about the formation of my chromosome string. I would be using an > evolutionary approach to design a circuit. > I have read documents on Multi Expression Programming(MEP) and Gene > Expression Programming(GEP). The examples are quite good but still i > feel its a challenege getting a valid equation from a random generated > string like - "(a&b))|c!d(b)" > I am currently generating a random string for the initial population of > the chromosomes. but major problem is how can i make it valid. > Someone suggested that i should use the concept of lexical analysis > used with compiler design. > I am really confused regarding what approach to adopt. > It would be great if someone could guide me. > I have read the MEP gate evolution example from C#corner > I feel its very complicated. > Ankit Parikh > Manukau Institute of Technoogy >Article: 89388
my aim is to develop a reconfiguration application thats able to reconfigure a fpga. i don't want to use more configuration files / bitstreams, which are stored in memory and loaded on demand.Article: 89389
Eithout knowing anything about your application,... I believe that if you managed to run things in a 20KE, you will definetly be able to run it in a CycloneII. My experience is that CycloneII is more powerful than 20KE, although not as powerful as the Stratix families. But as long as you don't intend to actively use the DSP blocks, the large RAM's and lots of clocks, CycloneII will do the job. HavardArticle: 89390
Ram wrote: > Hi Göran: > > >>I would connect the filtering modules as FSL modules to MicroBlaze. >>It makes the movement of data much easier. >>If the data don't need to be touch/modified after your filtering it can >>pipe the data directly to your audio interface with more FSL channels. > > > Would this not end up using 100% of the CPU for simple memory move > operations? > > Ideally MB should be able to continue executing out of cache (while memory > transfers are occurring) and resume when memory becomes available, no? > > The concern is long-term, if more audio channels are added that MB simply > becomes an expensive memory controller. > > I am still thinking what other possibilities exist. > > Thanks. > Ram. > > > Hi, That is a nice thing with FSL. You could then tie FSL to the memory controller or your DMA controller without the need of changing anything in the FSL modules. The FSL module doesn't know who sends the data. This will make it fast to get an initial design and also make it easier to expand for more performance in the future. GöranArticle: 89391
Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-3 starter kit. I would like to know how many months it will take me to fully design it. As a novice i would like to know few suggestions and references for my project. I need help. I don't know from where to start.Article: 89392
there are quite a few spartan 3 demo boards out there with LCD displays, 100 base-T and USB on board... sounds like a simple solution ?? I just got one from Memec for less than a grand with a spartan 3 1500 Of course .. you have to build software and hardware drivers for each interface. Not exactly trivial to a newbe. Simon "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:43272f2a$1@clear.net.nz... > Le.Wang wrote: > > > Hello everyone, > > > > I am a totally newbie with FPGA, I really need some help for our project. > > > > We have 24 simple digital signals, and we want to build a FPGA-Board to take > > count of the pulses of each digital > > signal, so it runs just like 24 counters, and the results should be > > transfered to PC with a USB-Interface. > > > > I have found pretty much information about FPGA, but I really don't know > > which is suitable for this job. Could someone give me some suggestions (e.g > > which type, which mark, the price and so on)? I very appreciate for any > > help. > > > > Le > > P.S: What we need is a design-kit, because maybe we could program more > > functions on it in the future. > > You need to specify the width ( how many bits ) in each counter and > the expected MAX pulse rate. That tells you how much resource you need > for the front end, at a minimum. > Then, you might want to buffer this, so a read captures the whole > counter into another latch - this avoids counter-change-during-read > problems. > This might fit in larger CPLDs like Altera MAXII or Lattice MachXO. > [The MachXO can support their Mico8 small CPU ] > > For the back end (USB) you could use a small uC with USB, or a > USB-Serial chip (FDTI, SiLabs etc). > Maxim have posted data on a nice MAX 3420 SPI-USB bridge device, > that needs minimal SW support, and is much faster than the RS232 ones. > > -jg >Article: 89393
Thanks a lot! :-) Le "Le.Wang" <lewang@weh.rwth-aachen.de> schrieb im Newsbeitrag news:3oo8m2F6rvspU1@news.dfncis.de... > Hello everyone, > > I am a totally newbie with FPGA, I really need some help for our project. > > We have 24 simple digital signals, and we want to build a FPGA-Board to > take count of the pulses of each digital > signal, so it runs just like 24 counters, and the results should be > transfered to PC with a USB-Interface. > > I have found pretty much information about FPGA, but I really don't know > which is suitable for this job. Could someone give me some suggestions > (e.g which type, which mark, the price and so on)? I very appreciate for > any help. > > Le > P.S: What we need is a design-kit, because maybe we could program more > functions on it in the future. >Article: 89394
The truth is (e) none of the above... if you order 500,000 you can have the first shipment in 4-6 weeks if you order one then its 12-16 weeks I would ask your dist how much and how soon.. because he will do his best to get them to you on time or will loose the business. Simon "Finn S. Nielsen" <removfinnstadel@tiscali.dk> wrote in message news:43272fa7$0$67259$157c6196@dreader2.cybercity.dk... > Does anyone know what the current delivery situation is for > XC3S1000-5FT256C. > On Xilinx's website they say 3-4 weeks, but from Memec they say more than 8 > weeks. > Does anyone know the truth here.. Austin ? > > FinnArticle: 89395
Dynamically reconfigurable computing. I need to access to the low level config informations in order to have a system that self adapts itself with the environment :) Austin Lesea wrote: > Why? > > What do you hope to accomplish with this knowledge? > > I am curious. > > Austin > > GaLaKtIkUs=99 wrote: > > > When I say a P&R soft I mean replace Xilinx P&R. > > For doing this I need to undestand what is contained in the binary > > files produced by Xilinx P&R ;) > > This job is really impossible ? > > If very difficult ... any start points ? > >Article: 89396
You are not completely new to FPGA, that was yesterday when you came
with the same question, ...
A good starting point is google.com, my advice is to try something less
complex and after you became familiar with the flow ....
one step at a time.
Aurash
biot wrote:
>Hi members,
> I am a student and completely new to FPGA. I am learning VHDL. My
>objective is to implement FFT in spartan-3 starter kit. I would like to
>know how many months it will take me to fully design it. As a novice i
>would like to know few suggestions and references for my project. I
>need help. I don't know from where to start.
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 89397
Hi,
> I'm working on a small project in which we want basically to filter
> Input data (Input Data Rate = 105Mhz) with a FIR filter (64
> coefficients).
> I've forseen to use the MAC FIR IP provided by Xilinx but there could
> be a problem in the way input data are sampled.
A MAC FIR is not ideally suited to your application, given those parameters.
At a clock rate of (say) 210MHz, you would need 32 parallel MAC units to
keep up with the data input rate. This is virtually a full-parallel FIR
implementation. Of course your achievable clock rate will depend on what
part you are targeting.
You should probably still be able to use the Xilinx core, as it is capable
of using multiple MAC units according to your data rate requirements.
Provided that you configure the core such that it has enough processing
power to keep up, the handshaking on the data input samples will cause you
no problems.
Cheers,
-Ben-
Article: 89398vssumesh wrote: > Hello all, > In my design there is a possibility (its dynamic) that a register > may get connect to inputs of 172 gates. Is this possible on Virtex E or > any other xilinx FPGA. And is it possible in the real silicon i am > asking about industry standards. Or is there any other way i can achive > this. By changing my design etc. > Sumesh V S > This is no problem at all. It might be a little slow. In that case you can duplicate your register to balance the fanout between two stages. Kolja SulimmaArticle: 89399
sudarangareddy@yahoo.com wrote:
> Hi All,
>
>
> i request some of you guys who worked or having knowledge on
> imlementation of ARM core with MBA bus in FPGA.Basically we are
> designing two FPGAs in single card with the functionality given below.
>
> we are are trying to implement ARM926 IP core and USB2.0 IP CORE in one
> of the Virtex4 FPGA. Due some constraints we are planning to implement
> some other IP CORES in an another FPGA with ARM interface to this
> IPCORE via AMBA bus from the 1st FPGA.
> Now the issue is that if there are any signals of AMBA bus which have
> any latency issues if we connect the AMBA bus from one FPGA to Other
> FPGA with some IP core(Like PCI express and ethernet MAC).
>
> please direct us in this issue. Feel free to ask if any other
> informaton is required from my side.
>
> regards,
>
> S.RANGA REDDY
>
Hi there,
In this configuration you may find that you can only
run the AHB in quite low clock frequency. AHB design
require signals to be propagate within 1 cycle.
If you connect the AHB across two FPGAs without breaking
up the signal delay, your AHB propagation path can be
very long
CPU Bus interface <-> FPGA #1 bus matrix <-> pad <->
circuit board delay <-> pad <-> FPGA #2 bus matrix <->
AHB slaves on FPGA #2
If your company has the ARM Amba Development Kit (ADK),
there should be a Synchronous 32-bit AHB-AHB bridge (1:1).
That can be used to break up the delays into multiple paths.
Path 1:CPU Bus interface <-> FPGA #1 bus matrix <-> Ahb2Ahb,
Path 2:Ahb2Ahb <-> pad <-> circuit board delay <-> pad <-> Ahb2Ahb,
Path 3:Ahb2Ahb <-> FPGA #2 bus matrix <-> AHB slaves on FPGA #2
regards,
Joseph
____________________________________________________
Joseph Yiu
ARM Holdings Ltd
110 Fulbourn Road
Cambridge
CB1 9NJ
United Kingdom
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