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That is the problem. It is so simple that there is not a direct answer. So if you do not know, don=B4t tell me that it is a joke. Don=B4t lost your time. I would like to choose a strategy to implement a dynamic partially reconfigurable architecture, but I think that the first thing to decide is, what granularity it should have. I have read many articles about both strategies, but anyone tells a definitive assertion about it. What benefits can I enjoy using fine-grain against coarse-grain and vice-versa?Article: 88876
If you could live with an external PPC, Lattice and Altera have both a FPGA fabric with Serdes on it. Altera: Startix GX Lattice: ORTx2G5 (Ethernet), ORSOx2G5 (SONET) where x stands for 4 or 8 (# of channels) delivering up to 3.7Gbps Serdes channels with excellent Jitter specs One suggestion: get away from the on board processor. It kills your SerDes performance. Luc On Tue, 30 Aug 2005 10:53:21 GMT, "blah" <blah@blah.ca> wrote: >Does anyone know of another FPGA (other than Virtex series from Xilinx) that >has an embedded processor comparable to the PowerPC 405 as well as 3Gbps >Serdes? >Article: 88877
Mike wrote: > I think we can take things one step further. Mini Circuits thoughtfully > provides us with the typical phase noise of their VCO (-86dBc @1kHz offset), > and the VCO gain (1-4MHz/V, which we will take to be 2.5MHz/V). > [snip] > > The point of all this is that your noise is probably not coming from your > crystal reference oscillator. I think it's more likely that it's coming from > your VCO, and (if my assumptions about Kd*R are roughly correct) is > approximately what you'd expect to see. > > -- Mike -- Mike, thank you. I just had one of those "Doh! Why didn't I think of that?" moments. I think you may have solved the mystery. The loop bandwidth is only slightly wider than 1 KHz, so of course there is very little attenuation of VCO noise at that frequency! I've just checked the predicted response of my loop for noise injected by the VCO, using my SCILAB model, and it agrees to within a few dB with the measurements. I'd like it to be closer though .....Article: 88878
Hey Nitin, Search for "Basics FPGA" in this group and you will find people in the past who have asked same question as you. Also look for "FPGA/CPLD trend" in this group to see what the latest is happening in this area. In the end google is always a big help. Ciao and good luckArticle: 88879
Hi, I've been struggeling with a long standing problem driving a 320x240 graphic LCD display. I've been using a LCD module with an Epson SED1335 controller chip. In my application the controller is quite susceptible to noise - it resets for no reason, exibits distortion of the image. Googling has come up with some other people also having similar symptoms with this controller. I have mostly overcome the problem by adding additional filtering to the module - extra caps, ferrite on the cable, but the problem sometimes persists. I've been looking at using a controller-less module and driving it directly from the FPGA I have on the board. The problem is that the Acex 1k30 I have on the board only has about 24k memory bits and the memory buffer for the LCD requires 76k bits (320x240). I've been thinking lately that maybe I can compress the memory buffer, then write it to the FPGA and have the FPGA uncompress the buffer spitting writing the frame out to the LCD. Any ideas on this technique or compression techniques? Regards PierreArticle: 88880
Thank you all for the helpful responses. n article <sh49h1h2vvg1df2jaqn0fgqin66b2par5e@4ax.com>, > The Xilinx lvds differential inputs are actually pretty good > comparators but I doubt you could get a solid 8 bits from them. > Besides, single-slope adc's are tacky. > > I bet you could do a good delta-sigma adc in an fpga, with a few > external parts. > > But the op needs a cheap 8-bit adc and a mux. There's nothing very > complex about multiplexing. Some more info, so you don't think I'm completely crazy :). First, I made a big mistake in my original post and said 2 milliseconds instead of 2 *micro* seconds. My target sample latency is under 2 microseconds. Currently, I am multiplexing all inputs down into a 8-input ADC that feeds a uC. I have a latency of 8 us per sample (microseconds, not ms as I originally said) and samples are obtained round-robin. I want to reduce the latency down to 1 us if possible, and also grab all samples at once. I have trouble finding an 8-input+ ADC, 8-bit resolution+, 1 Msamples/sec that doesn't cost an arm and a leg. A new design I am working on will need an FPGA anyway, so I wanted to suck the ADC+uC functionality into the FPGA (probably Xilinx) if possible. Could a delta-sigma style ADC be able to produce new samples at 1 us (1Msamples/sec) w/8-bit+ resolution? I can live with the multiplexing since I'm having to do that anyway. I am guessing the external circuitry would be a comparator, RC network for filtering the PWM, and maybe a FET/BJT to clear the cap of charge? Thanks again. H.Article: 88881
Hello, It was suggested in a previous posting by Paulo Dutra to use XST as a 3rd party synthesizer in EDK to use the -vlgincdir XST option (http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/989278ca15769ba0/a5cf7b4e820ac198?lnk=st&q=EDK+vlgincdir&rnum=1&hl=en#a5cf7b4e820ac198). In the latest version of EDK 7.1i can we sidestep this work-around and set an option directly in EDK? I have been looking in the EST guide (Embedded System Tools Reference Manual) and the GUI as well, but I haven't found any pointers. Thanks, NNArticle: 88882
Hello John, > The Xilinx lvds differential inputs are actually pretty good > comparators but I doubt you could get a solid 8 bits from them. > Besides, single-slope adc's are tacky. I have done a lot of tacky tricks in electronics. Other things they said in design reviews were "weird, gross, unorthodox, yech, ...". Somehow that always happens when cost rules. I am not sure what these diff inputs would do on slow transitions. If they'd let off a wee oscillation-like burst every time the FCC might not be so enthused about that. > I bet you could do a good delta-sigma adc in an fpga, with a few > external parts. Or just use a really cheap audio converter, maybe the kind that is in the $4.99 sound cards. Heck, you even get more bits, like buy eight and get another eight for free. > But the op needs a cheap 8-bit adc and a mux. There's nothing very > complex about multiplexing. Thanks to the CD4051 it would boil down to about two cents per channel. Just my two cents :-) Do you know what happened to the HC4051? They became expensive and non-stock in a lot of places. Did they fall from grace? Regards, Joerg http://www.analogconsultants.comArticle: 88883
Hello Care to give us a first name? > Some more info, so you don't think I'm completely crazy :). We would never think that way of anyone. Well, most of us wouldn't. > First, I made a big mistake in my original post and said 2 milliseconds > instead of 2 *micro* seconds. My target sample latency is under 2 > microseconds. Oops, three orders of magnitude. That calls for a "real" ADC. I am not sure whether it would make sense to do that within an FPGA but John would be the expert on that, not me. Just keep in mind that your FPGA size and thus cost might grow beyond of what a simple ADC would have cost and you can't really mux with them. > Currently, I am multiplexing all inputs down into a 8-input ADC that > feeds a uC. I have a latency of 8 us per sample (microseconds, not ms > as I originally said) and samples are obtained round-robin. I want to > reduce the latency down to 1 us if possible, and also grab all samples > at once. Sound like a good concept. I don't think there is a decently price ADC with 24 inputs. > I have trouble finding an 8-input+ ADC, 8-bit resolution+, 1 > Msamples/sec that doesn't cost an arm and a leg. How about TLV1570? 8-channel 10bits for well under $4. ADS7888 is a serial 8-bit one-channel for under a buck. Can't beat that, really. For muxing the CD4051 is a bit hard pressed at 1usec but can possibly be used. Regards, Joerg http://www.analogconsultants.comArticle: 88884
Eric wrote:
> "...Altera continues to sell Excalibur devices, this product family is
> not recommended for new designs. Designs requiring embedded processors
> should consider Altera's Nios® II processor.
>
> Excalibur devices integrate a 200-MHz processor with the APEX™ 20KE
> FPGA architecture, balancing the price, performance, and system
> integration requirements of system-on-a-programmable-chip (SOPC)
> designs."
>
> Not sure if this is just research or product development, but you could
> still get Excalibur devices.
> Eric
>
You can probably still get the Altera EPXA1, EPXA4 or EPXA10 devices, but
they have been mostly eradicated from the Altera web site and they don't
want you to use them as you noted above.
http://www.altera.com/products/devices/arm/arm-index.html
Also, these devices don't include a high speed transceiver as the OP wanted.
Ed
Article: 88885Hi Pierre, Pierre de Vos wrote: > I've been struggeling with a long standing problem driving a 320x240 graphic > LCD display. I've been using a LCD module with an Epson SED1335 controller > chip. In my application the controller is quite susceptible to noise - it > resets for no reason, exibits distortion of the image. Googling has come up > with some other people also having similar symptoms with this controller. > > I have mostly overcome the problem by adding additional filtering to the > module - extra caps, ferrite on the cable, but the problem sometimes > persists. > > I've been looking at using a controller-less module and driving it directly > from the FPGA I have on the board. The problem is that the Acex 1k30 I have > on the board only has about 24k memory bits and the memory buffer for the > LCD requires 76k bits (320x240). Well, or more ... Using temporal dithering you can achieve about 16 gray levels if you want. (more and it starts to flicker). > I've been thinking lately that maybe I can compress the memory buffer, then > write it to the FPGA and have the FPGA uncompress the buffer spitting > writing the frame out to the LCD. > > Any ideas on this technique or compression techniques? What kind of stuff are you displaying ? For example if you have a user interface, maybe you can consider you screen as being a matrix of character to display text with some char being "icon". Imagine dividing 8x8 tiles with 256 possible chars. So the screen is 40x30 tiles = 1200 tiles = ~1.2 kbytes = 9.6 kbits to store what char to display in each tile. Then there is the content of the tiles themselves. With just B/W tiles, each tile takes 8x8 = 64bits, so you need 16kbits for the tiles memory. The total is 25.6 kbits, slightly above what you have but you can imagine only allowing to use 128 different tiles ... If you have real _images_ to display then you need some image compression, that's quite harder and there is no guarantee that the image you'll need to store will be compressible into what space you have. SylvainArticle: 88886
On 2005-08-30, Hw <localhost@com.com> wrote:
>
> I have trouble finding an 8-input+ ADC, 8-bit resolution+, 1
> Msamples/sec that doesn't cost an arm and a leg.
>
> A new design I am working on will need an FPGA anyway, so I wanted to
> suck the ADC+uC functionality into the FPGA (probably Xilinx) if
> possible.
You will have trouble competing on cost and performance with e.g.,
LTC2236, 10-bit 25 MS/s for $4.67 in singles. All you need to add
is an external 8:1 multiplexer like a MAX4312 ($4.45).
That ADC part has a 6-cycle latency, at 25 MS/s that's only 240 ns.
You could stop it down to 8 MS/s (to lower power dissipation)
and still hit your 1 us latency and throughput goals. Depends
on what clocks you have available.
- Larry
Article: 88887Hi It's possible to implement usb core on xilinx xc95 family devices?Article: 88888
Hi Sylvain, "Sylvain Munaut" <com.246tNt@tnt> wrote in message news:4314d565$0$22061$ba620e4c@news.skynet.be... > Hi Pierre, > > Pierre de Vos wrote: >> I've been struggeling with a long standing problem driving a 320x240 >> graphic >> LCD display. I've been using a LCD module with an Epson SED1335 >> controller >> chip. In my application the controller is quite susceptible to noise - >> it >> resets for no reason, exibits distortion of the image. Googling has come >> up >> with some other people also having similar symptoms with this controller. >> >> I have mostly overcome the problem by adding additional filtering to the >> module - extra caps, ferrite on the cable, but the problem sometimes >> persists. >> >> I've been looking at using a controller-less module and driving it >> directly >> from the FPGA I have on the board. The problem is that the Acex 1k30 I >> have >> on the board only has about 24k memory bits and the memory buffer for the >> LCD requires 76k bits (320x240). > > Well, or more ... > Using temporal dithering you can achieve about 16 gray levels if you > want. (more and it starts to flicker). > > >> I've been thinking lately that maybe I can compress the memory buffer, >> then >> write it to the FPGA and have the FPGA uncompress the buffer spitting >> writing the frame out to the LCD. >> >> Any ideas on this technique or compression techniques? > > What kind of stuff are you displaying ? > > For example if you have a user interface, maybe you can consider you > screen as being a matrix of character to display text with some char > being "icon". > Imagine dividing 8x8 tiles with 256 possible chars. So the screen is > 40x30 tiles = 1200 tiles = ~1.2 kbytes = 9.6 kbits to store what char to > display in each tile. > Then there is the content of the tiles themselves. With just B/W tiles, > each tile takes 8x8 = 64bits, so you need 16kbits for the tiles memory. > The total is 25.6 kbits, slightly above what you have but you can > imagine only allowing to use 128 different tiles ... > > > If you have real _images_ to display then you need some image > compression, that's quite harder and there is no guarantee that the > image you'll need to store will be compressible into what space you have. > > > Sylvain > It's a B/W LCD 1 bit per pixel and basically I display line graphics using an in memory frame buffer and blasting the buffer to the LCD from the CPU. PierreArticle: 88889
Well, Digi-Key has stock of the HC4051 from Texas Instruments, STMicroelectronics, Philips, Fairchild Semiconductor, and Toshiba. So what is the problem? Daniel Lang "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:yO3Re.644$sF6.632@newssvr24.news.prodigy.net... > Hello John, > >> The Xilinx lvds differential inputs are actually pretty good >> comparators but I doubt you could get a solid 8 bits from them. >> Besides, single-slope adc's are tacky. > > I have done a lot of tacky tricks in electronics. Other things they said > in design reviews were "weird, gross, unorthodox, yech, ...". Somehow that > always happens when cost rules. > > I am not sure what these diff inputs would do on slow transitions. If > they'd let off a wee oscillation-like burst every time the FCC might not > be so enthused about that. > >> I bet you could do a good delta-sigma adc in an fpga, with a few >> external parts. > > Or just use a really cheap audio converter, maybe the kind that is in the > $4.99 sound cards. Heck, you even get more bits, like buy eight and get > another eight for free. > >> But the op needs a cheap 8-bit adc and a mux. There's nothing very >> complex about multiplexing. > > Thanks to the CD4051 it would boil down to about two cents per channel. > Just my two cents :-) > > Do you know what happened to the HC4051? They became expensive and > non-stock in a lot of places. Did they fall from grace? > > Regards, Joerg > > http://www.analogconsultants.comArticle: 88890
Hi folks, I'm new to the Quartus software. Can someone tell me how to implement a PLL in the schematic entry mode using a Cyclone FPGA? I just want to get started with them, but don't see any "lpm" functions or such to put one in the schematic. ThanksArticle: 88891
Luc wrote: > If you could live with an external PPC, Lattice and Altera have both a > FPGA fabric with Serdes on it. > Altera: Startix GX > Lattice: ORTx2G5 (Ethernet), ORSOx2G5 (SONET) where x stands for 4 or > 8 (# of channels) delivering up to 3.7Gbps Serdes channels with > excellent Jitter specs > > One suggestion: get away from the on board processor. It kills your > SerDes performance. > > Luc > By "on board processor" I'm assuming that you mean in-FPGA processor. I'm not sure where you got the impression that the PowerPC in the Virtex family effects the operation of the SerDes/MGTs, but this is not accurate. We have many customers that use both in their system with no issues and we have multiple application notes showing designs using both PowerPC and MGTs. I personally have done a lot of analysis of Virtex-II Pro MGT operation here at Xilinx and have never seen a higher bit error due to the PowerPC being active. The PowerPC uses the same transistor design rules as the rest of the FPGA fabric and therefor has no process impact on the MGT performance either. EdArticle: 88892
If id just look harder! Found it. thanks anywayArticle: 88893
i tried jp2. it doesnt connect at all. more hints welcome! # ./jp2 xpc3 9999 Connected to parallel port at 378 Dropping root privileges. JTAG ID = f77db57b Stall 8051 RETRY RETRY RETRY RETRY JTAG ID = f77db57b RETRY JTAG ID = f77db57b RETRY JTAG ID = f77db57b RETRY JTAG ID = f77db57bArticle: 88894
Hi Paul, I ran this past one of the development kit people. He can't definitively answer your questions without seeing your design, but his best guesses at what might be going on are below. If you send your design to me I'll get him to take a look at it, and hopefully he could get you a more definitive answer. Q - How do you decide by how much to phase shift the clock? A - At 100Mhz no phase shift is needed on the clock. I can't think of any reason why a phase shift would be needed at 80 MHz either, and we did run some initial designs on this board at 80 MHz with no phase shift on the clock, and they worked. I suspect this phase shift is covering a problem with how the project is set up. (Also refer to the answer to question 2 -- perhaps that is related) Q - It appears that my data is inverted, does anyone know if the ADC's on this board are active high or active low? A - Two things to check 1) Where is the signal that you are feeding into the ADC's coming from? If looped back on the board like in the reference designs make sure the DAC's are pinned out correctly. The Data sheet on the DAC is confusing in that they pin the chip out to be Bit 1 - 14 which is how they are denoted in the schematic but in reality bit 1 is data 13 MSB and bit 14 is data 0 LSB. There is a note describing this on page 24 of the board data sheet. 2) The second thing to check is how you are interpreting your data. The ADC is set to output the data in 2's complement so make sure you are evaluating it as such. Regards, Vaughn Altera [v b e t z (at) altera.com] "Paul Solomon" <psolomon@tpg.com.au> wrote in message news:430d5265@dnews.tpgi.com.au... > Hello, > > I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I > have been having a bit of trouble getting the ADC to work correctly and I > was wondering is there was anyone therer that had experience with this > board. > > I am able to get it to work when the clk is set to 100MHZ, but is I use a > PLL to run the clk at say 80MHz then the data that I read from the ADC > (also clocked at 80MHz from the same PLL output) is not clean. i.e. it is > similar to the signal I would expect however it has spikes in it > everywhere. I assume this is a clock skew issue or something like that. I > have found that if I use a seperate PLL output to drive the ADC clk then I > apply a 180 degree phase shift to that output then my data looks clean. > > So the questions I have are: > > 1) It would appear that you need to apply a phase shift on the adc clock > output to account for clock skew (or for some other reason). How do you > decide by how much to phase shift the clock? I chose 180 degrees at random > and it seems to work, however I am concerned that this was not a very > academic approach and I could be near a threshold of working / not > working. > > 2) It appears that my data is inverted, does anyone know if the ADC's on > this board are active high or active low? I had assumed active high as > there is no _n suffix next to the pin name, but my data does appear to be > upside down. > > Regards > > Paul Solomon > > >Article: 88895
I emailed Junaid the answer to this a while back, but should have posted to the group in case others hit this. Better late than never ... Quartus 5.0 writes out blif files where unused LUT inputs are connected to gnd. Some tools (e.g. Vpack below) do not like this, since they don't know what gnd is. To get rid of the gnd LUT inputs, read the blif file into sis and write it back out. Now each LUT will be of minimal size (i.e. if only two inputs were used and two were grounded, sis will write out a 2-input LUT only). For more info on writing blif files out of Quartus 5.0, see the QUIP 5.0 documents at https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp The blif writer is documented in the documents/quartus_synthesis_interface.pdf file. Regards, Vaughn Altera [v b e t z (at) altera.com] junaid wrote: > Dear Sir, > > Thanks a lot. I followed the information given by you and converted > verilog to blif file. But while I am converting the same to the net > file one error is coming. > Allow Unrelated Blocks to be Clustered: Yes > Connection Driven Clustering: No > Timing Driven Clustering On > Timing Analysis Done Every 32000 blocks > Allow Early Exit: No > Tradeoff Parameter Alpha: 0.75 > Delay Through Blocks: 0.10 > Intra Cluster Net Delay: 0.10 > Inter Cluster Net Delay: 1.00 > > > Error: Net #35 (null) has no driver and will cause > memory corruption. > I have sent one mail in your mail address <vaughn@eecg.utoronto.ca> > kindly see the mail and help me to solve the problemArticle: 88896
Version 5.0 of QUIP is now on the web. If you're researching FPGA CAD, architecture or applications, or you're teaching a graduate-level CAD course, the hooks into the Quartus CAD system described here are likely of interest. See https://www.altera.com/support/software/download/altera_design/quip/quip-download.jsp to download. Major new features in this release are: - Detailed device documentation for the Stratix II and Cyclone II architectures, enabling researchers to write CAD tools targeting these architectures - Ability to write blif files out of Quartus, enabling the use of Quartus as an RTL front-end to get HDL benchmarks to academic synthesis tools (see documents/quip_synthesis_interface.pdf) - A set of benchmark circuits, including several containing over 30,000 LEs, some with DSP blocks, and many with memory (see documents/quip_benchmarks.pdf) - A description of how to set the Quartus optimization goals and measure the relevant parameters so that you can fairly and accurately compare an academic CAD tool to Quartus (see documents/quip_benchmarking.pdf). Feel free to contact me if you have any questions or suggestions, or if you have benchmark circuits to contribute to the FPGA research community. Regards, Vaughn Betz Altera [v b e t z (at) altera.com]Article: 88897
I created microblaze design using bases system builder for virtex 4 lx25 lc board using Xilinx EDK 7.1i sp2. After downloading, when using xmd to connect, the following error happens.. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0167c093 10 XC4VLX25 Assuming, Device No: 1 contains the MicroBlaze system WARNING:EDK - MDM Peripheral Not Detected on Hardware WARNING:EDK - Assuming opb_jtag_uart peripheral Connected to the JTAG MicroProcessor Debug Module (MDM) No of processors = 1 UNKNOWN Processor Version (0) Verify if FPGA Bitstream was downloaded and DONE pin went High FPGA bitstream was properly built and downloaded to the system. likely possible causes : 1. JTAG cable 2. EDK downloading issue like the ise 7.1i doent program single virtex4 devices after sp3 Any advice. Thanks Best Regards ShakithArticle: 88898
On 2005-08-30 11:18:29 -0700, Mike Treseler <mike_treseler@comcast.net> said: > Brian C. Van Essen wrote: >> I am attempting to simulate a very basic system built with Xilinx EDK >> ModelSim> vsim system_conf system >> > ** Fatal: INTERNAL ERROR in reset_trigger_process(). >> # Time: 0 ns Iteration: 0 Process: >> /system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process >> File: >> C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd >> # >> FATAL ERROR while loading design >> # Error loading design >> > Bring up park_lock_logic.vhd > and find reset_trigger_process > Check the declarations of all > array indexes used there. > > I fixed a similar problem by changing > an array index type from integer to natural. > > > -- Mike Treseler > Well, I have tried to find the reset_trigger_process in all of the libraries vhdl files, but was unable to. I am guessing that it is part of a library like unisim (which is commented to be a Xilinx library). If that is the case, then I am not sure how to correct it if the library is already compiled. Does anyone else have a working environment with these settings. It is important to note that this error does not appear when using a system that only has a PowerPC. Thus, it seems isolated to a component required by the Microblaze. Again, any more feedback would be wonderful. -- Brian Van EssenArticle: 88899
hi For vitex4 devices you are required to use the latest cvs version of mdm (2.01.a). The file can be download from xilinx's answer database (link below), it also tells you how to solve this problem. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20060 cheers, Jason
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