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Frank wrote: > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope). What > might > be the cause? Analog offset and gain difference is most likely. Nonlinearity is possible. Could a hold capacitor be defective? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92376
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). When I connect I channel from DAC to I & Q channel of ADC, I am seeing vastly different digital outputs on ADC (sampling three pins on oscilloscope). What might be the cause?Article: 92377
"Jerry Avins" <jya@ieee.org> wrote in message news:zJudne6ssMf6SxbeRVn-vg@rcn.net... > Frank wrote: > > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > > vastly > > different digital outputs on ADC (sampling three pins on oscilloscope). What > > might > > be the cause? > > Analog offset and gain difference is most likely. Nonlinearity is > possible. Could a hold capacitor be defective? > > Jerry > -- > Engineering is the art of making what you want from things you can get. > ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ OMG! There are 3 ADC boards in my lab, all of them had been badly tampered and the one I am using is the least tampered piece. Maybe I am really doomed. :-(Article: 92378
I have a design that synthesizes to run at a little over 200 MHz. I want to make the design run at 200 MHz on the Spartan 3 board too. I generated the .xaw file by using the Frequency Synthesizer in the DCM Wizard. What I am actually trying to do is.....program the board, but I dont know where to use the .xaw file while programming. Could any of you please let me know how to include the .xaw file while (i) programming the FPGA with the download cable or (ii) programming the PROM by download cable, and then have the PROM program the FPGA. --rsriraghArticle: 92379
"Hal Murray" <hmurray@suespammers.org> wrote in message news:k5udnR_VhaxAUxbenZ2dnUVZ_t2dnZ2d@megapath.net... > >>There can be a problem, when DONE is released by the FPGA, if its risetime >>is too slow. From what I understand, this is only a problem if there are >>more than one FPGA's DONE pins tied together. > > Who/what gets confused if DONE rises slowly? Slow relative to what? > > -- Hal, DONE, after it's been released, becomes an input. An option in the bitstream (via bitgen) can be setup so it looks to see if DONE's being held low, after configuration, and if so, holds off the activation of its guts. I believe that the reason for this is if there are other devices that are being configured, and their DONE pins are tied together, that activation waits until the last device has been configured before they start running. The slowness of the risetime somehow affects a device's ability to sense the release of DONE. This is what I was told. The effect is (at least what we saw when we experienced this problem) that the device never starts up. Both solutions worked, for us -- the stronger pullup worked and and the push/pull option worked. We use the push/pull option, now, since we never tie DONE pins together. I'm not a Xilinx employee, and I don't play one on tv, so if you're really interested I'm sure that there is some documentation on their website. Where are Peter/Austin when you need them? They've probably made so much damn money that they only, now, answer the easy questions. Ingrates! BobArticle: 92380
I have a design that synthesizes to run at a little over 200 MHz. I want to make the design run at 200 MHz on the Spartan 3 board too. I generated the .xaw file by using the Frequency Synthesizer in the DCM Wizard. What I am actually trying to do is.....program the board, but I dont know where to use the .xaw file while programming. Could any of you please let me know how to include the .xaw file while (i) programming the FPGA with the download cable or (ii) programming the PROM by download cable, and then have the PROM program the FPGA. --rsriraghArticle: 92381
Another post by Antti with no knowledge of what the truth is. It's common though, you don't know squat buddy. You get on here and run your mouth as if you know something. Buddy, it's not a matter of pushing anyone. You have no concept of what the truth is in FPGAs. Here is the truth. Here is a link to see where the missing FX parts are. Wake up! http://www.ov-10bronco.net/users/merlin/Flight/kaboom.htm Antti Lukats wrote: > "MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag > news:3upganF12m2i7U1@individual.net... > > Hi folks, > > > > We have laid out a board for XC4VFX20-10FF672, but can't get a single > > sample. The local distributors have been promising us parts for ages, but > > now are saying that they can't get any... The design uses MGTs, but at > this > > point we will accept samples even with the non-functioning MGTs as soon as > > everything else is working... Can anyone help please? It is a very > important > > project for us. > > Thanks, > > Mikhail Matusov > > Hardware Design Engineer > > Square Peg Communications > > Tel.: +1 (613) 271-0044 ext.231 > > Fax: +1 (613) 271-3007 > > http://www.squarepeg.ca > > > > we did receive FX20- FF672 CES1 in May or June, the package has an label > 'sealed on 28 march 2005' - so if your disti has not been able to get you > the very same part by today then they are doing a very bad job. CES1 and > also CES2 have been available for a while, just make more push on the > distributor ! > > AnttiArticle: 92382
Frank schrieb: > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope). What > might > be the cause? You will never, ever, get a noiseless analog signal. Do you know how signed binary numbers work? Are you aware, that there are pairs of numbers that are very close together, but have all or many different bits? In your case noise of less than 1mV can change the ADC value from -1 to 0. This will flip all bits. Therefore you probably have no problem at all. But you will need to look at all bits, not just 4. But you could start with looking at the 4 higher bits, this will give you results acurate to 1/16 of a Volt. Please note that asking essentially the same question three times is considered inpolite in usenet. Like shouting around in class. Also, most of the newsgroups you posted to are completely unrelated to your problem. You did not even mention FPGAs yet. Kolja SulimmaArticle: 92383
The machine is 16702B Logic analyzer, but the module inside is 16750A 400MHz State 2GHz Timing zoom 4MSa Analyzer. I am pretty new to this machine, where can I download the operating manuals?Article: 92384
"Kolja Sulimma" <news@sulimma.de> wrote in message news:438c0e6e$0$27886$9b4e6d93@newsread4.arcor-online.net... > Frank schrieb: > > I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > > vastly > > different digital outputs on ADC (sampling three pins on oscilloscope). What > > might > > be the cause? > > You will never, ever, get a noiseless analog signal. > Do you know how signed binary numbers work? > Are you aware, that there are pairs of numbers that are very close > together, but have all or many different bits? > In your case noise of less than 1mV can change the ADC value from -1 to > 0. This will flip all bits. > > Therefore you probably have no problem at all. But you will need to look > at all bits, not just 4. But you could start with looking at the 4 > higher bits, this will give you results acurate to 1/16 of a Volt. > > Please note that asking essentially the same question three times is > considered inpolite in usenet. Like shouting around in class. Also, > most of the newsgroups you posted to are completely unrelated to your > problem. You did not even mention FPGAs yet. > > Kolja Sulimma Yeah you are right. I have a Virtex 2 FPGA, and I am doing some signal processing with it. Now I am borrowing a logic analyzer and hope that will help me do the measurement better. Thank you for the noise and here is another question: Now I set NFS/GAIN = 0 on datasheet it says "offset binary output available, 1 V p-p supported;". and ADC input is -20mV ~ 0.8V, what range of digital values do I get after ADC? What does that offset mean here? Is this interpretation correct? 0 for -20mV, 0xCCC for 0.8V?Article: 92385
Frank schreef: > The machine is 16702B Logic analyzer, but the module inside > is 16750A 400MHz State 2GHz Timing zoom 4MSa Analyzer. > I am pretty new to this machine, where can I download the > operating manuals? Seach the agilent website: http://www.agilent.com/ Beste Regards, RoelArticle: 92386
Frank schrieb: > Yeah you are right. I have a Virtex 2 FPGA, and I am doing some signal > processing > with it. Now I am borrowing a logic analyzer and hope that will help me do > the measurement better. Use Chipscope ILA. Your university has a site license or at least can get one for free from XUP. > Now I set NFS/GAIN = 0 on datasheet it says "offset binary output available, > 1 V p-p supported;". > and ADC input is -20mV ~ 0.8V, what range of digital values do I get after > ADC? What does that > offset mean here? > > Is this interpretation correct? > 0 for -20mV, > 0xCCC for 0.8V? Offset binary output means that a fixed value is added to the output to avoid negative numbers for negative input voltages (Whatever negative means for you ADC). The analog 0 voltage and the digital offset added to the measurement should be presented in the datasheet. Kolja SulimmaArticle: 92387
Hello, As I would like the Ethernet performance from the GSRD design in the ML403 reference design, I would like to merge them into a single system. I tried to use the DCR2OPB to connect the OPB bus with all the slave's, but that will take me some more time to change all lot of address ranges. Therefore I just took a PLB2OPB bridge and attached it to the DPLB bus of the processor, but that gave an error in EDK "more than 1 slave connected to PLB bus .. ". Does someone know what's wrong? Does someone maybe have a merged version for me ? Best Regards, RoelArticle: 92388
I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external single-port SRAM connected to the FPGA (Spartan II/III). Does anyone have similar FIFO controller (sync/async) implemented using VHDL? Thanks, DamirArticle: 92389
The Virtex 4 "RAMB16" component lets you set the aspect ratio with generics/attributes. But it still only generates a single BlockRAM. If you want a RAM which is larger than 18kbits, then you need to instantiate the RAMB16 component multiple times. -- Fergus J. Henderson "I have always known that the pursuit Galois Connections, Inc. of excellence is a lethal habit" Phone: +1 503 626 6616 -- the last words of T. S. Garp.Article: 92390
We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal FIFO stalls and missing data on the receiving side. Small FIFO implemented inside FPGA does not help to resolve the problem. On the PC, data acquisition is implemented using CyAPI & CyUSB. USB bulk mode is used for transfer. As mentioned data rate is only a fraction of USB 2.0 bandwidth, I don't know if the mentioned problem is related to the implementation of the receiver side (CyAPI) or lacking capability to sustain such bandwidth within Cypress FX2. Did anyone have similar problems using FX2 and how you manage to solve it? I will appreciate any help to resolve this problem, if possible in software - hardware solution will require redesign of the PCB and implementation/addition of large size FIFO to buffer FX2 stalls (which may, according to our experience, extend up to 50 ms). Thanks, DamirArticle: 92391
Bob Perlman wrote: >Fergus Henderson wrote: >>Mike Treseler writes: >>> Problem 1. >>> There are ten times as many software designers >>> as digital hardware designers. >>Solution 1: >>Develop high-level languages for hardware design. Make these similar >>enough to existing software development practices that developers only >>need a general understanding of hardware optimization techniques (e.g. >>pipelining, resource sharing, etc.), available hardware resources (e.g. >>LUTs >>and BlockRAMs), and how high-level language constructs map onto those >>hardware resources. Then one hardware engineer can easily train up 10 >>software engineers to the level of hardware knowledge that they need in >>order >>to be able to productively develop efficient hardware using a >>high-level language. > >Would it be possible to do just the opposite, and create a high-level >language that lets a digital designer write efficient, >high-performance software the same way he'd design hardware? Because >I'd like to become an expert programmer without expending much effort. I'm not suggesting that becoming an expert hardware designer isn't going to take effort. But currently popular hardware design tools are in the stone age in comparison to software design tools. The amount of effort required to implement even very simple functionality in synthesizable VHDL/Verilog is huge -- much higher than the effort required to implement the same functionality in software. Becoming an expert warrior certainly takes effort, regardless of whether your weapon of choice is a sharpened stone axe or an AK47. But that's not a good reason to stick with stone axes. -- Fergus J. Henderson "I have always known that the pursuit Galois Connections, Inc. of excellence is a lethal habit" Phone: +1 503 626 6616 -- the last words of T. S. Garp.Article: 92392
hi I have studied some papers of implementation of morphological operator in FPGA and ASIC. I want to know the reason of implementation of morphological operator in FPGA. Does FPGA implementation use only in test of our design? and what is the meaning of realtime processing? (the required speed of chip) can anyone help me? thank best regardArticle: 92393
Just to add small clarification - What happens is that output FIFO on FX2 is not emptied on time by PC host (using USB BULK IN transfers) - this results that internal FX2 FIFO gets full for significant amount of time and we are currently not able to compensate this using small FIFO implemented in FPGA. As the bandwidth we are using is only a fraction of bandwidth provided by USB 2.0, I'm suspicious about driver performance. Damir "damir" <damir.makni@srce.hr> wrote in message news:dmhhe6$ej8$1@bagan.srce.hr... > We have developed data acquisition system which uses Cypress FX2 as the > USB 2.0 interface. State machine for control and conversion of data > between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. > The problem is that with higher data rates (up to 25 Mbit/s) we experience > FX2 internal FIFO stalls and missing data on the receiving side. Small > FIFO implemented inside FPGA does not help to resolve the problem. On the > PC, data acquisition is implemented using CyAPI & CyUSB. USB bulk mode is > used for transfer. > > As mentioned data rate is only a fraction of USB 2.0 bandwidth, I don't > know if the mentioned problem is related to the implementation of the > receiver side (CyAPI) or lacking capability to sustain such bandwidth > within Cypress FX2. > > Did anyone have similar problems using FX2 and how you manage to solve it? > > I will appreciate any help to resolve this problem, if possible in > software - hardware solution will require redesign of the PCB and > implementation/addition of large size FIFO to buffer FX2 stalls (which > may, according to our experience, extend up to 50 ms). > > Thanks, > > Damir > > >Article: 92394
On 2005-11-29, damir <damir.makni@srce.hr> wrote:
> We have developed data acquisition system which uses Cypress FX2 as the USB
> 2.0 interface. State machine for control and conversion of data between AD
> converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem
> is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal
> FIFO stalls and missing data on the receiving side. Small FIFO implemented
> inside FPGA does not help to resolve the problem. On the PC, data
> acquisition is implemented using CyAPI & CyUSB. USB bulk mode is used for
> transfer.
The USRP/GnuRadio people have equivalent hardware running
reliably at 33 Mbyte/second, at least for most modern motherboards.
Not sure about the Windows part, though, and certainly not with
CyAPI & CyUSB. Check it out -- there is some trickery involved
on all three fronts: FPGA programming, FX2 programming, and host
programming.
- Larry
Article: 92395Damir, I'm more of a hardware type than software, but I believe you're looking at system issues that won't be resolved with bulk mode transfer. If you need a guaranteed minimum data rate over any period of time and can't switch to a real-time OS on your PC, you have to use isochronous transfers. Bulk mode is usually used for non-time-critical data. Even if your data doesn't need true isochronous delivery, you can't use bulk mode if you cannot tolerate gaps in the transfer process for times on the order of many milliseconds. Bulk transfer is for really slow peripherals or those that usually tolerate up to seconds of link downtime without data loss. damir wrote: > Just to add small clarification - > > What happens is that output FIFO on FX2 is not emptied on time by PC host > (using USB BULK IN transfers) - this results that internal FX2 FIFO gets > full for significant amount of time and we are currently not able to > compensate this using small FIFO implemented in FPGA. > > As the bandwidth we are using is only a fraction of bandwidth provided by > USB 2.0, I'm suspicious about driver performance. > > Damir > > "damir" <damir.makni@srce.hr> wrote in message > news:dmhhe6$ej8$1@bagan.srce.hr... > > We have developed data acquisition system which uses Cypress FX2 as the > > USB 2.0 interface. State machine for control and conversion of data > > between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. > > The problem is that with higher data rates (up to 25 Mbit/s) we experience > > FX2 internal FIFO stalls and missing data on the receiving side. Small > > FIFO implemented inside FPGA does not help to resolve the problem. On the > > PC, data acquisition is implemented using CyAPI & CyUSB. USB bulk mode is > > used for transfer. > > > > As mentioned data rate is only a fraction of USB 2.0 bandwidth, I don't > > know if the mentioned problem is related to the implementation of the > > receiver side (CyAPI) or lacking capability to sustain such bandwidth > > within Cypress FX2. > > > > Did anyone have similar problems using FX2 and how you manage to solve it? > > > > I will appreciate any help to resolve this problem, if possible in > > software - hardware solution will require redesign of the PCB and > > implementation/addition of large size FIFO to buffer FX2 stalls (which > > may, according to our experience, extend up to 50 ms). > > > > Thanks, > > > > Damir > > > > > >Article: 92396
In the Xilinx timing reports, paths that have exceptions to the period constraint show up as unconstrained. If you have the patience to follow through the chain of net names you may find that this path has either been assigned "TIG" (timing ignore) via some group, or that it doesn't meet the normal definition of a path from clocked flip-flop output to data input, such as a gated clock or reset signal. In your case the path does look like the timing constraint would apply unless there is a TIG or multipath exception for the signal or module. johnp wrote: > I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm > seeing the > following unconstrained path in the timing report: > > ================================================================================ > Timing constraint: Unconstrained period analysis for net "clk_conv" > > Delay: 3.073ns (data path - clock path skew + > uncertainty) > Source: u0clk_trig_if/trig_conv0 (FF) > Destination: u0clk_trig_if/trig_conv1 (FF) > Data Path Delay: 3.073ns (Levels of Logic = 0) > Clock Path Skew: 0.000ns > Source Clock: clk_conv rising at 0.000ns > Destination Clock: clk_conv rising at 2.450ns > Clock Uncertainty: 0.000ns > > Data Path: u0clk_trig_if/trig_conv0 to u0clk_trig_if/trig_conv1 > Location Delay type Delay(ns) Physical > Resource > Logical > Resource(s) > ------------------------------------------------- > ------------------- > SLICE_X32Y0.YQ Tcko 0.419 > u0clk_trig_if/trig_conv0 > > u0clk_trig_if/trig_conv0 > SLICE_X25Y9.BY net (fanout=2) 2.428 > u0clk_trig_if/trig_conv0 > SLICE_X25Y9.CLK Tdick 0.226 > u0clk_trig_if/trig_conv1 > > u0clk_trig_if/trig_conv1 > ------------------------------------------------- > --------------------------- > Total 3.073ns (0.645ns logic, > 2.428ns route) > (21.0% logic, > 79.0% route) > > > > In my .ucf file, I have set the period on clk_conv, so I don't see why > I'm getting this unconstrained path. In fact, in another section of the > timing > report, I see: > > ================================================================================ > Timing constraint: TS_clk_conv = PERIOD TIMEGRP "clk_conv" 2.450 nS > HIGH 50.000000 % ; > > 4 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold > errors) > > > Thus, I believe the constraint on clk_conv is entered correctly, but > for some reason > the tools appear to ignore the constraint on some of the registers > driven by the > clock. > > My Verilog code has the registers trig_conv1 and trig_conv0 in the same > always > block with the proper clock edge. The code seems straight forward, so > I don't > see how the coding style could cause this. > > > > Any ideas? > > Thanks > > John ProvidenzaArticle: 92397
Martin Schoeberl schrieb: >>HI group, >> >>I am searching for some technique which can give me instruction count >>and cache hits/misses for a configuration created using Xilinx FPGA. >>I have bitstream corresponding to that configuration. >>My objective is to get the following statistics such as instruction >>count and cache hits/misses for any application executing on the system >>configuration downloaded on FPGA. >> > > That's a very strange question. Instruction count and cache > misses are related to processors and do not apply to FPGAs > per se. Well, André DeHon would say that you usually have one instruction and no cache misses if you do not use dynamic reconfiguration. Kolja SulimmaArticle: 92398
Setting these attributes: attribute equivalent_register_removal: string; attribute equivalent_register_removal of busA,busB: signal is "no"; where the buses are 96bit causes a couple of minutes of warning flood for every permutation for bit m,n.. Is there a way to supress these warnings? I dont want these merged for timing reasons.Article: 92399
Have a problem so tracing signals. What's a X_LUT3? A standard LUT3 only
has an INIT value of 0 to 7. This is the "...translate.vhd" file which has
this primitive and an INIT value of x"EB".
Q_n0024_0_1 : X_LUT3
generic map(
INIT => X"EB"
)
port map (
ADR0 => cycle(2),
ADR1 => cycle(0),
ADR2 => cycle(1),
O => Q_n0024(0)
);
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