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Anyone here using a Virtex in a flip-chip package? If so, what precautions do you take during pcb processing to make sure it doesn't water in the vents? Is everyone using a no-clean process? Just looking for some info, Amy ASorensen@gmail.comArticle: 91826
Amy, http://www.xilinx.com/bvdocs/appnotes/xapp426.pdf See page 4, pre-baking. Austin AmyS wrote: > Anyone here using a Virtex in a flip-chip package? If so, what > precautions do you take during pcb processing to make sure it doesn't > water in the vents? Is everyone using a no-clean process? > > Just looking for some info, > > Amy > ASorensen@gmail.com >Article: 91827
I am looking for RTL "64/65-octet encapsulation" IP core, compliant with IEEE802.3ah sec. 61.3.3. Does anyone know where can I find it? I already looked in Xilinx and Altera IP cores, but I did not see one. Thanks, Robert.Article: 91828
johannes.vanderhorst writes: > But it can be tricky applying the GPL to an HDL project, because > traditional concepts like source code and binary executables are > transferred to a domain with source, several intermediate netlist > formats, some of which can be regarded as source when you're wide > awake... The GPL defines what source code means: | The source code for a work means the preferred form of the work for | making modifications to it. For an executable work, complete source | code means all the source code for all modules it contains, plus any | associated interface definition files, plus the scripts used to | control compilation and installation of the executable. In general, if a HDL source is automatically compiled to hardware via several intermediate netlist formats, only the original file(s) that a human wrote should be considered the source for the purposes of the GPL, since only those are the "preferred form ... for making modifications to it." If the programmer has been using scripts to tweak the intermediate netlist files, then those scripts are also part of the source. If the programmer has been manually tweaking the intermediate netlist files, then the manually tweaked files must also be considered as part of the source, in addition to the original source files.Article: 91829
> don't use many software packages that elict grudging acceptance, > much less praise, so when I find a good one, I like to spread > the word. I fully understand and no offence take ;) Jussi JumppanenArticle: 91830
Mike Treseler writes: > Problem 1. > > There are ten times as many software designers > as digital hardware designers. Solution 1: Develop high-level languages for hardware design. Make these similar enough to existing software development practices that developers only need a general understanding of hardware optimization techniques (e.g. pipelining, resource sharing, etc.), available hardware resources (e.g. LUTs and BlockRAMs), and how high-level language constructs map onto those hardware resources. Then one hardware engineer can easily train up 10 software engineers to the level of hardware knowledge that they need in order to be able to productively develop efficient hardware using a high-level language. -- Fergus J. Henderson "I have always known that the pursuit Galois Connections, Inc. of excellence is a lethal habit" Phone: +1 503 626 6616 -- the last words of T. S. Garp.Article: 91831
Eli Hughes writes: > I seriously doubt you see anything much bigger that the snippets on Open Cores. A lot of people once seriously doubted that we'd ever have full-featured high-quality open-source compilers (GCC, lcc, etc.), operating systems (Linux, *BSD, etc.), office software (OpenOffice, KOffice, etc.), and so on. Those people were wrong. Open-source efforts like OpenCores, GRLIB/LEON, FpgaC, JHDL, etc. are just the start of a trend that is only going to get stronger as time goes by. -- Fergus J. Henderson "I have always known that the pursuit Galois Connections, Inc. of excellence is a lethal habit" Phone: +1 503 626 6616 -- the last words of T. S. Garp.Article: 91832
Eric Smith writes:
> Problem 3.
>
> The average software designer couldn't describe
> two gates and flip flop in C (or any other programming language), but
> would instead describe something that synthesizes to a large
> collection of gates and flip-flops.
Solution 3:
Several steps are required:
(a) Provide source-level hardware resource profiling, so that
developers using high-level languages for hardware design
can determine how much each part of their source code contributes
to the overall resource costs.
(b) Provide documentation of recommended HLL idioms for generating
efficient hardware.
(c) Ensure that the high-level language used for hardware design has a
way of expressing constructs that will map directly down to the
each of the available hardware resources, such as LUTs and
flip-flops,
so that programmers can if necessary manually transform their
code
to optimize it at a fairly low level without having to switch to
a different
programming language.
(d) Implement compiler optimizations to perform as many as possible of
these transformations automatically, or by means of pragmas or
compilation
options, rather than requiring the programmer to perform the
transformations
manually.
--
Fergus J. Henderson "I have always known that the pursuit
Galois Connections, Inc. of excellence is a lethal habit"
Phone: +1 503 626 6616 -- the last words of T. S. Garp.
Article: 91833
Hello Everyone again,
This topic is troubling me for couple of weeks now. I want to
get over this as quickly as possible. I am trying to transmit data from
the virtex 4 LX fpga board to the PC using ethernet PHY and i am
unable to detect any data on the PC.
I have written a small state machine using vhdl which actually
transmits the ethernet packet( dest MAC, Source MAC, length/type, data,
fcs(Crc)] . I am sure that FCS is correct as i tested my code for
sample ethernet packets and i got it right.
There is a sample bit file given with the evaluation board to me
for testing the ethernet PHY.So when i download this bit file and in
the cmd , when i say ping fpga(mac address) and i start the ethereal
capture. I am able to see the data transfer to and from between fpga
and mac.
But if i dont ping it and just start capturing by clicking the capture,
i am not able to detect anything except the ARP which is data
transferred from PCs ip address to broadcast.
In my project i dont ping in the cmd because i didnt include any ip
address in my vhdl code. So basically i am not able to detect anything
in the ethereal except the ARP which is being transferred from PC to
broadcast. The format of the ethernet frame i am using is
Destination MAC ad, Source MAC, length/type, data, FCS(CRC) and i am
not using any ip address or udp header in my ethernet frame in the vhdl
code.
Probably the data is getting transferred on to the PC, but not able to
capture it since, i am not pinging it. So how do we see what data is
coming out from the PHY.
Please advice ?
Thanks
Ashwin
Article: 91834On 14 Nov 2005 14:49:49 -0800, "fjh-mailbox-38@galois.com" <fjh-mailbox-38@galois.com> wrote: >Mike Treseler writes: > >> Problem 1. >> >> There are ten times as many software designers >> as digital hardware designers. > >Solution 1: > >Develop high-level languages for hardware design. Make these similar >enough to existing software development practices that developers only >need a general understanding of hardware optimization techniques (e.g. >pipelining, resource sharing, etc.), available hardware resources (e.g. >LUTs >and BlockRAMs), and how high-level language constructs map onto those >hardware resources. Then one hardware engineer can easily train up 10 >software engineers to the level of hardware knowledge that they need in >order >to be able to productively develop efficient hardware using a >high-level language. Would it be possible to do just the opposite, and create a high-level language that lets a digital designer write efficient, high-performance software the same way he'd design hardware? Because I'd like to become an expert programmer without expending much effort. Bob Perlman Cambrian Design WorksArticle: 91835
Thanks for the advice Everyone, Have made some progress in that the local Avnet FAE has contacted me as a result of this thred and is setting up a discussion with Xilinx directly so at least I can make my case to the source. Jon, good to hear you actually got some FX20s, gives me heart the FX60s are out there. Alex, I'm one of those CSIRO guys. While we have designed boards for the V4FX we are yet to see a V4 chip arrive apart from the FX12 (which have no rockets) on my dev board I have been using to get the linux PPC control code going on which will eventually go on the FX60 board. For interest here is a photo of the assembled board waiting for the FX60 chip (for 2 months now on the bench) the other gaps are some expensive 2GS/S 10 bit ADCs/DEMUX and memory which I don't want to put on till I've tested the FPGA. http://www.atnf.csiro.au/people/Paul.Roberts/pics.html My collegue who is building the receiver board is in a similar situation with a fully assembled board using the FF1152 package just sitting on the bench awaiting a V4. Enjoy your stopover Antti. Its not often one just stops over in Sydney, its a long way from anywhere. Are you on your way to New Zealand? Regards, Paul "Paul R" <paul_p_roberts@bigpond.com> wrote in message news:eBEdf.16405$Hj2.13728@news-server.bigpond.net.au... > I was wondering what anyone else's experience ahs been with getting hold of > Virtex4 FX 20 and 60 devices (The ones with the up to 10 GBPs MGTs). I have > had 3 of the XC4VFX60-10FF672CES2 (That is engineering sample stepping 2) > devices on order since May this year, originally with a 6 week lead time. I > have had constant series of delays for no clear reasons given by our local > agent (I'm in Australia). Xilinx won't talk directly, everything has to go > through this agent MEMEC, the sole authorized distributer for Xilinx in Oz. > They are either unwilling or don't have the info themselves. I get given > snippets about speed of the MGTs , yield problems, new speed grade > desiginations but no real info. The Xilinx website has nothing but its > totally positive marketing hype. To add insult to injury I was due to get my > chips late October. At this time MEMEC was bought by AVNET, all the puchase > orders with xilinx were reraised under the AVNET banner but they stuffed up > and reraised at the current market leadtime of 16 weeks odd! > > I have a fully designed (12 layer) PCB which is fully populated with a big > blank where the FPGA is to go and its seriously delaying our whole project. > The project also relies on the 10 GBPs serial data rate capability of the V4 > RocketIOs. Do any of you people not so far away from the source as I am know > what the story is with the FX devices? Should I be redesigning my sytem to > use external SERDES and not rely on the V4 FXs coming along. I spoke to one > of the hard to find parts specialists in the US and they said the > engineering sample V4 devices are free in the US. I'm paying $1300 each for > them is this true? > > When I looked at going back one step to the Viretex2 pro X 10 GBPs devices I > find all reference to the -5 10 GBPS devices has totally vanished from the > Xilinx datasheets. What's going on here? > > Paul R > >Article: 91836
hi, thanx for the advice. i 'll try both of these. however in the KODAK spec it mentions its addresss clearly as 1000100. and in the analyzer i see the same being transfered to the device with LSB set to 0 to indicate a Write. all the properties are normal, i.e sda changes only when the scl is low, start bit is correct. just before the ACK clock pulse, the sda goes high and stays there continuously. So i dont see any stop condition in the waveform. i thought this is because slave does not acknowlege the master. CMOSArticle: 91837
Hello, Is it possible to use a JTAG cable connection to transfer data into and out of an FPGA during regular operations? The situation is like this: we have a Xilinx Spartan 3 board that we are programming with a digilent parallel cable. This works fine. We would also like to transfer data into and out of the FPGA, for which we are currently using serial communications (RS232), but the data rate is now becoming a bottleneck. The JTAG cable, connected through the parallel port, should be capable of doing much higher speeds than RS232. It is, however, connected to the JTAG pins of the FPGA. Can this somehow be used to transfer data in and out without redesigning the board in any way? Is there any software that could be a starting point for this? Thanks, Nitin ChandrachoodanArticle: 91838
For my mind I would agree.. I want a editor that edits files.. the more bells and whistles the more there is to break and the slower it runs.. How many people complain about bloatwere from MS? An editor is an editor... I will accept searching but revision control is best done outside... We have HDL designer at work and using VSS it runs like a 2 legged dog... (no offence to animal lovers) but VSS itself checks in and out the same files in a serious fraction of the time. Simon "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:q91gn1h89n6fn6fmtjljbdacdidb4dqkpj@4ax.com... > On 13 Nov 2005 18:30:33 -0800, jussij@zeusedit.com wrote: > > >> At $39.95, it costs the same as Zeus. > > > >Just curious. For the same price, does UltraEdit also come with > >integrate version control, class browsing, intellisensing and > >macro scripting? > > > >The last time I checked, for these extra programming features you > >needed to move up to the UltraEdit Studio which comes in at twice > >the price. > > Plain old UltraEdit has macro scripting. For version control, I use > the Tortoise extension for subversion. As for the other features you > mentioned, I don't know; I don't use them. And I also configure > UltraEdit to run emacs Verilog mode in batch to get quick generation > of port lists, etc. > > >> And when you report a bug, they fix it, quickly. > > > >Zeus is no different in this regard. > > Nor would I suggest otherwise. > > I posted not to disparage anyone else's editor, but to say that > UltraEdit is nothing short of terrific. I don't use many software > packages that elict grudging acceptance, much less praise, so when I > find a good one, I like to spread the word. > > Bob Perlman > Cambrian Design WorksArticle: 91839
I dont think you require anything else. For in circuit debugging.. all you need is.. 1) JTAG cable 2)ChipScope Pro 3)Impact for programming (which comes with ISE only) YOu need to have debuger like 'paradigm' through which you can do the software verification of your IP. ChipScope is good enough to monitor In-FPGA signals but puts a limitation on memory requirement.Article: 91840
Ethereal has no problems showing non-IP packets when it catches them. Are you sending the correct preamble and SFD ? Do you see the link blink on the PC whenever you send something ? Manually copy a static IP packet bit by bit in your VHDL code, and send that as a test packet. Compare your version with the sample bit file by looking at PHY signals with a scope.Article: 91841
CMOS a =E9crit: > however in the KODAK spec it mentions its addresss clearly as > 1000100. and in the analyzer i see the same being transfered to > the device with LSB set to 0 to indicate a Write. all the properties > are normal Hi Your SDA and SCL ports should be bidir (I haven't checked OC's design so I assume they are). Use ChipScope to monitor SDA & SCL *inputs* to the FPGA, not its outputs. This will show you what's going on on the actual bus lines, not what the FPGA drives out. (this is an alternative to the use of an oscilloscope :o) NicolasArticle: 91842
Just one more question. In the FPGA what ressource realizes the physical external memory access ? Is it the JTAG that drives the FPGA IO to creates access cycles ? Is it the the use of the embedded hardware module which drives the EMC peripheral ? Something else ? Thanks. Stéphane. "Newman" <newman5382@yahoo.com> a écrit dans le message de news: 1131979709.484972.194960@f14g2000cwb.googlegroups.com... sjulhes wrote: > Hi, > > I'am wondering about the download capabilities of XMD. > > If an FPGA is configured with impact on the JTAG, then software uses XMD > with the JTAG cable to be downloaded in FPGA. > > If for example my SOC has a PPC, some BRAM, an OPB_EMC peripheral and some > externalSRAM attacheds to it. > > Is XMD able to directely download my .elf into the external SRAM through the > EMC peripheral and launch software from the external SRAM ??? Yes > > This is what I understand of the xilinx's webserver reference design to > work. > I'm not sure of this, I would thing there has to be a bootloader to > interface with XMD that will drive the EMC peripheral ??? > But they don't speak about it... The reset vector is at 0xfffffffc, so there has to be some memory to vector the program off to where the rest of the memory is. If you notice, from XMD, there are commands like mrd and mwr (memory read) and (memory write) that are available via the JTAG emulator through XMD. One could write a tcl program that did a series of writes and reads to load the program into memory. There is a the "dow" command available that takes an elf file and loads sram. Others have written tcl programs to program flash, which needs a series of mwr, mrd commands. - Hope this helps Newman > > Can someone clear this point ? > Thak you. > > Stéphane.Article: 91843
Thank you for the various links and recommendations on this subject. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91844
I've read accounts indicating that RoHS compliance has been known to cause issues in high-speed designs. Being that FPGA's are usually at the core of a lot of these designs, I thought I ask here if anyone has had first-hand experience with these problems. RoHS compliance is great, but not at the expense of reliability or manufacturability. If RoHS compliance isn't desirable due to these or other issues, what approach have you or your company taken? Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91845
Hi, You may also want to look at the GNAT design which was featured in the following Xilinx Xcell Journal. http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm This design uses the JTAG port of the FPGA as a communication channel from a PC to the logic in your design. You can use it as an interface to the PicoBlaze. The GNAT design is available for download for free from here. http://www.s3group.com/system_ic/gnat/ Derek Dhivya wrote: > hi.. > i am tryin to interface the pico blaze from SPRATAN III to a computer > and hvin some trouble..can ny 1 guide me/?? >Article: 91846
Hi, You can use the JTAG port of the FPGA to read back the contents of any BRAM. However you will need to build some custom logic into your design to enable this. Firstly you will need logic to talk to the JTAG port of the FPGA and secondly you will need logic to read the appropriate BRAM and pass the contents to the JTAG port. Furthermore you will need software on your PC to capture the data read back through the JTAG port. The following Xcell article describes the GNAT design which illustrates how you can use the JTAG port of a Xilinx FPGA to communicate with the internals of your design. http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm The GNAT example design is available for download free from http://www.s3group.com/system_ic/gnat/ Derek giohdl@netscape.net wrote: > Hi all. > I'm using a Virtex2 fpga which uses a lot of BRAMs. > The design modifies the content of these BRAMs during elaboration. > Is it possible to dynamically readback the BRAMs contents in a text > file using JTAG? > I've read the Xilinx documentation (impact) but I can't find a simple > and fast solution. > Can anybody help me? > Thanks. >Article: 91847
Well, I dont have any account of FPGA problems, but you have to be ready for trouble when it comes to fabrication, and pcb design. PCB material has to change to meet the new standards (RoHS is not just about lead) New materials = New impedances... High speed designs might depend on certain track impedances, and if you try and port an old design to the new process - they won't match! Then there's the problem of finding _ALL_ components on your design in a RoHS version... and finding RoHS solder, and then putting it all together. A soldered joint that has been made with a RoHS process looks different to a traditional joint... so good joints might be flagged as bad etc etc. Anyways, I don't have FPGA specific comments, but obviously the FPGA is going to be on a PCB with other devices. HTH Ben "Martin" <0_0_0_0_@pacbell.net> wrote in message news:eOief.20170$dO2.7437@newssvr29.news.prodigy.net... > I've read accounts indicating that RoHS compliance has been known to cause > issues in high-speed designs. Being that FPGA's are usually at the core > of a lot of these designs, I thought I ask here if anyone has had > first-hand experience with these problems. > > RoHS compliance is great, but not at the expense of reliability or > manufacturability. If RoHS compliance isn't desirable due to these or > other issues, what approach have you or your company taken? > > Thanks, > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > eCinema Systems, Inc. > > To send private email: > x@y > where > x = "martineu" > y = "pacbell.net" > > >Article: 91848
"Paul R" <paul_p_roberts@bigpond.com> wrote in message news:Fmaef.17770$Hj2.15399@news-server.bigpond.net.au... > For interest here is a photo of the assembled board waiting for the FX60 > chip (for 2 months now > on the bench) the other gaps are some expensive 2GS/S 10 bit ADCs/DEMUX > and > memory which I don't want to put on till I've tested the FPGA. > http://www.atnf.csiro.au/people/Paul.Roberts/pics.html > Hi Paul, I noticed from your photo that you have two 28 pin PLCC packages (U15/16?) in the bottom right of the PCB. Do you find you have problems with getting the right solder paste thickness for these parts given that you have some fine-pitched TTSOPs on the board as well? You might need a stepped solder mask with a BIG step! I try very hard to avoid PLCC packages, I've had too many manufacturing problems with them. Anyway, it's a minor point, just thought I'd mention it! Any chance of a view of the backside to see how you've laid out your bypass caps for the V4? Good luck, Cheers, Syms.Article: 91849
Martin wrote: > I've read accounts indicating that RoHS compliance has been known to cause > issues in high-speed designs. Being that FPGA's are usually at the core of > a lot of these designs, I thought I ask here if anyone has had first-hand > experience with these problems. > > RoHS compliance is great, but not at the expense of reliability or > manufacturability. If RoHS compliance isn't desirable due to these or other > issues, what approach have you or your company taken? There is no way around RoHS compliance, at least over here. There are some exception for certain industries. Unless you belong to them, You just have to make it work. The exception are being constantly reevaluated. So if your competition can make it work without lead, you'll be out soomer or later. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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