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glen herrmannsfeldt wrote:
> Marc Battyani wrote:
>
> (snip)
>
>> In fact I'm not sure that full IEEE floating point accuracy is
>> needed. For
>> sure single precision is not enough but probably double precision is not
>> really needed. The problem is that people who write the algorithms do
>> it in
>> C(++) using double precision floats and they use double precision
>> libraries,
>> etc. So it's not obvious to see what precision is really needed.
>> After all
>> in an FPGA we can use the exact number of bit needed. (In fact it is
>> even
>> possible that a fixed point format could work)
>
>
> If fixed point will do it, even significantly wider than floating
> point, it is likely the best way. Floating point add is a lot more
> expensive than fixed point. The difference is much smaller for
> multiply and divide, not counting any overhead specific to full IEEE
> implementations.
>
> -- glen
>
Glen, for this application, I'd argue that the floating point might be
cheaper if he needs the dynamic range, especially if fixed point pushes
him to wider than 35x35 multipliers. a floating point multiplier has
very little extra compared to fixed point, and you can get away with a
considerably smaller multiply. He may find that he can get away with a
17 bit significand with floating point (in which case a single
multiplier per node in the array is needed), or at worst 4 multipliers
for single precision. On the other hand, if his dynamic range demands
more than 35 bit multiplication if converted to fixed point, then he's
got 9 embedded multipliers per multiply, plus adders to combine the
partials. Generally speaking, using floating point for multiplication
and division is cheaper than using fixed point. The opposite is true of
addition and subtraction. In this case however, his addition has to
essentially be done in fixed point, so he can do the conversion to fixed
using denorms, do the row add and then renormalize the sum. In any
event, I don't see any problems getting this matrix multiply into a
spartan3 as a floating point implementation.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90401I see. But I have two algorithms and I have to estimate the term Area*Time (time of execution). How can I choose the best algorithm ( min Area*Time), if I haven't an unique parameter that rappresents the area? -ClaArticle: 90402
>But I have two algorithms and I have to estimate the term Area*Time >(time of execution). >How can I choose the best algorithm ( min Area*Time), if I haven't an >unique parameter that rappresents the area? Count LUTs and FFs. It doesn't matter how much logic you put into a LUT, it still takes the same amount of area. Maybe count RAM and multipliers too. That's assuming you are trying to compare two implementations in a FPGA. If you are really targeting an ASIC technology, then you need to extract the logic and count the gates. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90403
allanherriman@hotmail.com wrote: ------------- Much thanks to you, Guenter and Allan. I did as you both advised, and GTKwave is now running wonderfully with the iverilog, vvp output as expected. I especially appreciate you both giving me examples to follow. ------------- Again much thanks guys. Cheers GrahameArticle: 90404
Problem solved by using version 6.0 ...Article: 90405
To avoid metastability problems, we use such a median filter. Depending
on the input signal rising time (d could be an input pad), the length
of the filter is sometimes increased to 5 or 7. In theses cases, we use
of a variant of it that we call a recursive median filter in which the
output is changed only if we receive a given number of consecutive
sample w/ the same value. It reduces latency before taking a decision
by 2. It helps if you use handshaking between 2 non-correlated
synchronous clock domains w/ relatively close clock frequencies.
BTW, what a complicated style for a median filter which use 2 more DFFs
than necessary. Why not:
PROCESS(clk_24M)
VARIABLE a : STD_LOGIC := '0';
VARIABLE b : STD_LOGIC := '0';
VARIABLE c : STD_LOGIC := '0';
BEGIN
IF RISING_EDGE(clk_24M) THEN
c := b;
b := a;
a := d;
q <= (a and b) or (a and c) or (b and c);
END IF;
END PROCESS;
We use such
Article: 90406> I've got a spartan-3 starter board and got tired of the 8color output > from the standard vga connector. > So I hooked up som E12 series resistors (570, 1200 and 2200) to get > 9bits and 512 possible colors (not evenly spread, but cool anyway). Hey, I made the same mod to my board. Using 470,1k, and 2k2. I used some of the B1 port pins. Another way to increase the colors output without modifying the board is to use dithering. How is one to learn about alpha blending with only single bit color ?Article: 90407
<nospam.eric@gmail.com> wrote in message
news:1129103466.883591.77880@g47g2000cwa.googlegroups.com...
> To avoid metastability problems, we use such a median filter. Depending
> on the input signal rising time (d could be an input pad), the length
> of the filter is sometimes increased to 5 or 7. In theses cases, we use
> of a variant of it that we call a recursive median filter in which the
> output is changed only if we receive a given number of consecutive
> sample w/ the same value. It reduces latency before taking a decision
> by 2. It helps if you use handshaking between 2 non-correlated
> synchronous clock domains w/ relatively close clock frequencies.
>
> BTW, what a complicated style for a median filter which use 2 more DFFs
> than necessary. Why not:
>
> PROCESS(clk_24M)
> VARIABLE a : STD_LOGIC := '0';
> VARIABLE b : STD_LOGIC := '0';
> VARIABLE c : STD_LOGIC := '0';
> BEGIN
> IF RISING_EDGE(clk_24M) THEN
> c := b;
> b := a;
> a := d;
> q <= (a and b) or (a and c) or (b and c);
> END IF;
> END PROCESS;
>
>
>
> We use such
Eric,
With tongue in cheek! ;-)
What a complicated style for a retimer circuit which uses 1 more DFF and one
more LUT than necessary. Why not:
PROCESS(clk_24M)
BEGIN
IF RISING_EDGE(clk_24M) THEN
a <= d;
q <= a;
END IF;
END PROCESS;
You realise your code only synthesises 3 FFs including 'q'? Input 'd'
connects straight to the FF 'q'. Your longer 'median' circuits are, perhaps,
a useful glitch filter. However, your voting circuit has a negative effect
on metastability performance compared to a straight retiming circuit. The
logic adds extra delay. In my circuit the FF 'a' which initially retimes
'd', (in both circuits this is the critical FF) has more time to recover
from any metastable state than your circuit.
Cheers, Syms.
Article: 90408Also look for the GNAT XCell Article http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm Sylvain Munaut wrote: > Hello, > > > I'm looking for some example on how to use the USER1,2 functions in a > spartan 3 (examples on virtex2/4 or others are welcomed). I know how to > instanciate the component but that's about it. I searched xilinx site > but didn't found any real example ... > > If anyone of you has a simple stuff using that at hand, that would be nice ! > > Regards, > > SylvainArticle: 90409
After some investigation, Xilinx recommended the C_APU_CONTROL = 0b0000_0000_0000_0001 setting and the problem has since gone away on all of our boards. I have not seen any noticeable side effects in software. At least in the short term this seems like a reasonable solution. - ChrisArticle: 90410
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:usjnk19bc90d5elmc6rra6e7169g793mdl@4ax.com... > Sharing this filthy ground or power with your precious > little 3.3V FPGA is asking for trouble. Hi Jonathan, So, thanks for a good post as ever! Just to pedantically whinge on about a pet subject of mine, I would recommend sharing the ground as tightly as you can. Provided you have a good multi-layer board with ground planes, you'll make things much easier than if you have a separate ground. Bits of metal floating around in electrically noisy environments can re-radiate in the most irritating and unpredictable way, acting like antennas. Even very large currents passing through your ground planes don't affect the circuit provided the board supplies are tightly coupled to the ground - in other words use lots of bypass caps. All this assumes you took the other eminently sensible precautions you describe, i.e. I/O protection and power supply filtering. Cheers, Syms. p.s. I learn something from every post. From this one I learnt that the plural of antenna is only antennae when they're on animals! The sad life of the pedant is never simple.Article: 90411
Stephan, Xilinx? If so in your UCF file do this:- NET "enable" TNM_NET = "enable_FFS"; TIMESPEC TS6070 = FROM : enable_FFS TO enable_FFS : 50ns; A discription of this is in the contraints guide in the "TNM_NET" section. HTH, Syms. "Stephan Flock" <sflock@freenet.de> wrote in message news:diglv9$aan$00$1@news.t-online.com... > Let's assume I have a global clock running at 80 MHz and a 2 bit counter > running from this clock, which generates a 20 MHz clock enable signal. > > Now I'm going to put a lot of combinatorial logic between two registers, > which are clocked from the 80 MHz clock and enabled with the 20 MHz CE > signal. > > How can I constrain this design so that it is not being placed and routed > for 80 MHz? > Is there a way to apply any sort of timing constraint to the clock enable > signal / net? > > TIA, > Stephan Flock > >Article: 90412
Hi So what constraints did you use. We are trying to get DDR to work for virtex 4 lx160 Thanks jit <jjohnson@cs.ucf.edu> wrote in message news:1128704552.444478.309370@g43g2000cwa.googlegroups.com... > Thanks Antti, for both replies. We've already got a board built and > half-running with V4LX100-11's (ordered early, paid big bucks, got > engineering samples). > > We had the design running at 360MHz in a V2Pro a few months ago (DCM, > source-synchronous mode, no IDELAY, plus a few LOC constraints), but > I'm still not sure I got the timing constraints right. SynplifyPro > doesn't seem to support hold-time constraints, and Xilinx's UCF syntax > boggles my mind. > > UCF doesn't seem to support multiple constraints on a port (like > Synopsys does with set_input_delay -max|-min -add_delay); UCF appears > to overwrite them. (Last one wins, plus some other priority rules they > have...) > > The 500 MHz was slightly rounded up for clarity in illustration. We > need 360MHz for the current 12-bit A/D converters, and 420/480 if we > move up to 14/16-bit converters. > > We hope to put this in an ASIC someday, at which point I'll need > complete timing constraints; it would be great if everybody supported > the same constraint format (like Synopsys .SDC), or if I could find an > English <-> UCF translator... > > Thanks again, > > mj > >Article: 90413
On Wed, 12 Oct 2005 04:41:33 -0700, "Symon" <symon_brewer@hotmail.com> wrote: > I would recommend sharing the ground as tightly as you can. Sounds good to me, with the proviso... > Provided you have a good multi-layer board with ground planes > The sad life of the pedant is never simple. Please, can someone explain what's sad about it? A pedant is someone who prefers their opinions to be correct. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90414
Jonathan Bromley <jonathan.bromley@doulos.com> writes: > If you're in the automotive world for your 12V, > then it's just as bad. Remember that load dump > effects can cause +/- 60V transients on power > and control wires. Take a look at CANbus transceiver > chips from Philips and others (82C251 rings a bell, > but someone better check - it's been a long time...) > to see how bulletproof it's possible to make 'em. > <ding goes the bell> Indeed so, although that's one of the older ones - TJA1050 is a more current one - apply -27 to 40V to the CAN pins for as long as you like, +-200 V transients as well! There's a great series of scope shots of real automotive transients from things like windscreen wipers in a paper I can't find at the moment - regular 70V spikes every time the intermittent wipers triggered IIRC! I'll try and dig them out... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 90415
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:711qk1trchp4t17islo7n6vfso5ooikh7d@4ax.com... > >> The sad life of the pedant is never simple. > > Please, can someone explain what's sad about it? > A pedant is someone who prefers their opinions to be correct. > Through bitter (and occasionally painful) experience I've discovered that not everybody enjoys having their grammar, punctuation and spolling corrected at every possible opportunity. Especially your nearest and dearest. To paraphrase the (apparently falsely accredited) words of Churchill on the occasion of him being corrected for ending a sentence with a preposition (Good grief, what was he thinking of?), "It is the kind of arrant pedantry up with which they will not put." I refer you to this article:- http://en.wikipedia.org/wiki/Pedant Wikipedia seems to imply that pedantry is a symptom of lack of social interaction, or even "an indication of certain developmental disorders". I fear the author may have confused cause and effect. Cheers, Syms. ;-)Article: 90416
Symon wrote: > I've discovered that > not everybody enjoys having their grammar, punctuation and spolling > corrected at every possible opportunity. You entered that typo on purpose, didn't you? KoljaArticle: 90417
Would I do that? It reminds me of the funniest spelling mistake I ever saw. I received an email which referred to a 'qwarty' keyboard. He'd actually typed qwarty and, no, he didn't have a fancy layout keyboard! Cheers, Syms. "Kolja Sulimma" <news@sulimma.de> wrote in message news:434d2f4c$0$24169$9b4e6d93@newsread4.arcor-online.net... > Symon wrote: >> I've discovered that >> not everybody enjoys having their grammar, punctuation and spolling >> corrected at every possible opportunity. > > You entered that typo on purpose, didn't you? > > Kolja > >Article: 90418
I am currently trying to use the MGT XBERT system with an unsupported
board. I have no problem synthesing the design but when I try to
implement the design I get the two error messages below.
Does anyone have any ideas what the problem could be? I am using only
Xilinx'x own files so there shouldn't be a problem with the code. I
don't really know where to start...
Rosemary
ERROR:NgdBuild:455 - logical net 'N1' has multiple driver(s):
pin G on block XST_GND with type GND,
pin PAD on block
flib/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/N1
with type PAD
ERROR:NgdBuild:924 - input pad net 'N1' is driving non-buffer
primitives:
pin G on block XST_GND with type GND,
pin I0 on block flib/clk_startup_0/clk_startup_0/jtgtdoen1 with
type LUT2,
pin I1 on block flib/clk_startup_0/clk_startup_0/jtgtdoen1 with
type LUT2,
pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_1 with
type FDP,
pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_0 with
type FDP,
pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_2 with
type FDP,
pin PRE on block flib/clk_startup_0/clk_startup_0/por_ff_3 with
type FDP,
pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01111 with type
LUT3,
pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01141 with type
LUT3,
pin I2 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01171 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01451 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01421 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n00991 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01021 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01051 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01081 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01111 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01141 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01171 with type
LUT3,
pin I0 on block flib/plb_mgtbert_0/plb_mgtbert_0/_n01191 with type
LUT2
Article: 90419The popular misconception is that the output of a metastable latch or flip-flop somehow indicates that it is metastable. Not true. The metastable output (usually) has a perfectly valid level, 0 or 1 (and either one is as acceptable as the other, since the decision was obviously ambiguous.) The trouble is that this "proper" output can spontaneously change state at a completely unpredictable, non-deterministic moment. So you can get a state change that occurs at an unpredictable, non-synchronous moment, and that is what defies any attempt at a "solution". We can only say that any such bad transition occuring more than x ns after the last clock edge is very unlikely. And for modern CMOS latches and flip-flops, it will be a million times less likely if we can wait one additional nanosecond, i.e. (x+1) ns. See XAPP094. For practical circuits and frequencies x=3, or make it 4 if you are a pessimist. Peter Alfke, Xilinx ApplicationsArticle: 90420
Hey, I'm building a DDR2 controller and have 3 banks on a virtex 4 so 6 IDELAYCTRL blocks ... so i look in pace to loc them (as this is preferred method) and it seems that it only locks 4/6 IDELAYCTRL blocks on the right place and the other 2 not ... this is in PACE .... When i lock it in floorplanner i get the same issue ... When i look at it (ngd/ncd) in fpga editor they are at the right place???? who should i believe???? the strange this is that this is happening in the middle banks ... so the small banks in the middle of the fpga?? because when i loc those2 IDELAYCTRL on the other (left/right) banks i don't have that problem? is this a bug in the software? Any help is welcome .... thanks in advance, kind regards, TimArticle: 90421
Peter Alfke wrote: > The popular misconception is that the output of a metastable latch or > flip-flop somehow indicates that it is metastable. Not true. Agreed. Logic simulations produce and propogate generic X's, not real circuitry. > The > metastable output (usually) has a perfectly valid level, 0 or 1 (and > either one is as acceptable as the other, since the decision was > obviously ambiguous.) This is not always true. Depending on the logic family and actual circuit design of the flip-flop, it may be possible for the output voltage to momentarily sit in the guard band between the voltages that are defined as a valid "0" or "1" according to the design spec of the the logic family. If you don't wait for the feedback of this flip-flop to resolve to a voltage well outside of the guard band, then it is possible for two different gates connected to this flip-flop output to make (or not make!) opposite decisions as to whether this signal is a "1" or a "0". Not good if you are trying to, say, clear a counter and only some counter bits clear, or transition to a state machine NextState and end up in the wrong state, or even an illegal unrecoverable state. There are also other problems that propogating a metastable signal might cause, including increased shoot-thru power consumption, ground/power bounce and thus signal integrity issues with the local surrounding logic, etc. IMHO. YMMV. -- rhn A.T nicholson d.O.t C-o-MArticle: 90422
Thank you Newman and Syms, TNM_NET and TIMESPEC FROM TO seems to be exactly what I was looking for. StephanArticle: 90423
"Peter Alfke" wrote: >The popular misconception is that the output of a metastable latch or >flip-flop somehow indicates that it is metastable. Not true. This misconception may be caused by not understanding that almost all modern logic is buffered. If the FF or latch is buffered, as almost all other modern packaged logic is, the buffering will hide the metastable level from observation. Old stuff like original TTL wasn't buffered, and the metastable state of latches was observable with an analog storage scope. For old TTL FFs, all sorts of amusing glitches, odd voltages, and variations in delay between Q and Q_bar could be observed. Buffering a latch is a very good thing, as it makes the metastable condition resolve faster by reducing the loading on the cross coupled gates that are the latch. If you build a latch or FF out of gates, FETs or transistors, you could observe the metastable state(s), as the metastable levels would be voltages on the wires between the components of the circuit. All sort of amusing behavior may be observed, depending on design details, if the setup/hold time requirements are not respected. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90424
Hello, I have a design in a Virtex2 that uses RAMB16 primitives. In this design I access to this memory to write and read the same address at the same time. This gives a collision but over the board it has the expected result, it means, it write the data and put in the output the new data. Porting this design to a Virtex4 I found that the behaviour of the RAMB16 is different and the design doesnt work. I go around this problem adding some logic to avoid collisions in the memory. But my question is, is there any difference between RAMB16 primitive in Virtex2 and Virtex4? Regards Javier
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