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Currently, we purchased a Xilinx ML-310 Evaluation Board. The board comes with two Personality Module (PM) interfaces on which a total of 96 single ended IOs and 8 pairs of RocketIO reside. We are thinking of using the 96 single ended IOs, which according to the manual are 2.5V IOs. My question is: 1. Is it possible to feed these IOs with a 3.3 V input 2. If not, we are planning to use a Logic Level Translator to provide the 2.5 V. However, these LLTs require driven device to be CMOS compatible. Are these IOs CMOS compatible ? ThanksArticle: 90426
Look at the Library Guide entry for RAMB16. There are three WRITE_MODE parameter values that may underscore the difference between the two designs. I believe the Virtex2 RAMB16 primitive behaves like the "WRITE_FIRST" mode while the Virtex4 has the additional settings of "READ_FIRST" or "NO_CHANGE" for same-port read/write. Your synthesizer might change the default setting from "WRITE_FIRST" to something else, altering your expected behavior. "Javier Castillo" <jcastillo@opensocdesign.com> wrote in message news:knoqk1d441m502fphumu5hd5pp5jkrrip3@4ax.com... > Hello, > > I have a design in a Virtex2 that uses RAMB16 primitives. In this > design I access to this memory to write and read the same address at > the same time. This gives a collision but over the board it has the > expected result, it means, it write the data and put in the output the > new data. > Porting this design to a Virtex4 I found that the behaviour of the > RAMB16 is different and the design doesnt work. I go around this > problem adding some logic to avoid collisions in the memory. But my > question is, is there any difference between RAMB16 primitive in > Virtex2 and Virtex4? > > Regards > > JavierArticle: 90427
"Peter Alfke" wrote: >And for modern CMOS latches >and flip-flops, it will be a million times less likely if we can wait >one additional nanosecond, i.e. (x+1) ns. See XAPP094. For practical >circuits and frequencies x=3, or make it 4 if you are a pessimist. In case anyone wants to know, old TTL (74LS) needed about 20 ns excess delay for the same factor of a million reduction in metastability probability. To get the change of failure down to just once per 1000 years with a single FF you needed about 100 ns of excess delay. See Figure 8 in: http://focus.ti.com/lit/an/sdya006/sdya006.pdf 74S was even worse. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90428
Peter, the fact is that it may also be neither a '1' or a '0'. It can
drift around in the middle, change slowly from one to the other, change
at unpredictable times, sometimes multiple times, or even oscillate
depending on the precise circuit characteristics. Somwhere in my pile
of stuff I have a oscilloscope photograph of a TTL SN54??374 output
who's input signal was changing right in the middle of the set-up window
and made it go metastable every time, this was in a system that was
getting clocked at 6 MHz (this was back in 1989). When it hit the
metastability, it would oscillate with a perfect nearly rail to rail
sine wave at over 100 MHz, and it kept doing that with no apparent
decay until the next time the flip-flop was clocked 167 ns later, and
then it would abruptly stop. When I showed it to the project leader his
comment was "damn, there are radar guys here who have spent their whole
lives trying to do that". Point is, if you hit metastability, all bets
are off as to what that flip-flop will do between the clock edge that
tripped the metastability and the next clock edge. There is no
guarantee that it is going to be in either defined state, nor that if it
does wind up in one of the defined states that it will stay there, and
there are no guarantees that it will resolve within the clock period
either, as was shown in that example from my personal experience. I've
seen other instances where the output level just sort of wanders around
for quite a while before settling on one or the other state. In the
wandering around, it may cross the threshold voltages of the next gate
in the system several times.
Peter Alfke wrote:
>The popular misconception is that the output of a metastable latch or
>flip-flop somehow indicates that it is metastable. Not true. The
>metastable output (usually) has a perfectly valid level, 0 or 1 (and
>either one is as acceptable as the other, since the decision was
>obviously ambiguous.)
>The trouble is that this "proper" output can spontaneously change state
>at a completely unpredictable, non-deterministic moment. So you can get
>a state change that occurs at an unpredictable, non-synchronous moment,
>and that is what defies any attempt at a "solution".
>We can only say that any such bad transition occuring more than x ns
>after the last clock edge is very unlikely. And for modern CMOS latches
>and flip-flops, it will be a million times less likely if we can wait
>one additional nanosecond, i.e. (x+1) ns. See XAPP094. For practical
>circuits and frequencies x=3, or make it 4 if you are a pessimist.
>
>Peter Alfke, Xilinx Applications
>
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90429Symon wrote: > Would I do that? It reminds me of the funniest spelling mistake I > ever saw. I received an email which referred to a 'qwarty' keyboard. > He'd actually typed qwarty and, no, he didn't have a fancy layout > keyboard! LOL! What a classic! Regards, MarkArticle: 90430
>Would I do that? It reminds me of the funniest spelling mistake I ever saw. >I received an email which referred to a 'qwarty' keyboard. He'd actually >typed qwarty and, no, he didn't have a fancy layout keyboard! Best one I've seen recently was Litterature in an anti-spam group discussing the 2005 Ig Noble prizes: LITERATURE: The Internet entrepreneurs of Nigeria, for creating and then using e-mail to distribute a bold series of short stories, thus introducing millions of readers to a cast of rich characters -- General Sani Abacha, Mrs. Mariam Sanni Abacha, Barrister Jon A Mbeki Esq., and others -- each of whom requires just a small amount of expense money so as to obtain access to the great wealth to which they are entitled and which they would like to share with the kind person who assists them. http://www.improb.com/ig/ig-pastwinners.html -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90431
Georgios Sidiropoulos wrote:
> Can someone use logic operations or concatenation
> within port mapping statments on Xilinx ISE? for example:
PacketRAM: packet_dpram
PORT map (
data => CAV & DAV & KDATA, -- illegal. see below use ranges
wren => CAV or DAV, -- illegal. maybe in VHDL-2006
wraddress => packet_wraddress,
rdaddress => packet_rdaddress,
wrclock => LHC_CLK,
rdclock => INT_CLK,
q => packet0
);
Slicing arrays (of course insert the correct dimensions):
PacketRAM: packet_dpram
PORT map (
data(3 downto 0) => CAV,
data(7 downto 4) => DAV,
data(15 downto 8) => KDATA,
When doing this, always map all elements of data
and map all elements of data consecutively.
Cheers,
Jim
P.S. You might also try posting in comp.lang.vhdl for VHDL questions.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 90432The lpm_widthu parameter need sto be calculated & set by MegaWizard based on the size of FIFO chosen by the user. > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a > value. The design should be modified through the scfifo MegaWizard and should not changed manually. Hope this helps, Subroto Datta Altera Corp. <pinod01@sympatico.ca> wrote in message news:1129005330.788003.36580@g47g2000cwa.googlegroups.com... > To all, > > I have been attempting to load a lpm component into a Modelsim > project and when I get my test bench compiled and I try to simulate, I > get the following error. Note that vosq0_prestore_fifo (my own name) > is an instantiated VHDL LPM component from Altera Quartus software > using their scfifo function. Below shows the log window. The fatal > error is shown below and is detailed because for some reaoson I don't > know where to declare a value for the LPM_WIDTHU variable? I had > thought that this was already defined? Your help would be appreciated. > > Cheers > Pino > > # Loading work.vosq0_prestore_fifo(rtl) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl) > # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl) > # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl) > # Loading > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a > value. > # Time: 0 ns Iteration: 0 Instance: > /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14 > File: > QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd) > # FATAL ERROR while loading design > >Article: 90433
Jim Lewis wrote: > Georgios Sidiropoulos wrote: > > Can someone use logic operations or concatenation > > within port mapping statments on Xilinx ISE? for example: > > PacketRAM: packet_dpram > PORT map ( > data => CAV & DAV & KDATA, -- illegal. see below use ranges > wren => CAV or DAV, -- illegal. maybe in VHDL-2006 > wraddress => packet_wraddress, > rdaddress => packet_rdaddress, > wrclock => LHC_CLK, > rdclock => INT_CLK, > q => packet0 > ); > > > Slicing arrays (of course insert the correct dimensions): > PacketRAM: packet_dpram > PORT map ( > data(3 downto 0) => CAV, > data(7 downto 4) => DAV, > data(15 downto 8) => KDATA, > > When doing this, always map all elements of data > and map all elements of data consecutively. > > Cheers, > Jim > P.S. You might also try posting in comp.lang.vhdl for VHDL questions. > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim Lewis > Director of Training mailto:Jim@SynthWorks.com > SynthWorks Design Inc. http://www.SynthWorks.com > 1-503-590-4787 > > Expert VHDL Training for Hardware Design and Verification > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Cool Jim, Can slicing arrays be done on Verilog. I had XST warning on "unused" bits after a multiply, and indeed, some of the lsb bits were not used because they were truncated on purpose. I was wondering whether data slicing in Verilog was possible to alleviate dealing with the XST warning. -NewmanArticle: 90434
Any body please suggest any good tool to convert simulink model to equivalent RTL.Article: 90435
Ok, thanks. I have to think about another solution..my problem remains unsolved ClaArticle: 90436
I don't know any tool that convert simulink model to RTLbut you could use specific tools from altera (DSPBuilder) and I believe that Xilinx got is own. DSPBuilder is a librairy that permit you to developped your application under simulink and integrated it in your fpga. "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1129184609.080693.210040@g47g2000cwa.googlegroups.com... > Any body please suggest any good tool to convert simulink model to > equivalent RTL. >Article: 90437
Hello, Yes, I know it. In simulation I tried NO_CHANGE parameter and all works fine. In both designs when sinthesizing I used the "WRITE_FIRST" parameter but in Virtex2 it works and in Virtex4 not. Regards Javier On Wed, 12 Oct 2005 21:28:15 GMT, "John_H" <johnhandwork@mail.com> wrote: >Look at the Library Guide entry for RAMB16. > >There are three WRITE_MODE parameter values that may underscore the >difference between the two designs. I believe the Virtex2 RAMB16 primitive >behaves like the "WRITE_FIRST" mode while the Virtex4 has the additional >settings of "READ_FIRST" or "NO_CHANGE" for same-port read/write. Your >synthesizer might change the default setting from "WRITE_FIRST" to something >else, altering your expected behavior. > > >"Javier Castillo" <jcastillo@opensocdesign.com> wrote in message >news:knoqk1d441m502fphumu5hd5pp5jkrrip3@4ax.com... >> Hello, >> >> I have a design in a Virtex2 that uses RAMB16 primitives. In this >> design I access to this memory to write and read the same address at >> the same time. This gives a collision but over the board it has the >> expected result, it means, it write the data and put in the output the >> new data. >> Porting this design to a Virtex4 I found that the behaviour of the >> RAMB16 is different and the design doesnt work. I go around this >> problem adding some logic to avoid collisions in the memory. But my >> question is, is there any difference between RAMB16 primitive in >> Virtex2 and Virtex4? >> >> Regards >> >> Javier >Article: 90438
I found the problem. I was using Synplify 8.1 to implement the design and it seems that it has some problem using RAMB16 primitives. Using XST the design works fine. The same design using Synplify and Virtex2 also works. So I suposse there are a problem with my design and the Virtex4 mapper. Regards Javier On Wed, 12 Oct 2005 21:29:02 +0200, Javier Castillo <jcastillo@opensocdesign.com> wrote: >Hello, > > I have a design in a Virtex2 that uses RAMB16 primitives. In this >design I access to this memory to write and read the same address at >the same time. This gives a collision but over the board it has the >expected result, it means, it write the data and put in the output the >new data. >Porting this design to a Virtex4 I found that the behaviour of the >RAMB16 is different and the design doesnt work. I go around this >problem adding some logic to avoid collisions in the memory. But my >question is, is there any difference between RAMB16 primitive in >Virtex2 and Virtex4? > >Regards > >JavierArticle: 90439
Hello, Just wondering if anyone can let me know if I'm going about this the right way - I'm trying to implement the opencores Ethernet MAC on a Xilinx FPGA, but the board I have has too few I/Os. So, I want to reduce the width of the 32bit data inputs and outputs in the wishbone interface to accommodate (I'm about 70 IOBs short). It seems like this should be feasible since the data is delivered to the interface in 1 byte chunks. If I work around the byte counter and write the data to the FIFO right away without assembling the bytes into 32bits... I'm not so keen with verilog, so feel free to let me know if I'm going about this all wrong, or if I'm forgetting something. Or you can tell me I'm smoking something and that I should just not be cheap and get a board that has enough IOs. thanks! peiArticle: 90440
Tim, What part and package are you attempting to use? It has been my observation that when xilinx has put multiple V4 parts into a common package, the parts with fewer IOs will have their NC pins located in the middle of the left and right sides. Perhaps this is the case but without more specifics, I don't think anyone will be able to assist you. Pip www.oledatech.comArticle: 90441
Enver, Depending on your device resources, you might build a barrel shifter with a multiplier. This was described in http://www.xilinx.com/bvdocs/appnotes/xapp195.pdf PipArticle: 90442
pei@uwiep.com wrote: > Hello, > > Just wondering if anyone can let me know if I'm going about this the > right way - > > I'm trying to implement the opencores Ethernet MAC on a Xilinx FPGA, > but the board I have has too few I/Os. So, I want to reduce the width > of the 32bit data inputs and outputs in the wishbone interface to > accommodate (I'm about 70 IOBs short). It seems like this should be > feasible since the data is delivered to the interface in 1 byte chunks. > If I work around the byte counter and write the data to the FIFO right > away without assembling the bytes into 32bits... > > I'm not so keen with verilog, so feel free to let me know if I'm going > about this all wrong, or if I'm forgetting something. Or you can tell > me I'm smoking something and that I should just not be cheap and get a > board that has enough IOs. > > thanks! > > pei > You're putting the wishbone interface externally ? To connect it to what ? SylvainArticle: 90443
Martin Thompson <martin.j.thompson@trw.com> writes: > There's a great series of scope shots of real automotive transients > from things like windscreen wipers in a paper I can't find at the > moment - regular 70V spikes every time the intermittent wipers > triggered IIRC! I'll try and dig them out... > Found them - in the proceedings of the Automotive EMC Conference 2003 "Transient Test Requirements for e-Marking - Necessity or Bureaucracy?" Unfortunately not available for free as far as I can tell :-( One car generated -110V with 8ns rise time when the fan speed for the heater was changed! The intermittent wipers were only 25V, 80ns risetime - quite tame really. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 90444
Who can tell me where I can find the introductions to the IO interface standard of fpga(For example,LV TTL,LV CMOS,GTL,GTL+,CTT)? If there is some books,please tell me their names. Thanks very much!Article: 90445
I haven't used Synplify for a while, but it used to add a 'collision wrapper' around dual port block rams unless you turned off an option, something like syn_ramstyle="no_rw_check" ( or there may be a "don't mess with instantiated primitives" option somewhere ) Brian Javier Castillo wrote: > I found the problem. > > I was using Synplify 8.1 to implement the design and it seems that it > has some problem using RAMB16 primitives. Using XST the design works > fine. > The same design using Synplify and Virtex2 also works. So I suposse > there are a problem with my design and the Virtex4 mapper. > > Regards > > Javier >Article: 90446
vssumesh wrote: > Any body please suggest any good tool to convert simulink model to > equivalent RTL. > Look on the Xilinx website. There is a tool called System Generator for DSP. You get a special simulink toolbox to create your logic. -EliArticle: 90447
zqhpnp@gmail.com wrote: > Who can tell me where I can find the introductions to the IO interface > standard of fpga(For example,LV TTL,LV CMOS,GTL,GTL+,CTT)? If there is > some books,please tell me their names. Most (if not all) of these are JEDEC-standards and can be downloaded from www.jedec.org. Look for JESD8. Kolja SulimmaArticle: 90448
Hi Javier,
Javier Castillo wrote:
>I found the problem.
>
>I was using Synplify 8.1 to implement the design and it seems that it
>has some problem using RAMB16 primitives. Using XST the design works
>fine.
>The same design using Synplify and Virtex2 also works. So I suposse
>there are a problem with my design and the Virtex4 mapper.
>
>
very likely simplify doesn't propagate the bram attribute further (but
xst does) , what I would try is to run netgen to generate a back
annotated netlist after ngdbuild (translate) and try to see if the
atteibute is attached to the bram correctly.
I realy don't see this coming from mapper (assuming mapper is xilinx MAP
app) but I can investigate for you is you give me some files.
I think the default value for this attribute has change from V2 to V4
and this will explain difference in behaviour when this is not set by
the synthesizer.
Cheers,
Aurash
>Regards
>
>Javier
>
>
>On Wed, 12 Oct 2005 21:29:02 +0200, Javier Castillo
><jcastillo@opensocdesign.com> wrote:
>
>
>
>>Hello,
>>
>> I have a design in a Virtex2 that uses RAMB16 primitives. In this
>>design I access to this memory to write and read the same address at
>>the same time. This gives a collision but over the board it has the
>>expected result, it means, it write the data and put in the output the
>>new data.
>>Porting this design to a Virtex4 I found that the behaviour of the
>>RAMB16 is different and the design doesnt work. I go around this
>>problem adding some logic to avoid collisions in the memory. But my
>>question is, is there any difference between RAMB16 primitive in
>>Virtex2 and Virtex4?
>>
>>Regards
>>
>>Javier
>>
>>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 90449Hi, I am writing a verilog code whereby I read data from a txt file and use it in one of the modules. I want to store the data from the .txt file on to FPGA, where it can be used by other modules. How can I embedd the .txt file in synthesis? Does Xilinx have a way of doing it so that the .txt file information is included in the .bit file which is burned on the FPGA? Robert.
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