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Hi Robert, your first idea appears often in a designers mind, because it works so well in simulation. But in synthesis the tool is not executing your code, only analyzing it and looking for synthesizable parts. The rest of the code will be ignored in the best case or gives you errors and warnings. If you want to develop FPGAs with certain RAM contents defined by some other tool before synthesis you better try this flow: - develop your design assuming that your RAM/ROM contents are available after startup. - after PAR extract the paths to your memeory elements e.g. by using the floorplanner tool (maybe there are other ways too). - write a BMM file (even if XILINX still makes a big secret of the syntax. :-) Read some examples, that helps.) - use the data2mem tool to patch your bitstreams with the actual memory contents generated by your special tool or script (provide the correct file format for data2mem) For Simulation, if you are using modelsim 6.xx, you can work similar to the above flow. -Load your design and your testbench into vsim. - use the mem load command to initialize the memory elements in your design (you can find out about the correct file syntax by filling some pattern directly into your memory with mem load and then storing it with mem save) This way you don't need to use your HDLs file io anymore inside your design and have similar flows for synthesis and simulation. have a nice synthesis Eilert Robert wrote: >I am writing a verilog code whereby I read data from a txt file and use >it in one of the modules. I want to store the data from the .txt file >on to FPGA, where it can be used by other modules.Article: 90476
On 10 Oct 2005 11:06:34 -0700, "river064" <river064@gmail.com> wrote: >Hi, all. > >I'm newbie in circuits, >and I have a silly question. > >Suppose that one FPGA device has about 100 Vcc pins >(including VCCINT, VCCO, VCCAUX) and 80 GND pins. >Then how many decoupling capacistors are needed >for this IC? How can I decide that quantity? > We use multilayer boards with a solid ground plane layer and, when possible, one additional plane for each supply. But we often split a plane between, say, VCCINT and VCCAUX to save layers, one supply pour "inside" the chip footprint and the other "outside". We generally use four 0805 or 0603 ceramic caps, 0.33 uF each usually, per supply per chip, 12 caps total for a typical FPGA. Works fine. I've never done a multilayer board that had too few bypass caps. 12 per FPGA may be too many, for all I know. TDR testing and real-life noise measurement have convinced me that using huge numbers of caps, or mixing cap values, isn't beneficial. JohnArticle: 90477
On 13 Oct 2005 11:39:06 -0700, "Robert" <robertsolanki@gmail.com> wrote: >^Thanks! >Also, when you say cutting and pasting into VHDL code, do you mean that >I'll have to do this each time the data in my txt file changes? The answer to this would typically be yes. >The >data I generate in the text file will change depending on my inputs. I >need a way so that I can quickly load/initialize the RAM with the new >values from txt file. I'm confused by this. In your earlier post, you said that the text file was created by a Python program. You then wanted a way to take this text, and encode it somehow and have it included in the bitstream that configures the FPGA. There are many ways to do this, and some have been described by other posters to your question. By "inputs" do you mean signals to your FPGA, or parameters to your Python program? If there is a small set of inputs, then I guess you could build them all and load them all into the FPGA (needs N x memory), and select at runtime what you need. If the parameters are unbounded, then you need a more complex process, since this implies running Python for each change in the inputs. >Thanks in advance. >Robert. Ray pointed out that a cut-and-paste process can be used to get from a text file to a block of VHDL/Verilog initializer statements, or with Xilinx's data2mem program. If you find yourself going down this path, I highly recommend that use an editor program that includes a "column edit" mode, and maybe also a hex mode. My favorite editor is UltraEdit, that is reasonably cheap, and an excellent programmer's editor. Philip Philip Freidin FliptronicsArticle: 90478
Hi My company wanted to buy PCI core(33Mhz), and it should be fitted in spartan-3 fpga and should not take not more than 350 slices Does any one have got any idea from where i can get this PCI core ? pls mail to pbijoy@rediffmail.com rgds bijoyArticle: 90479
Just out of curiosity John, it seems like you are suggesting designing around your own SDRAM chips is much harder than using a module - while I have used neither, I would think using SDRAM ic's are easier since you can place them better - and I don't see the big issue about SI, its' 100 MHz after all (or 133). I mean, I agree, you shouldn't use 2-layer, but with 4-layer, unless you are weaving in and out and going all around the board, simple matched trace lengths with some series R's should do it, no? I ask because I'm doing my first design around SDRAM, and now would be a good time to find out how doomed I :) Regarding the original question however, John answered it well - don't try and cheat by only connecting half the VDD's or whatever. They used multiple VDDs for a reason, and they expect you to make use of that. On a 4-layer board, this wouldn't be a problem if you had planes - but 2 layer, I can see why you want to minimize the pin usage. I think you may waste more money than if you were to just have gone with a 4 layer to start... $140 for 2 pieces isn't that bad, is it? JArticle: 90480
Who can give me(A fresh man) some advice about the FPGA learning,and how to become an expert in it.Please recommend some materials to me. Thanks!Article: 90481
Hi everybody! Synplify Pro offers Retiming, which allows register relocation across combinatorial logic. However, this does not work with the embedded 18x18 multipliers. Does anybody know how to make the retiming work, i.e. that Synplify Pro moves registers accross multipliers? Or does there exist another tool capable of that? Best Regards, SimonArticle: 90482
"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag news:ee90d8e.-1@webx.sUN8CHnE... > Hi My company wanted to buy PCI core(33Mhz), and it should be fitted in spartan-3 fpga and should not take not more than 350 slices Does any one have got any idea from where i can get this PCI core ? pls mail to pbijoy@rediffmail.com > > rgds bijoy there are several free PCI cores as well, one that is very simple and small can be downloaded from the lattice website. it defenetly works in S3 and is sure less than 350 slices. but I think the license doesnt promote using it in non lattice silicon. anttiArticle: 90483
I didn't really have control over including the original note on google when I replied. My (not always reliable) news reader at work (once my PC was up and running again) showed the origninal message as well. I generally try to include the pertinent parts of the original post when responding, but posting through google is a different ball of wax. - John_H "Jeremy Stringer" <jeremy@_NO_MORE_SPAM_endace.com> wrote in message news:434ee100$1@clear.net.nz... > John_H wrote: >> Even if your design runs very slow, the SDRAM module has high current >> demands. >> >> Since all the VSS and VDD pins are connected, you still need to connect >> all the pins on the module. Would you consider it safe to ride in a >> hot-air balloon where the basket is attached by one small rope? It may > > [cut] > > Did anyone else miss the message that this is in reply to? I found it > using google, but it didn't come down on my newsfeed. > > JeremyArticle: 90484
^Thanks Philip and Eilhert. A clarification for Philip: I need to generate different data files using Python scipts and then want to store this on the FPGA. The inputs I was talking about was for the python, which will generate different output data files each time. I am not sure if it would be possible to store all of the possible data file outputs from Python onto the FPGA. Consequently, cut-paste won't be a very good option here. For general audience: I just found out there in Altera, its possible to define your data into a very simple memory format (addresses and data). This file can then be used to intialize the RAM/ROM on to the FPGA. I am quite sure it can be done on Xilinx as well. But I am don't know how to do it. Can somebody show steps as to how to initialize the memory? Obviously, sample codes are not that easy to find. Robert.Article: 90485
<jai.dhar@gmail.com> wrote in message news:1129295345.792785.282840@g47g2000cwa.googlegroups.com... > Just out of curiosity John, it seems like you are suggesting designing > around your own SDRAM chips is much harder than using a module - while > I have used neither, I would think using SDRAM ic's are easier since > you can place them better - and I don't see the big issue about SI, > its' 100 MHz after all (or 133). I mean, I agree, you shouldn't use > 2-layer, but with 4-layer, unless you are weaving in and out and going > all around the board, simple matched trace lengths with some series R's > should do it, no? SI is still an issue because it's not the frequency, it's the edge rates. Working with ICs can be easier than working with modules for 1-3 chip designs. The original poster wanted to use a single layer board (?!) which wouldn't support most modern devices' current needs and still maintain any semblence of logic levels. If you *know* what you're doing, a 2-layer board can work. Decoupling becomes more critical since the VCC impedance will be significantly dependent on the caps and their locations versus the 4-layer board that has a low impedance from many distributed decoupling caps to the chips. If modules are used (my latest experience was DDR-2s) there may be a VCC "region" separate from the grounds requiring decent decoupling between the 2-layer board's ground plane and the VCC pins for the module to keep the return current for the address/control signals from crosstalking significantly through the return paths. SI for a single line can easily be tamed with appropriate termination schemes. A multitude of signals, however, require good terminations *and* good return paths. The larger problem on a 2-layer board may be the bounce provided by poor VCC impedances even if the ground impedance is kept reasonably solid. It's the edges we worry about most, not the frequency. > I ask because I'm doing my first design around SDRAM, and now would be > a good time to find out how doomed I :) If you have the experience under your belt to understand what kind of crosstalk and chip-rail related I/O overshoot/undershoot you get with chips that handle the edge rates of your memories, you have a good chance of not being doomed. If you push up to 4 layers to keep solid VCCs and grounds and stay aware of the return paths for your signals (especially your clocks) you should be golden. > Regarding the original question however, John answered it well - don't > try and cheat by only connecting half the VDD's or whatever. They used > multiple VDDs for a reason, and they expect you to make use of that. On > a 4-layer board, this wouldn't be a problem if you had planes - but 2 > layer, I can see why you want to minimize the pin usage. I think you > may waste more money than if you were to just have gone with a 4 layer > to start... $140 for 2 pieces isn't that bad, is it? > > J The cost of 4 layer boards isn't outrageous these days even in prototype quantities. The headaches from a 2-layer board aren't worth the difference in prototype costs unless you have nothing better to do than enjoy the extra weeks figuring out why your design is flakey (which some people might!) - John_HArticle: 90486
"Robert" <robertsolanki@gmail.com> wrote in message news:1129303985.046433.284290@g49g2000cwa.googlegroups.com... > I am quite sure it can be done on Xilinx as well. But I am don't know > how to do it. Can somebody show steps as to how to initialize the > memory? Obviously, sample codes are not that easy to find. > Hi Robert, Yeah, as Philip and Eilhert said, it looks like you want to use the data2mem program. This puts the data from a simple format .mem text file into your fully placed and routed Xilinx configuration bit file. This way you don't need to do a P&R every time you change the data. It's all in the documentation with examples IIRC. HTH, Syms.Article: 90487
Well put. I'm aware it's all about edge-rates, but not having the Micron datasheet handy, it was easier to fire off the frequency :) Besides, you rarely see a 10 MHz signal with the edge rate typically found in a 10 Gbps signal... at least I haven't! I definitely recommend a thorough 3+ readings of Howard johnson's High-speed digital design - for those interested in SI (just as an aside). I am definitely using 4-layer for my upcoming design, so return paths shouldn't be a problem. I'm more concerned about how I can't verify the SI on the board since I don't have a scope at all... are simple series-end terminators sufficient for SDRAM, or are more complicated termination schemes advised? PS: I don't mean to hijack the thread - I just thought since my questions are relevant, and potentially of interest to the poster, I would post here...Article: 90488
I stand corrected.... I was a customer then. Austin Peter Alfke wrote: > Since I am the oldest Xilinx veteran here ( Jan 88), I can answer with > authority: > > The first part, in 85, was the 2064 (named after the number of CLBs in > the matrix), followed soon by the 2018, named after the (contentious > forever) number of gate equivalents. > The 3000 series was introduced in the following sequence (sorry Austin, > I was there): > 3020 in late 87, 3090 was the second (!) in mid 88. 3042 came soon > after and becamemost popular, then (early 89?) the 3062 as the > last-born and forever least popular. > The 0riginal 3090 die was exactly 100 square-millimeters, but it was > not 10x10 since we wanted to fit two masks into the biggest possible > square reticle, so it was something like 12.5 x 8 mm, and we proudly > depicted it (to scale) on the back of the data book. Xilinx has, > forever since, always pushed manufacturing to offer the biggest > possible top-end device, because we know that there are designers > salivating for something even bigger, and the unavoidably high price is > grudgingly accepted when there is no alternative. > > Process shrinks were done more quietly in those days, since they did > not affect the user with a change in supply voltage. Those were the 5-V > days, when everybody used the same Vcc :-) > > 3000A was a functional superset, and 3100 offered higher speed through > "pumped gates", internally generating a higher Vcc for certain circuit > detailss. Also a new top-end, the 3195. > I wrote a candid comparison of the various 3000 families and published > it at the front of the family datasheet, with an innovative > 3-dimensional picture... > See: http://direct.xilinx.com/bvdocs/publications/3000.pdf > Peter Alfke, Xilinx Applications >Article: 90489
zqhpnp@gmail.com wrote: > Who can give me(A fresh man) some advice about the FPGA learning,and > how to become an expert in it.Please recommend some materials to me. > Thanks! > First, even though vendors and some professors may think you can do complex things easily with the modern tools without a whole lot of knowledge about the underlying hardware (a.k.a System Generator), Learning basic logic is ******VERY******* important. I got in an argument with a professor at the college here about these tools. It was stated that even though there is a lack in good engineers coming out of college, "We Scientists" don't need them. In 5 minutes, I can use Xilinx tools to "download" a complete mathematical system to a chip. This is true for the trivial examples that comer with the development tools, but for any real world system alot more work will needed. So, if you fundamentally don't understand D-Latchs, Synchronous Design, etc, you will never become an expert. You may learn the tools well enough to connect functional blocks together, but you need a solid foundation in logic design, electronics (yes, transistors and all the basic theory) to have a good grasp. Second, the way I like to learn is to think about something I want to make (i.e. some cool gadget), and then figure out the tools to implement my creation. You will learn more by fixing your own broken logic, badly soldered connections and bad technical documentation than you will trying to come up with the next theory on FSMs (not to say that isn't important). You will also gain some tools along the way to will make yourself useful to an employer some day. Maybe a good way to start is to get one of those low cost CPLD boards from Digilent and blink some LED's. You can even get you advisor to get a university donation from Xilinx if the stuff is used in class. Don't worry about getting the lastest and greatest Virtex chip, use one of the small CPLDs to get started. Try to some LEDs to blink, see if you can do some things with the switches on the PCB. Fundamentally, if you can't make LEDs blink, it doesn't make sense to try anything else. Learning an HDL (I like verilog) will be very useful. But for now you can use the schematic entry tools that come with the Xilinx (or Altera, etc.) to make you first simple design. Hope this helps...... -EliArticle: 90490
In addition to the tools mentioned above, please note that AccelChip Inc. offers an algorithmic synthesis tool from MATLAB to target-optimized RTL. Some designers find the MATLAB language-based approach is their preferred design entry method, but AccelChip's tool is also integrated with Simulink and Xilinx System Generator for DSP. Further information sources are as follows. - Datasheets for synthesis tools and DSP IP core generators at http://www.accelchip.com/datasheets/ - Conference technical papers and white papers at http://www.accelchip.com/papers.htmlArticle: 90491
>The cost of 4 layer boards isn't outrageous these days even in prototype >quantities. The headaches from a 2-layer board aren't worth the difference >in prototype costs unless you have nothing better to do than enjoy the extra >weeks figuring out why your design is flakey (which some people might!) Even if you are sure that your final target is 2 layers, it might be better to use 4 on the prototype stage to reduce the risk and get the software guys off the ground and off your back. Then you can work on making 2 layers work in parallel with software development. And if your new/inexpensive boards crash occasionally when the old/prototype ones don't, the software guys have a good claim that their code is not the problem. (Assuming you didn't make many other changes so you can run the same code.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90492
Hello, I am a beginner with fpgas with practically no experience with this material, working as an undergraduate researcher under a graduate student and a professor at the University of Maryland. They have asked me to find out a few things about the Linux capabilities on the xilinx ml300 board I am playing with. Under the documentation on the xilinx site, the microdrive has a version of Montavista Linux 2.1 already installed on it, which can be booted. However, after logging in, I'm not able to really do anything because the drive is set as read-only. Everything I have found on the web about the ml300 board and Linux refers to porting a newer version onto the board, which confuses me as to why. I was wondering what the problem with the already installed Linux was or where I could find information on how to use it, especially it's TCP/IP capabilities. Any help or advice from anyone would be greatly appreciated, thank you. Eric YehArticle: 90493
Hal Murray wrote: >>The cost of 4 layer boards isn't outrageous these days even in prototype >>quantities. The headaches from a 2-layer board aren't worth the difference >>in prototype costs unless you have nothing better to do than enjoy the extra >>weeks figuring out why your design is flakey (which some people might!) > > > Even if you are sure that your final target is 2 layers, it might > be better to use 4 on the prototype stage to reduce the risk and > get the software guys off the ground and off your back. > > Then you can work on making 2 layers work in parallel with software > development. And if your new/inexpensive boards crash occasionally > when the old/prototype ones don't, the software guys have a good claim > that their code is not the problem. (Assuming you didn't make many > other changes so you can run the same code.) Very good advice - and often you can finish the 4 layer design faster, so gain valuable up-front time. You can also probe to find which nets are the really noisy ones, and so need special care on the 2 layer design. Also, there is nothing quite like this to focus a bean-counters mind : "You can have this one for $Y, that works, or this one, for a saving of ZZc, that fails EMC, and is not as reliable ?" :) On 2 layer, placing physically small SMD CAPS on the opposite PCB side, right underneath the FPGA, can also buy some trade off. There are BGA packages especially designed for 2 layer PCBs, so it can be done, but the FPGA vendors currently have other priorities. It may come that they chase lowest applied cost, and target 2 layer applications, and also include caps in their BGA stackups. [ Which is really just a tiny multilayer PCB anyway ] -jgArticle: 90494
"jai.dhar@gmail.com" <jai.dhar@gmail.com> writes: > I'm more concerned about how I can't verify the > SI on the board since I don't have a scope at all... Do yourself a favor and buy or rent a scope. You can get a used Tek 485 scope (350 MHz) for under $500, but 350 MHz isn't really fast enough to fully check SI for a 100 MHz SDRAM interface. Still, it will let you spot gross SI problems.Article: 90495
It is very likely that the Linux filesystem on the MicroDrive has been corrupted, for example by powering the board down without following a proper shutdown sequence. On a reboot Linux then recognizes the corrupt filesystem and mounts it read-only. There are two ways out of this: 1. Reimage the MicroDrive. To do so follow the documentation provided with ML300. 2. Put the MicroDrive in a CF reader and attach it to your Linux workstation/PC (or boot your PC from a Knoppix CD). Then, check the filesystem with the following command (as root under the assumption that the Linux kernel recognizes the MicroDrive as /dev/sda): # e2fsck /dev/sda3 You might want to read the man page of e2fsck for more information. - Peter Eric Yeh wrote: > Hello, I am a beginner with fpgas with practically no experience with this > material, working as an undergraduate researcher under a graduate student > and a professor at the University of Maryland. > > They have asked me to find out a few things about the Linux capabilities on > the xilinx ml300 board I am playing with. > > Under the documentation on the xilinx site, the microdrive has a version of > Montavista Linux 2.1 already installed on it, which can be booted. However, > after logging in, I'm not able to really do anything because the drive is > set as read-only. Everything I have found on the web about the ml300 board > and Linux refers to porting a newer version onto the board, which confuses > me as to why. I was wondering what the problem with the already installed > Linux was or where I could find information on how to use it, especially > it's TCP/IP capabilities. > > Any help or advice from anyone would be greatly appreciated, thank you. > > Eric Yeh > >Article: 90496
<jai.dhar@gmail.com> wrote in message news:1129309865.211686.182910@f14g2000cwb.googlegroups.com... > Well put. I'm aware it's all about edge-rates, but not having the > Micron datasheet handy, it was easier to fire off the frequency :) > Besides, you rarely see a 10 MHz signal with the edge rate typically > found in a 10 Gbps signal... at least I haven't! I definitely recommend > a thorough 3+ readings of Howard johnson's High-speed digital design - > for those interested in SI (just as an aside). > > I am definitely using 4-layer for my upcoming design, so return paths > shouldn't be a problem. I'm more concerned about how I can't verify the > SI on the board since I don't have a scope at all... are simple > series-end terminators sufficient for SDRAM, or are more complicated > termination schemes advised? <snip P.S.> If your signals are all piont-to-point, source series terminations are great. If your signal traces are under 2", don't bother with the series terminations where the edge slew will be much longer than the round-trip delay and you might get worse performance adding all the vias for the resistors. If you have multiple destinations, the source series terminations might not do you the good you hope they will. If your topology isn't simple, free SI tools for simple simulations appear to be available.Article: 90497
Here's some more history (from a long term Xilinx user): There was a time when companies didn't trust any part that didn't have a second source, so companies would license their designs to other manufacturers. So Xilinx licensed its designs to AMD, and then later to ATT. So you could buy a 2064 from AMD, and 3000 series parts from ATT. In both cases, for various reasons, Xilinx cancelled the agreements. ATT didn't want to get out of the business, so they made their own FPGAs, called the Orca family, roughly similar to the XC4000 family. ATT later became Agere, and Agere later sold the Orca family to Lattice, where you can still buy it.Article: 90498
Here's some more history from a long time Xilinx user: There was a time when companies didn't trust any ICs that were not second sourced (more than one manufacturer). So Xilinx licensed their designs to AMD, and then later to ATT. You could buy a 2064 from AMD and later a 3000 series part from ATT. For various reasons Xilinx cancelled these agreements (there's no doubt some interesting stories here). ATT didn't want to get out of the FPGA business so they developed their own Orca line, roughly equivalent to the XC4000 family. The IC devision of ATT later spun off to become Agere. Agere later sold the Orca line to Lattice, where you can still buy it.Article: 90499
Sorry for the double post. The system said it couldn't process my reply, so I had to retype it from memory. Now I find out it went through!
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