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Philip Freidin wrote:
>On 13 Oct 2005 11:39:06 -0700, "Robert" <robertsolanki@gmail.com> wrote:
>
>
>>^Thanks!
>>Also, when you say cutting and pasting into VHDL code, do you mean that
>>I'll have to do this each time the data in my txt file changes?
>>
>>
>
>The answer to this would typically be yes.
>
>
>
>>The
>>data I generate in the text file will change depending on my inputs. I
>>need a way so that I can quickly load/initialize the RAM with the new
>>values from txt file.
>>
>>
>
>I'm confused by this. In your earlier post, you said that the
>text file was created by a Python program. You then wanted a
>way to take this text, and encode it somehow and have it included
>in the bitstream that configures the FPGA. There are many ways to
>do this, and some have been described by other posters to your
>question.
>
>By "inputs" do you mean signals to your FPGA, or parameters to
>your Python program?
>
>If there is a small set of inputs, then I guess you could build
>them all and load them all into the FPGA (needs N x memory), and
>select at runtime what you need. If the parameters are unbounded,
>then you need a more complex process, since this implies running
>Python for each change in the inputs.
>
>
>
>>Thanks in advance.
>>Robert.
>>
>>
>
>Ray pointed out that a cut-and-paste process can be used to get
>from a text file to a block of VHDL/Verilog initializer statements,
>or with Xilinx's data2mem program. If you find yourself going down
>this path, I highly recommend that use an editor program that
>includes a "column edit" mode, and maybe also a hex mode. My
>favorite editor is UltraEdit, that is reasonably cheap, and an
>excellent programmer's editor.
>
>
>Philip
>
>
>
>
>Philip Freidin
>Fliptronics
>
>
If this is something you are going to be changing several times, it
might not be unreasonable to write a translator that takes your text
input and outputs a VHDL package containing the memory contents as a
constant array. I've done that both in 'C" and in Matlab, as well as in
non-synthesizable VHDL. The file containing the package just gets
included with the rest of the files at design time. That way, you don't
have to touch any of your design files, just one file containing a
package that has your data in it. You can also generate the data file
in the Xilinx .coe file format and load the data into the memories at
compile time.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90501Hi Ray, So, why isn't it better to use 'C'/'Matlab'/Perl to generate a .mem file that data2mem loads into the previously compiled .bit file? It still meets the 'you don't have to touch any of your design files' criterion, but saves a P&R each time you change the memory contents. Cheers, Syms. http://toolbox.xilinx.com/docsan/xilinx7/de/dev/data2b.pdfArticle: 90502
To be precise: Xilinx licensed MMI before that company got swallowed up (there are uglier words for that procedure) by AMD. Soon after that, Xilinx bought the rights back from AMD (who made a nice profit from the Xilinx shares...) For XC4000, ATT was supposed to be the prime manufacturer, not only the second source. That really did not work out. We are now much better off with our friends in Taiwan (UMC) and Japan (Toshiba). "Second source" seems to be a forgotten word now, and the world is a better place without it. Peter AlfkeArticle: 90503
Start with the Spartan 3 development board available for $99 on the xilinx website. Eli Hughes wrote: > zqhpnp@gmail.com wrote: > > Who can give me(A fresh man) some advice about the FPGA learning,and > > how to become an expert in it.Please recommend some materials to me. > > Thanks! > > > > > First, even though vendors and some professors may think you can do > complex things easily with the modern tools without a whole lot of > knowledge about the underlying hardware (a.k.a System Generator), > Learning basic logic is ******VERY******* important. I got in an > argument with a professor at the college here about these tools. It was > stated that even though there is a lack in good engineers coming out of > college, "We Scientists" don't need them. In 5 minutes, I can use > Xilinx tools to "download" a complete mathematical system to a chip. > This is true for the trivial examples that comer with the development > tools, but for any real world system alot more work will needed. > > > So, if you fundamentally don't understand D-Latchs, Synchronous Design, > etc, you will never become an expert. You may learn the tools well > enough to connect functional blocks together, but you need a solid > foundation in logic design, electronics (yes, transistors and all the > basic theory) to have a good grasp. > > Second, the way I like to learn is to think about something I want to > make (i.e. some cool gadget), and then figure out the tools to implement > my creation. You will learn more by fixing your own broken logic, badly > soldered connections and bad technical documentation than you will > trying to come up with the next theory on FSMs (not to say that isn't > important). You will also gain some tools along the way to will make > yourself useful to an employer some day. > > Maybe a good way to start is to get one of those low cost CPLD boards > from Digilent and blink some LED's. You can even get you advisor to get > a university donation from Xilinx if the stuff is used in class. Don't > worry about getting the lastest and greatest Virtex chip, use one of the > small CPLDs to get started. Try to some LEDs to blink, see if you can > do some things with the switches on the PCB. Fundamentally, if you > can't make LEDs blink, it doesn't make sense to try anything else. > > Learning an HDL (I like verilog) will be very useful. But for now you > can use the schematic entry tools that come with the Xilinx (or Altera, > etc.) to make you first simple design. > > Hope this helps...... > > -EliArticle: 90504
There is a reference EDK project that drives the VGA port at www.xilinx.com/ml403 . XAPP717 written for the ML403 has a pretty cool demo too.Article: 90505
Aurelian Lazarut: Thanks for your answers,I'm a learner.I don't understand what you said about it,can you say detaily.I use Synplify Pro to synthesis it,it gives me:@E:Internal Error @E:"F:\Xilinx\ColorConvertor\csc_top.vhd":95:8:95:14|Can't find library simprim @E:"F:\Xilinx\ColorConvertor\csc_top.vhd":96:27:96:27|use: simprim is not a library @E:"F:\Xilinx\ColorConvertor\csc_top.vhd":97:24:97:24|use: simprim is not a library @E:"F:\Xilinx\ColorConvertor\csc_top.vhd":96:27:96:27|Identifier simprim is not declared @E:"F:\Xilinx\ColorConvertor\csc_top.vhd":97:24:97:24|Identifier simprim is not declared what is it?Why?Thank you very much!Article: 90506
Have You got any experiences running design software for windowses under WINE & Linux? The devices I'd like to design for are Lattice ispLSI1016/1032/E and Xilinx XC9572/XL. I have ispDesignExpert 8.4 installed for Windows. And a recent Xilinx Webpack.Article: 90507
Hi We have already got a PCI core from xilinx to experiment, and it takes 530 slices, presently we are using 200K spartan-3, we have some more logic and it takes about 1200 slices altogether. but the cost requirement of my project wants us to use spartan-3e-100K device, which has got only 1000 slices. Thank you for your suggestion, i will look into the lattice option, if the fpga cost is suitable for us regards bijoyArticle: 90508
The number and value of caps has a minimum, of course. Much depends on the speed you are running the device at and the current profile. If you have large pulsed currents (as you would if you implement a processor core and connect to external memory) you will need both more bulk bypass and high frequency bypass than if you are using (almost) constant current differential drivers for something. Board layout is key, of course. As John notes, a good plane system works wonders (and works really well if you can have the ground and power planes adjacent). So the answer is 'it depends on the power / speed / current profile for your implementation'. Cheers PeteSArticle: 90509
All excellent advice (especially about the scope!) Putting down chips rather than a stick has pros and cons - on the one hand, it is possible to control the part positioning, but the layout rules (especially length match) become quite complex if there are more than a couple of devices involved. A stick, on the other hand, has a single interface point (although one must then live with it taking much of the timing budget). Micron used to have a SDRAM app note with a 4 layer layout which can be an excellent starting point for someone without much experience. A typical single ended via adds around 0.2 - 0.5dB of frequency dependent loss (at around 500MHz) which will add to deterministic jitter on the signal, so the advice about considering vias is very important. As already noted, there are a host of things to be considered for successful SDRAM / DDR design. I would strongly suggest reading High Speed Digital Design. A Handbook of Black magic by Howard Johnson if you have not done this type of design before. Cheers PeteSArticle: 90510
Simon Heinzle wrote: > Hi everybody! > > Synplify Pro offers Retiming, which allows register relocation across > combinatorial logic. However, this does not work with the embedded 18x18 > multipliers. > > Does anybody know how to make the retiming work, i.e. that Synplify Pro > moves registers accross multipliers? Or does there exist another tool > capable of that? In general this is not possible because of the initialization problem. If you have registers after the multiplier that are initialized to a prime numberer larger than 18 bits and you retime them to the inputs of the multipliers there is no reset value for these registers that yields the same circuit behaviour. Even for numbers were it is possible you need to solve a complicated satisfiability problem. Of course most registers are initialized to 0 s there could be a special case implemented for that. Kolja SulimmaArticle: 90511
Hi all, Thinking of a 5 stage pipeline risc. 1. fetch 2. decode 3. execute 4. buffer 5. write back The result of execution stage is buffered at the +ve edge of the buffer cycle. And this works if we enable the data forwarding method. And the next instruction will get the updated values from the buffer register at its execution stage. And the buffered data will be placed to memory ony at the write back stage. My doubt is if this is true where will we buffer the output of the execution stage of the second instruction at the +ve edge of its buffer cycle as the buffer is still holding the result of the previous instruction. I am a beginer to these type of things. This is similar to the ARM9 pipeline. Whats their way of tackling this situation.Article: 90512
Symon wrote: > So, why isn't it better to use 'C'/'Matlab'/Perl to generate a .mem file > that data2mem loads into the previously compiled .bit file? It still meets > the 'you don't have to touch any of your design files' criterion, but saves > a P&R each time you change the memory contents. If you need to simulate the design with the block ram initialized data2mem will not help. Any given project may benefit from one, or at different times in the life cycle, both approaches. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 90513
Please tell me the process involved. Is the ASICS are manufactured in the big manufacturing places like ordinary ICs. Or is there any way we can do it in our own lab. I am experianced only with FPGAs. Can we convert an RTL written for the FPGA to ASIC. Please suggest some books on this topic. Thank you.Article: 90514
Symon wrote:
>Hi Ray,
>So, why isn't it better to use 'C'/'Matlab'/Perl to generate a .mem file
>that data2mem loads into the previously compiled .bit file? It still meets
>the 'you don't have to touch any of your design files' criterion, but saves
>a P&R each time you change the memory contents.
>Cheers, Syms.
>
>
>
It depends on your application, but if you need to simulate the design
with the data in the memories (as is usually the case if the data is
tables for DSP functions), data2mem is of no help. Data2mem is also one
more tool that has to be run on the design, which I've had trouble with
customers remembering to do if they go back and modify the design. The
point is, there are many ways to do this, and what is best really
depends on your situation.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90515backhus wrote: > Hi Robert, > your first idea appears often in a designers mind, because it works so > well in simulation. But in synthesis the tool is not executing your > code, only analyzing it and looking for synthesizable parts. The rest of > the code will be ignored in the best case or gives you errors and warnings. Actually the synthesis tools execute some of your code: Expressions are evalutated, for and generate loops unrolled, etc. In principle there is nothing that prevents the synthesis tools to execute processes that are only activated once to determine the result. Also, logic that converts text to integers can be described by an rtl netlist and with a little luck redundancy removal will boil it down to a lookup table. Opening files can be handled similar to an "include" statement. But this will not happen before a flip-flop with enable can be written as: if rising_edge(clk) and enable='1' then .... which still is not understood by most synthesis tools. At last years GI workshop there was a paper that used XML/XSLT to convert a load of "unsynthesisable" VHDL constructs into code that even XST considers to be synthesizable. Most of these transformations were really simple. Apparently the tool vendors settled years ago on what should be synthesizable and what shouldn't and now are too lazy to push that border. Kolja SulimmaArticle: 90516
On 2005-10-15, Mika Leinonen <mika.leinonen@tut.fi> wrote: > Have You got any experiences running design software for windowses under > WINE & Linux? The devices I'd like to design for are Lattice > ispLSI1016/1032/E and Xilinx XC9572/XL. > I have ispDesignExpert 8.4 installed for Windows. > And a recent Xilinx Webpack. > For the Xilinx part, ISE Webpack is available for GNU/Linux. They only claim to support only RHEL, but I got it running on Debian. It does seem slower than the Windows version, but it is better than using WINE. Actually the only slow thing about it is the GUI. Darrell Harmon http://dlharmon.comArticle: 90517
I am using a FPGA kit, when I download the bitstream, under windowsXP operating system, I get an error Done did not go high repeatedly. But if I keep everything same, the kit, the cable and the computer and only change the OS to any other version of windows ( 2000, 98 ...etc) the the FPGA configures perfectly, each time. Is there any known issue of compatibility between Xilinxs Impact tool and WindowsXPArticle: 90518
Synplify Pro will move registers across multiplers. I think it won't move registers across instantiated logic. You can dissolve an instantiated primitive back to its model using the attribute syn_hier with value "dissolve", which will allow retiming to take place. Synplify Pro's retiming will maintain an equivalent initial state if your registers have resets. - Ken Simon Heinzle wrote: > Hi everybody! > > Synplify Pro offers Retiming, which allows register relocation across > combinatorial logic. However, this does not work with the embedded 18x18 > multipliers. > > Does anybody know how to make the retiming work, i.e. that Synplify Pro > moves registers accross multipliers? Or does there exist another tool > capable of that? > > Best Regards, > Simon > >Article: 90519
A significant amount of time and expense is involved in making an ASIC. After the ASIC is taped out, masks have to be made and then it has to be manufactured. Modern mask sets can cost upwards of $1 million. The masks are then taken by the manufacturer and they oxidize, implant, anneal, etch, sputter, deposit and polish the wafers according to the various masks that they have. You probably can't do ASIC manufacturing in your lab. ASIC fabs cost billions of dollars to make. It's not something you can do with salvaged parts of a flashlight and a toaster oven. Also, I should mention that you need special tool sets to get an ASIC. You need to get ASIC synthesis tools (not terribly expensive, but still around $25k a seat as far as I understand), timing tools (primetime), layout and clock tree synthesis tools (astro, etc (very expensive)). These tools can easily cost millions of dollars. You also need to buy cell libraries. Artisan is a common developer of these. As for your other question as to porting FPGA RTL to ASIC, yes it's possible as long as it is just RTL. Vendor primitives aren't supported. The problem with this is that RTL development is only part of the time expendature. I develop a small ASIC at work and timing closure is taking months. A big chip can take a really long time. A company I previously worked for (who developed VERY LARGE chips) would take 6+ months to do timing closure. My suggestion would be to talk to Altera about Hard Copy. It is an FPGA to structured ASIC porting service. It is my understanding that they absorb a lot of the cost and you can do all of your development using their standard (couple thousand dollar) tools. You can also take a look at Xilinx EasyPath. They aren't ASICs, but they are a cheaper application specific FPGA option. I can't suggest any really good books on it, because I've never seen a good book on this. I've learned it all through working with people who know it. -Arlen Cox vssumesh wrote: > Please tell me the process involved. Is the ASICS are manufactured in > the big manufacturing places like ordinary ICs. Or is there any way we > can do it in our own lab. I am experianced only with FPGAs. Can we > convert an RTL written for the FPGA to ASIC. Please suggest some books > on this topic. > Thank you.Article: 90520
Hi all, I am new to logic design in general, but I am getting an FPGA development board (the Spartan-3 board from xilinx) and I hope to make a small circuit for connecting to an old microcomputer and some SRAM. For this project, I will need a bunch of (~60) 5V I/O lines, but the FPGA's lines are all 3.3V logic. How do people generally go about handling this sort of thing? It seems ridiculous to put 8-bit data buffers on the lines, as there would be a ridiculous amount of them. Is there a good level converter circuit with loads of I/O lines or some such? Any help would be appreciated! -dsgArticle: 90521
"David Geirsson" <alt.spam@gmail.com> wrote in message news:1129406486.415303.231540@z14g2000cwz.googlegroups.com... > Hi all, > > I am new to logic design in general, but I am getting an FPGA > development board (the Spartan-3 board from xilinx) and I hope to make > a small circuit for connecting to an old microcomputer and some SRAM. > For this project, I will need a bunch of (~60) 5V I/O lines, but the > FPGA's lines are all 3.3V logic. How do people generally go about > handling this sort of thing? It seems ridiculous to put 8-bit data > buffers on the lines, as there would be a ridiculous amount of them. Is > there a good level converter circuit with loads of I/O lines or some > such? > > Any help would be appreciated! > > -dsg > Don't know about Xilinx, but Altera parts generally have multivolt I/O. Some of the older parts, for example the ACEX1k part has I/O which can run at 2.5, 3.3 and 5V at the same time. I would imagine Xilinx would have the same capabilities. SlurpArticle: 90522
Waage wrote: > Has anyone gotten impact to work on Linux with the Platform USB Cable?? > > If so, what version of the kernel were you using? > What, if any debug did you have to do to get it to work? > > I just got the Cable yesterday, and have so far been unable to get > impact > to even find the device. > > I know the drivers are installed and the firmware is loaded. > > Does it really work on Linux? > > Thanks, Chris > I tried and never got it to work ... That really pisses me off actually because // is quite slow when downloading data to SDRAM ... Always get a "write cmdbuffer failed 20000015" in impact ... SylvainArticle: 90523
There are a few ways to do this. Bus switches are the common way especially when you don't want a significant timing penalty. We us these on our development products and you can see 20 bit devices on out Broaddown2 and Mini-Can products. However these are not for the quick knock-up circuit as they are on a 0.4 mm lead pitch. As a bit a plug when using our boards stand-alone the PCI interface on our boards can be used as 50 bit, 5V tolerant, interface using an optional connection module. There are other high bit count devices available as bus switches, or even 5V tolerant logic, but the same problems with non-simple packages will generally occur. We have a module planned that may help with bus switches on-board but probably 10-12 weeks before that is likely to be available. This module will be in DIL format and can be incorporated into stripboards circuits etc for use with anyone's boards. Otherwise you can use resistors to limit the current into the Spartan-3 using the internal protection diodes to limit voltage. If the I/O voltage is set at 3.3V, or higher, then you need to be careful as the limit on the Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this technique you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our products to improve the safety margin. If your board hasn't got Vccio low enough then you can use either schottky diodes, or appropriate zeners to 0V, to cut in before the internal protection diodes do. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 PCI Development Board. http://www.enterpoint.co.uk "David Geirsson" <alt.spam@gmail.com> wrote in message news:1129406486.415303.231540@z14g2000cwz.googlegroups.com... > Hi all, > > I am new to logic design in general, but I am getting an FPGA > development board (the Spartan-3 board from xilinx) and I hope to make > a small circuit for connecting to an old microcomputer and some SRAM. > For this project, I will need a bunch of (~60) 5V I/O lines, but the > FPGA's lines are all 3.3V logic. How do people generally go about > handling this sort of thing? It seems ridiculous to put 8-bit data > buffers on the lines, as there would be a ridiculous amount of them. Is > there a good level converter circuit with loads of I/O lines or some > such? > > Any help would be appreciated! > > -dsg >Article: 90524
> There is a reference EDK project that drives the VGA port at > www.xilinx.com/ml403 . XAPP717 written for the ML403 has a pretty cool > demo too. This link goes to the general ml403 site. I guess you are refering to the ML403 Video Demonstration Design of which, for a beginner, I have several issues. One it say that there are documentation files and source files. There is an MS word DOC file that describes driving a VGA through horizontal and vertical filters from a source thats is stored in a BMP files and somehow converted to bit stream, I guess. As for source files, I don't see anything recognizable. There are some ucf files, I didn't look to see why the three board varieties are different, and .m files and a .mdl fil, don't know what these are. I have VHDL code ready to go developed on a Spartan 3. I don't need FIR filters to get started, Xilinx System Generator, or other stuff. Is there something else you can point me to? Is this where you got started? Brad Smallridge
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z