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Messages from 90525

Article: 90525
Subject: Mixed voltage in JTAG chain.
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 15 Oct 2005 18:27:49 -0700
Links: << >>  << T >>  << A >>
Hi all,
Is it ok to have mixed voltage in the JTAG chain? (say 2.5V and 3.3V).
It seems to be ok from the documentation side but is it fine from the
programming point of view?
Thanks
Subhasri


Article: 90526
Subject: About with Synplify Pro?
From: seabrench@163.com
Date: 15 Oct 2005 19:38:35 -0700
Links: << >>  << T >>  << A >>
Hello everybody!When I use synplify Pro to synthesis,it tells me:
@E:Internal Error
Why?How to solve it?Thanks!


Article: 90527
Subject: Re: 3.3v<->5V
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 15 Oct 2005 19:50:27 -0700
Links: << >>  << T >>  << A >>
On Sun, 16 Oct 2005 00:10:52 +0100, "John Adair"
<loseitintheblackhole@blackholesextreme.co.uk> wrote:

>There are a few ways to do this. Bus switches are the common way especially 
>when you don't want a significant timing penalty. We us these on our 
>development products and you can see 20 bit devices on out Broaddown2 and 
>Mini-Can products. However these are not for the quick knock-up circuit as 
>they are on a 0.4 mm lead pitch. As a bit a plug when using our boards 
>stand-alone the PCI interface on our boards can be used as 50 bit, 5V 
>tolerant, interface using an optional connection module. There are other 
>high bit count devices available as bus switches, or even 5V tolerant logic, 
>but the same problems with non-simple packages will generally occur.
>
>We have a module planned that may help with bus switches on-board but 
>probably 10-12 weeks before that is likely to be available. This module will 
>be in DIL format and can be incorporated into stripboards circuits etc for 
>use with anyone's boards.
>
>Otherwise you can use resistors to limit the current into the Spartan-3 
>using the internal protection diodes to limit voltage. If the I/O voltage is 
>set at 3.3V, or higher, then you need to be careful as the limit on the 
>Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this technique 
>you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our 
>products to improve the safety margin. If your board hasn't got Vccio low 
>enough then you can use either schottky diodes, or appropriate zeners to 0V, 
>to cut in before the internal protection diodes do.
>

We interfaced a 5-volt uP to a Spartan3 with just series resistors. It
worked fine, but the high levels on the logic lines snuck through the
S3 esd diodes and pulled the 3.3 volt supply up to about 3.7. We
scaled down the programming resistors on the 3.3 volt regulator
radically to dump enough supply current and hold the 3.3 down where it
belongs.

John



Article: 90528
Subject: Re: 3.3v<->5V
From: "GPE" <See_my_website_for_email@cox.net>
Date: Sat, 15 Oct 2005 22:27:16 -0500
Links: << >>  << T >>  << A >>

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:dpf3l1t3786r5qor86djqncf2blo1ff3v6@4ax.com...
> On Sun, 16 Oct 2005 00:10:52 +0100, "John Adair"
> <loseitintheblackhole@blackholesextreme.co.uk> wrote:
>
>>There are a few ways to do this. Bus switches are the common way 
>>especially
>>when you don't want a significant timing penalty. We us these on our
>>development products and you can see 20 bit devices on out Broaddown2 and
>>Mini-Can products. However these are not for the quick knock-up circuit as
>>they are on a 0.4 mm lead pitch. As a bit a plug when using our boards
>>stand-alone the PCI interface on our boards can be used as 50 bit, 5V
>>tolerant, interface using an optional connection module. There are other
>>high bit count devices available as bus switches, or even 5V tolerant 
>>logic,
>>but the same problems with non-simple packages will generally occur.
>>
>>We have a module planned that may help with bus switches on-board but
>>probably 10-12 weeks before that is likely to be available. This module 
>>will
>>be in DIL format and can be incorporated into stripboards circuits etc for
>>use with anyone's boards.
>>
>>Otherwise you can use resistors to limit the current into the Spartan-3
>>using the internal protection diodes to limit voltage. If the I/O voltage 
>>is
>>set at 3.3V, or higher, then you need to be careful as the limit on the
>>Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this 
>>technique
>>you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our
>>products to improve the safety margin. If your board hasn't got Vccio low
>>enough then you can use either schottky diodes, or appropriate zeners to 
>>0V,
>>to cut in before the internal protection diodes do.
>>
>
> We interfaced a 5-volt uP to a Spartan3 with just series resistors. It
> worked fine, but the high levels on the logic lines snuck through the
> S3 esd diodes and pulled the 3.3 volt supply up to about 3.7. We
> scaled down the programming resistors on the 3.3 volt regulator
> radically to dump enough supply current and hold the 3.3 down where it
> belongs.
>
> John
>

Curious, Xilinx recommends 300 ohm resistors.  Which ones were you using?

-- Ed




Article: 90529
Subject: Re: 3.3v<->5V
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 15 Oct 2005 20:54:00 -0700
Links: << >>  << T >>  << A >>
On Sat, 15 Oct 2005 22:27:16 -0500, "GPE"
<See_my_website_for_email@cox.net> wrote:

>
>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
>news:dpf3l1t3786r5qor86djqncf2blo1ff3v6@4ax.com...
>> On Sun, 16 Oct 2005 00:10:52 +0100, "John Adair"
>> <loseitintheblackhole@blackholesextreme.co.uk> wrote:
>>
>>>There are a few ways to do this. Bus switches are the common way 
>>>especially
>>>when you don't want a significant timing penalty. We us these on our
>>>development products and you can see 20 bit devices on out Broaddown2 and
>>>Mini-Can products. However these are not for the quick knock-up circuit as
>>>they are on a 0.4 mm lead pitch. As a bit a plug when using our boards
>>>stand-alone the PCI interface on our boards can be used as 50 bit, 5V
>>>tolerant, interface using an optional connection module. There are other
>>>high bit count devices available as bus switches, or even 5V tolerant 
>>>logic,
>>>but the same problems with non-simple packages will generally occur.
>>>
>>>We have a module planned that may help with bus switches on-board but
>>>probably 10-12 weeks before that is likely to be available. This module 
>>>will
>>>be in DIL format and can be incorporated into stripboards circuits etc for
>>>use with anyone's boards.
>>>
>>>Otherwise you can use resistors to limit the current into the Spartan-3
>>>using the internal protection diodes to limit voltage. If the I/O voltage 
>>>is
>>>set at 3.3V, or higher, then you need to be careful as the limit on the
>>>Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this 
>>>technique
>>>you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our
>>>products to improve the safety margin. If your board hasn't got Vccio low
>>>enough then you can use either schottky diodes, or appropriate zeners to 
>>>0V,
>>>to cut in before the internal protection diodes do.
>>>
>>
>> We interfaced a 5-volt uP to a Spartan3 with just series resistors. It
>> worked fine, but the high levels on the logic lines snuck through the
>> S3 esd diodes and pulled the 3.3 volt supply up to about 3.7. We
>> scaled down the programming resistors on the 3.3 volt regulator
>> radically to dump enough supply current and hold the 3.3 down where it
>> belongs.
>>
>> John
>>
>
>Curious, Xilinx recommends 300 ohm resistors.  Which ones were you using?
>
>-- Ed
>
>

180's I think, because we have lots of them in teeny quad packages,
and also because there's lots of capacitance on the uP side of the
bus... multilayer traces all over the place. I guess the Vccio current
of the Spartan was pretty low, too. Actually, it worked fine at 3.7
volts, but it failed our test procedure in the part where we verify
all the power rail voltages.

John




Article: 90530
Subject: Re: About with Synplify Pro?
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 16 Oct 2005 04:28:15 GMT
Links: << >>  << T >>  << A >>
On 15 Oct 2005 19:38:35 -0700, seabrench@163.com wrote:
>Hello everybody!When I use synplify Pro to synthesis,it tells me:
>@E:Internal Error
>Why?How to solve it?Thanks!

Contact Synplicity at www.synplicity.com




Article: 90531
Subject: Re: How to Reduce Interconnects (VDD and VSS)
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 15 Oct 2005 21:38:35 -0700
Links: << >>  << T >>  << A >>
Hey everyone, thanks for the tips! Some follow up questions - I only
have the 2 SDRAM (16Mx16) Micron IC's left to route, so I thought I
would ask for advice. They are right up against the FPGA (Cyclone
EP1C12Q240 - QFP), with the long side against the long side of the FPGA
(as opposed to 'standing up') - I was thinking since I can choose pin
placement on the FPGA, I could route every other FPGA pin to the side
of the RAM facing closest to the FPGA, and then the alternate pins on
the bottom layer (4 layer board) under the SDRAM to the side further
away from the FPGA. Since it's only a 4-layer, getting decoupling may
be tricky with this way, but I'm using 0402's, so it may work. Also, is
there a specific FPGA pin I should use for the clock, and should I
buffer it? I have 2 modules, one of the top side of the FPGA, one on
the bottom, and they aren't sharing any signals. I suppose you could
argue that I should share address/control lines to form a x32 bus, but
I have the pins to spare and it saves on complexity. I'm not sure if it
would be possible on a 4-layer also (or is it?).

Any thoughts?


Article: 90532
Subject: Implementing I2C master
From: "Giox" <giovanniparodi79@yahoo.it>
Date: 16 Oct 2005 02:30:52 -0700
Links: << >>  << T >>  << A >>
HEllo everybody, I'm interested in the implementation of a master I2C
controller on a FPGA. I found some implementation of I2C controller on

the WEB (Opencores  for example), but I would like to find something
that fits only the master role. I don't need the code but I will

appreciate any document, link to web site that talks about this
specific aspect of I2C and that proposes simplified version of FSM that


controls the system.
Thanks.


Article: 90533
Subject: Re: Implementing I2C master
From: "PeteS" <ps@fleetwoodmobile.com>
Date: 16 Oct 2005 02:42:18 -0700
Links: << >>  << T >>  << A >>
I2C was invented by Philips.

You can download the specification here:

http://www.semiconductors.philips.com/markets/mms/protocols/i2c/

Cheers

PeteS


Article: 90534
Subject: Re: How to Reduce Interconnects (VDD and VSS)
From: "PeteS" <ps@fleetwoodmobile.com>
Date: 16 Oct 2005 02:51:14 -0700
Links: << >>  << T >>  << A >>
The critical length match for SDRAM is data, data strobe and clock.
Although the address has specific length match rules, the tightest
constraints are timing for the data phase.

Without knowing what SDRAM and what speed you are running, I can't give
specific advice about routing or routing rules.

Cheers

PeteS


Article: 90535
Subject: Re: Mixed voltage in JTAG chain.
From: "PeteS" <ps@fleetwoodmobile.com>
Date: 16 Oct 2005 03:01:54 -0700
Links: << >>  << T >>  << A >>
You can have mixed voltages provided you make sure you don't exceed the
higher one.

Take a simple two device chain where one device is 3.3V and one is 2.5V
(View in fixed font)

             3.3V                             2.5V

TDI ------->[    ] TDO ----[ 1k ]-------> TDI [  ] TDO --------------->
                                   ||
                                   || 2.2k
                                   -- Ground

Where each device must also have TMS and TCK (programmable devices
rarely have TRST).

You could pull each of TMS and TCK from 2.5V (a valid high to a 3.3V
device) and provide programmer power reference from the 2.5, provided
the *last* object in the chain is 2.5V (because the output will drive
to it's VCCIO voltage)

You will also need to convert the TDO -> TDI line when going *from* a
3.3V device *to* a 2.5V device. A simple resistor divider works fine (a
series 1k resistor on the output of TDO and a 2.2k resistor to ground
after that (on the lower voltage device TDI pin) would do it.

Don't attempt to drive the TDI pin directly with the 3.3V as you will
very probably damage both the input and the previous output (much
depends on the tolerance of the device - see the datasheet for
details).

Cheers

PeteS


Article: 90536
Subject: Re: 3.3v<->5V
From: Kolja Sulimma <news@sulimma.de>
Date: Sun, 16 Oct 2005 12:04:12 +0200
Links: << >>  << T >>  << A >>
David Geirsson wrote:
> Hi all,
> 
> I am new to logic design in general, but I am getting an FPGA
> development board (the Spartan-3 board from xilinx) and I hope to make
> a small circuit for connecting to an old microcomputer and some SRAM.
> For this project, I will need a bunch of (~60) 5V I/O lines, but the
> FPGA's lines are all 3.3V logic. How do people generally go about
> handling this sort of thing? It seems ridiculous to put 8-bit data
> buffers on the lines, as there would be a ridiculous amount of them. Is
> there a good level converter circuit with loads of I/O lines or some
> such?

Others allready mentioned that series resistor are a way to do it if you
do not need the highest speeds.
Let me add that you can stay fully TTL compliant by this approach
because 5V TTL only requires you to drive the outputs to 2.4V with a drive
strength of 2mA. You can add 1k or more to each pin and still meet that
requirement.

Kolja Sulimma

Article: 90537
Subject: Re: Storing a file onto FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Sun, 16 Oct 2005 04:01:47 -0700
Links: << >>  << T >>  << A >>
Hi Erik, Ray,
OK, simulation is a good reason! I was thinking about DSP apps where I tend 
to simulate to make sure the VHDL works, but often don't simulate the VHDL 
for every single different filter I design; I prefer to simulate just the 
DSP with Matlab or something similar.
The design flow where I use data2mem is when I want to tweak the performance 
of a dsp filter (say) but don't need or want to wait for a P&R cycle each 
time. Once everything is working I do go back and paste the data directly 
into the VHDL so that subsequent builds don't require the data2mem thingy.
So, as you both say, horses for courses!!
Thanks guys, Syms. 



Article: 90538
Subject: Re: 3.3v<->5V
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sun, 16 Oct 2005 12:12:48 +0100
Links: << >>  << T >>  << A >>
Ignoring the possible issues with slow edge you can increase the value to 
reduce the current. Just slows down how fast the interface can run. Using 
the simplist 2.2RC (did I remenber right) as you transition time you can 
balance your values against speed.

To avoid lifting supplies you can add a ballast load(resistor) or use a 
push-pull regulator like we use on sodimm reference voltages(LP2996).

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 PCI Development 
Board.
http://www.enterpoint.co.uk

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:oaj3l15om52eg9fismg1ivq9is3msf846m@4ax.com...
> On Sat, 15 Oct 2005 22:27:16 -0500, "GPE"
> <See_my_website_for_email@cox.net> wrote:
>
>>
>>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in 
>>message
>>news:dpf3l1t3786r5qor86djqncf2blo1ff3v6@4ax.com...
>>> On Sun, 16 Oct 2005 00:10:52 +0100, "John Adair"
>>> <loseitintheblackhole@blackholesextreme.co.uk> wrote:
>>>
>>>>There are a few ways to do this. Bus switches are the common way
>>>>especially
>>>>when you don't want a significant timing penalty. We us these on our
>>>>development products and you can see 20 bit devices on out Broaddown2 
>>>>and
>>>>Mini-Can products. However these are not for the quick knock-up circuit 
>>>>as
>>>>they are on a 0.4 mm lead pitch. As a bit a plug when using our boards
>>>>stand-alone the PCI interface on our boards can be used as 50 bit, 5V
>>>>tolerant, interface using an optional connection module. There are other
>>>>high bit count devices available as bus switches, or even 5V tolerant
>>>>logic,
>>>>but the same problems with non-simple packages will generally occur.
>>>>
>>>>We have a module planned that may help with bus switches on-board but
>>>>probably 10-12 weeks before that is likely to be available. This module
>>>>will
>>>>be in DIL format and can be incorporated into stripboards circuits etc 
>>>>for
>>>>use with anyone's boards.
>>>>
>>>>Otherwise you can use resistors to limit the current into the Spartan-3
>>>>using the internal protection diodes to limit voltage. If the I/O 
>>>>voltage
>>>>is
>>>>set at 3.3V, or higher, then you need to be careful as the limit on the
>>>>Spartan-3 I/O is 4.05V. 3.3V + 0.7(diode) = 4V. Usually with this
>>>>technique
>>>>you drop the I/O voltage slightly to 3.0-3.2V as we do on most of our
>>>>products to improve the safety margin. If your board hasn't got Vccio 
>>>>low
>>>>enough then you can use either schottky diodes, or appropriate zeners to
>>>>0V,
>>>>to cut in before the internal protection diodes do.
>>>>
>>>
>>> We interfaced a 5-volt uP to a Spartan3 with just series resistors. It
>>> worked fine, but the high levels on the logic lines snuck through the
>>> S3 esd diodes and pulled the 3.3 volt supply up to about 3.7. We
>>> scaled down the programming resistors on the 3.3 volt regulator
>>> radically to dump enough supply current and hold the 3.3 down where it
>>> belongs.
>>>
>>> John
>>>
>>
>>Curious, Xilinx recommends 300 ohm resistors.  Which ones were you using?
>>
>>-- Ed
>>
>>
>
> 180's I think, because we have lots of them in teeny quad packages,
> and also because there's lots of capacitance on the uP side of the
> bus... multilayer traces all over the place. I guess the Vccio current
> of the Spartan was pretty low, too. Actually, it worked fine at 3.7
> volts, but it failed our test procedure in the part where we verify
> all the power rail voltages.
>
> John
>
>
> 



Article: 90539
Subject: Re: Anyone remember the really early Xilinx FPGAs?
From: "Symon" <symon_brewer@hotmail.com>
Date: Sun, 16 Oct 2005 04:20:17 -0700
Links: << >>  << T >>  << A >>
"Peter Alfke" <alfke@sbcglobal.net> wrote in message 
news:1129336777.379304.117620@g14g2000cwa.googlegroups.com...
> "Second source" seems to be a forgotten word now, and the world is a
> better place without it.
Hi Peter,
I still try to write as much 'portable' VHDL as possible, and keep any 
device specific stuff in separate files. It gives the designer a 'virtual' 
second source, and at least gives a bit of a bargaining chip while 
discussing pricing!
Cheers, Syms. 



Article: 90540
Subject: Re: Mixed voltage in JTAG chain.
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sun, 16 Oct 2005 12:30:13 +0100
Links: << >>  << T >>  << A >>
If you are looking at something like a Spartan-3 at 2.5V with say Platform 
Flash devices then you really want to put series resistors in line to the
inputs of the Spartan-3.

Alternatively if you have control of your 3.3V supply and can make it, and 
live with it, at 3.0V then providing your 2.5V is than, or greater, then the
protection diodes should not operate and you can get away without the 
resistors.

As as stated elsewhere, and if you have the option, you can run the whole 
chain at 2.5V. Just be careful that your programming cable is happy with
this. Some are not happy at all at 2.5V and some become intermittant at 2.5V 
as we have found testing competitor cables with some of our products. I will 
state for the record that this issue does not occur with our own cables that 
we now supply with all of our development board products. We have also moved 
all our FPGA JTAG chains to 3.0V-3.3V, with resistors, to allow better 
reliability with non-Enterpoint JTAG cables.

John Adair
Enterpoint Ltd. - Soon to be home of Broaddown4. The Ultimate Virtex4 
Development Board.
http://www.enterpoint.co.uk


> Hi all,
> Is it ok to have mixed voltage in the JTAG chain? (say 2.5V and 3.3V).
> It seems to be ok from the documentation side but is it fine from the
> programming point of view?
> Thanks
> Subhasri
>

"Subhasri krishnan" <subhasri.krishnan@gmail.com> wrote in message 
news:1129426069.884050.22650@z14g2000cwz.googlegroups.com...
> Hi all,
> Is it ok to have mixed voltage in the JTAG chain? (say 2.5V and 3.3V).
> It seems to be ok from the documentation side but is it fine from the
> programming point of view?
> Thanks
> Subhasri
> 



Article: 90541
Subject: Re: Anyone remember the really early Xilinx FPGAs?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sun, 16 Oct 2005 12:52:34 +0100
Links: << >>  << T >>  << A >>
Mike

If get this all together I won't mind a copy. I have some of our free 
seminars to present next month and this as an intro to near virgin FPGA 
users is always useful. I do remember a lot of this being a veteran since 
the early 3064/90 days and pushing the technology to about 50MHz which was 
very fast in those days. 50MHz now rates as near DC in my design book 
nowadays. However given the number of FPGA devices and projects I have been 
involved in over the years, or maybe it was centuries, I wouldn't like to 
rely on my memory on what happened when and where.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Mike" <almost_rational@yahoo.co.uk> wrote in message 
news:1129233880.118922.55800@g44g2000cwa.googlegroups.com...
> Hi all,
>
> I'm trying to put together a picture of how Xilinx FPGAs evolved, from
> the XC2000 series up to the latest Virtex-4. Finding information on the
> early series is nigh impossible, however, so if anyone remembers the
> XC2000/3000 series and can answer *any* of the questions below, it'd be
> much appreciated!
>
> 1) When first introduced in 1985, which of the XC2000-series devices
> (2064, 2018) were actually made available?
>
> 2) When first introduced in 1987, which of the five XC3000-series
> devices (i.e. 3020, 3030, 3042, 3064 and 3090) were actually available?
> When did the 3090 finally arrive?
>
> 3) What year were each of the XC3000A, XC3000L and XC3100 families
> introduced in?
>
> Thanks,
>
> Mike
> 



Article: 90542
Subject: Best Async FIFO Implementation
From: "Davy" <zhushenli@gmail.com>
Date: 16 Oct 2005 07:15:33 -0700
Links: << >>  << T >>  << A >>
Hi all,

Does there exist a best implementation of Asynchronous FIFO?

Any suggestions will be appreciated!
Best regards,
Davy


Article: 90543
Subject: Re: Best Async FIFO Implementation
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sun, 16 Oct 2005 16:36:37 +0200
Links: << >>  << T >>  << A >>
Davy wrote:
> Hi all,
> 
> Does there exist a best implementation of Asynchronous FIFO?
> 
> Any suggestions will be appreciated!
> Best regards,
> Davy

I guess it depends on what you're looking for.
At minimum, it should *work* ...
Then the rest is a compromise of resources/speed/feature(like almost
empty/full flags,...)/...(reliability?)


	Sylvain

Article: 90544
Subject: Re: How to Reduce Interconnects (VDD and VSS)
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 16 Oct 2005 08:39:04 -0700
Links: << >>  << T >>  << A >>
I am using Microns MT48LC16M16A2P-75 part. Trace lengths are well below
2", but if I position the ram in the fashion that I mentioned (with the
long side parallel to the FPGA), length matching won't be possible for
the data bus since it is located on both sides of the SDRAM. What kind
of tolerance is normally used when lengt matching?


Article: 90545
Subject: Re: Best Async FIFO Implementation
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 16 Oct 2005 11:33:17 -0700
Links: << >>  << T >>  << A >>
All members of the Virtex-4 family from Xilinx have a
(hard-coded=full-custom) FIFO controller in each of their BlockRAMs. It
accepts different clocks for read and write (called "asynchronous
operation") at any frequency up to 500 MHz. Capacity is 18 Kbits, the
width is 4 to 36 bits, and the depth is accordingly from 4K to 512
addresses (depth and width can easily be expanded with additional
BlockRAMs)
There is an  EMPTY and a FULL flag, and also an ALMOST EMPTY and an
ALMOST FULL flag, both fully programmable (with 1-address granularity).

I designed the crucial asynchronous empty arbitration logic, and it
works perfectly: We tested it by writing data at ~200 MHz into the
FIFO, and reading it out at ~500 MHz, and the asynchrous empty-detect
logic had worked flawlessly for all those >10e14 operations when we
stopped the test after a week.
No real FIFO application will probably ever go empty 200 million times
a second...
The high performance is due to very fast and compact full-custom logic,
and our long experience in analyzing and dealing with the effects of
metastability.

Peter Alfke, Xilinx Applications (posting from home)


Article: 90546
Subject: Re: Best Async FIFO Implementation
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 17 Oct 2005 09:06:39 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> All members of the Virtex-4 family from Xilinx have a
> (hard-coded=full-custom) FIFO controller in each of their BlockRAMs. It
> accepts different clocks for read and write (called "asynchronous
> operation") at any frequency up to 500 MHz. Capacity is 18 Kbits, the
> width is 4 to 36 bits, and the depth is accordingly from 4K to 512
> addresses (depth and width can easily be expanded with additional
> BlockRAMs)
> There is an  EMPTY and a FULL flag, and also an ALMOST EMPTY and an
> ALMOST FULL flag, both fully programmable (with 1-address granularity).
> 
> I designed the crucial asynchronous empty arbitration logic, and it
> works perfectly: We tested it by writing data at ~200 MHz into the
> FIFO, and reading it out at ~500 MHz, and the asynchrous empty-detect
> logic had worked flawlessly for all those >10e14 operations when we
> stopped the test after a week.

Why stop after 1 week ?. Sounds like the sort of app nice to have
spinning in the corner of the lab forever....
Did you also test the full detect, or is that expected to be the same
by symmetry ?

> No real FIFO application will probably ever go empty 200 million times
> a second...
> The high performance is due to very fast and compact full-custom logic,
> and our long experience in analyzing and dealing with the effects of
> metastability.

So does that mean devices without this full-custom logic, can expect
lower performance, and if so, how much lower ?
[eg Spartan 3 / 3E ?]



-jg


Article: 90547
Subject: Re: How to Reduce Interconnects (VDD and VSS)
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 16 Oct 2005 13:56:48 -0700
Links: << >>  << T >>  << A >>
woops, I totally forgot the speed - 133 MHz max, but 100 Mhz most
likely.


Article: 90548
Subject: Error (XST): translate terminal to FCT
From: "Pasacco" <pasacco@gmail.com>
Date: 16 Oct 2005 14:49:40 -0700
Links: << >>  << T >>  << A >>
Dear

During synthesizing in XST of ISE 6.3, following error (?) is
encountered....

Does anyone have experience on this trouble?

Thankyou for information in advance

----------------

failed to translate terminal to FCT

$n0133[7] =
If $n0243 Then $n0297[7]
If $n0245 Then $n0299[7]
If $n0247 Then $n0301[7]
If $n0249 Then $n0303[7]
If $n0251 Then $n0305[7]
If $n0253 Then $n0307[7]
If $n0255 Then $n0309[7]
If $n0310 Then address[7]
Default <u>0
-->

Total memory usage is 58984 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Article: 90549
Subject: Re: Best Async FIFO Implementation
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 16 Oct 2005 15:30:22 -0700
Links: << >>  << T >>  << A >>
Hi, Jim..
We stopped after a week because we were satisfied. In one week, we
proved 10e14, it would take 10 weeks to prove 10e15, and 2 years to
prove 10e16. Diminishing returns...But we definitely did NOT stop
because we found an error. No cheating on my watch!

For some strange reason (fixed in "Virtex-5") there is a
one-clock-pulse latency for FULL. I suggest using ALMOST FULL instead.
FULL is not as important as EMPTY, since a properly designed system
should never overflow the FIFO, whereas it might be nice to empty it
completely. (I often use the savings-account analogy).

Yes, using the fabric to implement the FIFO controller might limit the
speed to 250 MHz.
The reasons for the "hard" FIFO controller were:
Higher performance, guaranteed reliable operation without user
involvement, and saving fabric resources as well as power consumption.
The same reasoning will be used for future "hard" subfunctions. It's
the best way to increase speed, functionality, and user-friendliness.
How else can we improve by a factor 2 or even more?
Peter Alfke




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